JP3242297B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device capable of displaying video signals having different resolutions on a display screen, and more particularly to a horizontally long TV having an aspect ratio of 9:16 for converting a video signal having an aspect ratio of 3: 4. The present invention relates to an apparatus for displaying a screen on a liquid crystal display device.

[0002]

2. Description of the Related Art As a driving method for displaying a TV [TeleVision] image or an image output from a computer on a liquid crystal display device, an active matrix driving method with high display quality is widely used. As shown in FIG. 11, the liquid crystal display device of the active matrix drive system includes a liquid crystal panel 1, a source driver 2 and a gate driver 3 for driving the liquid crystal panel. Although not shown, the liquid crystal panel 1 includes a dot electrode substrate and a counter electrode substrate,
On the dot electrode substrate, a large number of source lines connected to the source driver 2 are formed in the X direction, and a large number of gate lines connected to the gate driver 3 are formed in the Y direction. A dot electrode is formed in each of the rectangular regions. Each intersection of the source line and the gate line is provided with a TFT [Thin Film Tra
A switching element such as an nsistor] is provided, and each dot electrode is connected to an adjacent source line via the switching element. Further, a transparent counter electrode is formed on the counter electrode substrate, and the dot electrode substrate and the counter electrode substrate are arranged to face each other via a liquid crystal layer.

A source driver 2 sequentially takes in image data for each of the three primary colors RGB (R: red, G: green, B: blue) in a video signal VS in serial according to a clock signal CLK, and sends a horizontal synchronization signal HSYNC. Each time the image data is received, these image data are output in parallel and a gradation voltage is applied to each source line. The gate driver 3 applies a gate voltage to any one of the gate lines. Each time the horizontal synchronization signal HSYNC is sent, the gate driver 3 sequentially switches the gate line to which the gate voltage is applied, and sends the vertical synchronization signal VSYNC. The scanning is carried out by returning to the first gate line and repeating this operation each time it is received. Thus, the horizontal synchronizing signal HSYN
When a gray scale voltage of image data is applied to each source line in each cycle of C, and when a gate voltage is applied to any one of the gate lines, all the switching elements of the gate line are turned on and each source line is turned on. The upper gradation voltage is sent to each dot electrode. Then, the liquid crystal layer between each of the dot electrodes and the counter electrode changes the light transmittance according to the gradation voltage, so that the light emitted from the backlight is cut off according to the light transmittance and the gradation display is performed. Is performed. By repeating this for all the gate lines in each cycle of the vertical synchronization signal VSYNC, an arbitrary image can be displayed on the display screen of the liquid crystal panel 1. Each pixel on the display screen of the liquid crystal panel 1 has a three-primary RGB filter disposed therein.
Since each pixel is constituted by a plurality of dot electrodes, a color display of this image is possible by controlling the gradation of the image data of three colors of each pixel.

[0004]

In the liquid crystal display device having the above configuration, the number of image data of one line of each color of the video signal VS inputted during one cycle of the horizontal synchronization signal HSYNC is equal to the source line of the liquid crystal panel 1. , Ie, the number of pixels of one line, and the number of lines of image data input during one cycle of the vertical synchronization signal VSYNC does not match the number of gate lines, ie, the number of scanning lines. All of the image of the signal VS cannot be displayed on the entire display screen of the liquid crystal panel 1. However, for example, an aspect ratio of 9: 1
6 horizontal TV screen is a normal TV with an aspect ratio of 3: 4.
Compared with the V screen or the output screen of the computer, the number of pixels in one line is different even though the number of scanning lines is the same.

For this reason, conventionally, when such an image signal for a display screen having an aspect ratio of 3: 4 is to be reproduced and displayed on a liquid crystal display device having a landscape TV screen having an aspect ratio of 9:16, the line signal in the line direction is required. Since the number of pixels is insufficient, the left and right quarters of the display screen are not used, which causes an unnatural screen. In addition, if a liquid crystal display device having a normal display screen with an aspect ratio of 3: 4 must be separately prepared for this reason, there is a problem that waste is increased.

By the way, various techniques for reproducing and displaying such video signals VS having different aspect ratios on a display screen have already been developed.

For example, Japanese Patent Application Laid-Open No. 6-149194 discloses that a video signal is sampled with a reference clock signal, converted into digital signal image data, and the image data is temporarily stored in a memory and then higher than the reference clock signal. An invention is described in which a read operation is sequentially performed by a clock signal of a frequency and the same line is read twice at an appropriate interval to correct a distortion of an aspect ratio generated when an attempt is made to obtain a high horizontal resolution. However, according to the present invention, the aspect ratio is changed by increasing the number of scanning lines by interpolation. Therefore, an image having the same number of scanning lines but different only in the number of pixels of one line, for example, an image having an aspect ratio of 3: 4. The signal has an aspect ratio of 9:16
This cannot be applied to the case of displaying on a horizontally long TV screen.

In Japanese Patent Application Laid-Open No. Hei 6-31486, an image signal having a smaller number of scanning lines than that of a display screen is directly subjected to A / D conversion by sampling the image signal with a clock signal having a lower frequency than the original. An invention is described in which an image can be prevented from being displayed horizontally in a case, and display can be performed with a correct aspect ratio.
However, the present invention is, for example, originally 640 pixels × 4
A video signal to be displayed on a display screen of 00 lines is to be displayed in a range of 533 pixels × 400 lines which is a part of the display screen of 640 pixels × 480 lines,
This does not mean that video signals having different aspect ratios are displayed on the entire display screen without discomfort.

Further, Japanese Patent Application Laid-Open No. 3-109681 discloses that image data held adjacently on a line memory is weighted and averaged and sequentially read out while linearly interpolating the data. An invention capable of arbitrarily converting the number of pixels is described. Japanese Patent Application Laid-Open No. 3-278970 discloses that the number of pixels in one line of a video signal is calculated by performing linear interpolation on a two-dimensional plane in the horizontal and vertical directions based on image data held in a frame buffer. And an invention that can arbitrarily convert the number of scanning lines. According to these inventions, a video signal having an arbitrary aspect ratio can be reproduced and displayed on the entire display screen having another aspect ratio. However, in these inventions, since a calculation device for performing high-speed and complicated interpolation calculation is required, there is a problem that the image display device becomes expensive and large.

The present invention has been made in view of the above circumstances, and provides an image display device capable of easily performing an aspect ratio conversion using a simple circuit by partially using image data. It is an object.

[0011]

According to the image display device of the present invention (claim 1), each pixel constituting the display screen is composed of R pixels.
What is claimed is: 1. An image display device comprising three display dots corresponding to each of the three primary colors of GB, wherein each of four or more display dots adjacent to each other in a horizontal direction on a display screen is a pseudo pixel. A signal processing circuit is provided for supplying image data corresponding to each pixel of the video signal.

[0012] The signal processing circuit includes: three or more display dots of different colors among four or more display dots of each pseudo pixel;
Image data of a color corresponding to each of the three display dots of each pixel in the video signal is assigned, and a color corresponding to the remaining display dot of the pixel is assigned to each of the remaining display dots of the pseudo pixel. To generate an internal video signal to which the above image data is assigned in a redundant manner. Thereby, the above object is achieved.

According to a second aspect of the present invention, in the image display device according to the first aspect, an image memory for storing image data of each color in a first-in first-out manner, and an image memory of each color serially input are stored in the image data. Writing control means for sequentially storing the image data in the image memory in accordance with an external clock signal synchronized with the internal clock signal, and sequentially taking out the image data of each color from the image memory in accordance with the internal clock signal, and periodically taking out the image data for each color And read control means for performing the read operation.

According to a third aspect of the present invention, in the image display apparatus according to the second aspect, the read control unit is configured to fetch image data from the image memory once every four times at a different timing for each color. It is configured to stop.

The operation will be described below.

In the present invention (claim 1), when the number of pixels in one line of the display screen is larger than the number of pixels in one line of the video signal, three pieces of image data of each pixel of the video signal are partially Are assigned to four or more display dots of each corresponding pseudo pixel on the display screen so that the number of pseudo pixels in one line of the display screen matches the actual number of pixels in one line of the video signal. The generated internal video signal can be generated, and the image of the video signal can be reproduced and displayed on display screens having different aspect ratios without a sense of incongruity. Moreover, in this case, the number of pixels is not increased by linear interpolation, but the same image data is assigned redundantly, so that the number of display dots constituting the pixel (pseudo pixel) is increased so that the substantial number of pixels is increased. Since it is performed, complicated arithmetic processing such as interpolation calculation becomes unnecessary.

Further, in the present invention (claim 2),
The image data is stored in the image memory as usual by the writing control means, but the reading control means periodically stops taking out the image data from the image memory. The data extracted immediately before is used redundantly, and three or more pieces of image data can be overlapped by one or more to increase to four or more. Therefore, if it is considered that the pseudo pixels are composed of four or more display dots, the number of pseudo pixels in one line of the display screen is smaller than the original number of pixels. Will be able to

Further, in the present invention (claim 3),
Since the readout control unit stops taking out the image data from the image memory once every four times, the three image data can be overlapped by one and increased to four. Therefore, the number of pseudo pixels in one line of the display screen is ／ of the original number of pixels.
The video signal having the aspect ratio of 3: 4 can be displayed on the landscape TV screen having the aspect ratio of 9:16.

[0019]

Embodiments of the present invention will be described below.

1 to 10 show an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a liquid crystal display device, FIG. 2 is a block diagram showing a configuration of a signal processing circuit,
3 is a time chart showing a configuration of a video signal, FIG. 4 is a time chart showing an operation of writing image data in a signal processing circuit, FIG. 5 is a block diagram showing a configuration of a read timing adjustment circuit, and FIG. 6 is a read timing adjustment circuit. 7 is a time chart showing an operation of reading image data in the signal processing circuit, and FIG. 8 is a diagram showing image data when a video signal is displayed on a display screen having an aspect ratio of 3: 4. FIG. 9 is a diagram showing image data when an internal video signal is displayed on a liquid crystal panel having an aspect ratio of 9:16, and FIG. 10 is a time chart showing the configuration of the internal video signal.

In the image display device of the present embodiment, a case will be described in which a video signal VS for a display screen having an aspect ratio of 3: 4 is displayed on a liquid crystal display device having a landscape TV screen having an aspect ratio of 9:16. As shown in FIG. 1, this liquid crystal display device is an active matrix drive type image display device including a liquid crystal panel 1, a source driver 2 and a gate driver 3 for driving the liquid crystal panel. These liquid crystal panel 1, source driver 2 and gate driver 3
The configuration is the same as that shown in FIG. However, the liquid crystal panel 1 has a landscape TV screen with an aspect ratio of 9:16. Therefore, the number of pixels in one line of the video signal that the liquid crystal panel 1 originally displays is 4/3 times the video signal VS having the aspect ratio of 3: 4.

The above liquid crystal display device has an aspect ratio of 3:
The video signal VS for the display screen of No. 4 has an aspect ratio of 9: 1.
6 is provided with a signal processing circuit 4 for converting into an internal video signal INVS for a landscape TV screen. The signal processing circuit 4 receives the video signal VS and generates an internal video signal INVS in which only the number of pixels in one line is increased by 4/3 while keeping the number of scanning lines unchanged, thereby converting the aspect ratio. Is what you do. And for this conversion process,
An external clock signal EXCLK synchronized with the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the video signal VS;
An internal clock signal INCLK different from the external clock signal EXCLK is input. Further, in order to drive the liquid crystal panel 1, the internal video signal I generated by the conversion process is used.
NVS, horizontal synchronization signal HSYNC, and internal clock signal I
NCLK is sent to the source driver 2 and a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC are sent to the gate driver 3.

The signal processing circuit 4 comprises three field memories 41 to 43, a timing generation circuit 44, and a read timing adjustment circuit 45, as shown in FIG. Each of the field memories 41 to 43 has a first-in first-out method (FIF) having a memory capacity of one field.
O [First In First Out]) image memory, which sequentially writes and holds image data of each of the three primary colors RGB of the video signal VS in accordance with the external clock signal EXCLK, and sequentially stores the held image data in accordance with the internal clock signal INCLK. It can be read. When writing these image data, the write address is automatically updated, and when reading the image data, the read address is automatically updated. The timing generation circuit 44 receives the vertical synchronizing signal VSY.
NC, horizontal synchronization signal HSYNC, and external clock signal EX
CLK, these field memories 41 to 4
3 generates a write enable signal WE for permitting writing and holding of image data, a write reset signal WRST for returning a write address to an initial address, a vertical synchronizing signal VSYNC and a horizontal synchronizing signal H.
Based on the SYNC and the internal clock signal INCLK, a read enable signal RE for allowing these field memories 41 to 43 to read image data and a read reset signal RRST for returning the read address to the initial address are generated.

Here, the video signal VS is, for example, VESA
[Video Electronics Standard Association] Standard VG
It is assumed that the signal is an A [Video Graphics Array] signal (640 pixels × 480 lines). Therefore, as shown in FIG. 3, this video signal VS has one cycle of the vertical synchronizing signal VSYNC of 5 cycles.
25H (1H is one cycle of the horizontal synchronizing signal HSYNC), of which valid image data in the vertical direction is inserted during a period of 480H. Also, the external clock signal EXCL
Assuming that the cycle of K is tEX, 1 of the horizontal synchronization signal HSYNC
H becomes 800 tEX. During this period, the horizontal synchronization signal HSYNC becomes L level during a period of 96 tEX, and effective horizontal image data of the video signal VS is inserted during a period of 640 tEX. Then, the write enable signal WE becomes H level (active) during a period of 640 tEX in which effective image data in the horizontal direction of the video signal VS is inserted.

Accordingly, as shown in FIG. 4, after several tens of H have passed since the vertical synchronizing signal VSYNC became L level and the vertical scanning period was started, as shown in FIG. Begins to be entered. Then, the write enable signal WE becomes H level (active) during the period of valid image data in the horizontal direction within each 1H period of the period of valid image data in the vertical direction. The write reset signal WRST is
The write enable signal WE becomes H level (active) only once before it first becomes H level within the vertical scanning period, and the write addresses of the field memories 41 to 43 are returned to the initial values. Write enable signal WE
Becomes H level, the video signals VSR, VSG, V
The image data of each pixel (R0, G
0, B0, etc.) in order, so that the field memory 4
1 to 43 write and store these image data at the rising timing of the external clock signal EXCLK. Then, the writing operation of the image data is repeated while sequentially updating the writing address, thereby holding the image data for one frame.

Read timing adjustment circuit 45 shown in FIG.
Is a circuit that generates read enable signals RR, REG, and REB for each color based on the internal clock signal INCLK and the read enable signal RE from the timing generation circuit 44. This read timing adjustment circuit 4
5 is provided with a counter 45a as shown in FIG. The counter 45a is a 4-bit hexadecimal counter, and has an internal clock signal INC input to the clock terminal.
The counting is performed each time LK rises, and the counting result is output from output terminals QA to QD (only the lower two bits of output terminals QA and QB are shown in the figure). The enable terminals EP and ET are both set to the H level to always be in a countable state, and the input terminals A to D have an initial value of CH (H indicates hexadecimal notation), that is, 1100B (B is 2 (Shown in hexadecimal notation) is loaded. Also, the load terminal L
The output of the ripple carrier terminal RC via the inverter 45b and the read enable signal RE are output to OAD.
The input is made via the ND gate 45c. Therefore, as shown in FIG. 6, while the read enable signal RE is at the H level (active), the counter 45a counts according to the internal clock signal INCLK, and outputs the output terminals QA to QD to CH to FH (11).
11B) is repeatedly output in order.

The read timing adjustment circuit 45 includes three D flip-flops 45d to 45d, as shown in FIG.
5f. These D flip-flops 45d
45f configures a three-stage shift register by commonly inputting the internal clock signal INCLK via the inverter 45g to the clock terminal and connecting the output terminal Q between them to the input terminal D. A read enable signal RE is commonly input to the clear terminal CLR, and the shift operation can be performed only when the read enable signal RE is at the H level.
Further, another D flip-flop 45 latching the read enable signal RE with the internal clock signal INCLK.
The output of the inverted output terminal Q bar of h and the read enable signal RE are commonly input to the preset terminals PR of these D flip-flops 45d to 45f via the NAND gate 45i. For this reason, as shown in FIG.
When the read enable signal RE goes to the H level, the output P of the NAND gate 45i is thereafter set only for 1/2 tIN.
Since RST is at L level, D flip-flops 45d to 45f are all preset to H level. A data input D of a first-stage D flip-flop 45d of the shift register shown in FIG.
And the output of the output terminal QB of the counter 45a via the inverter 45j is input via the NAND gate 45k. This NAND gate 4
The output of 5k becomes L level only when the output values of the output terminals QA to QD of the counter 45a are DH (1101B), that is, when the output terminal QA is at H level and the output terminal QB is at L level. Then, the D flip-flops 45d to 45d of the respective stages
5f output terminal Q from each color read enable signal R
ER, REG, and REB are output.

Read timing adjustment circuit 45 having the above configuration
As shown in FIG. 6, when the read enable signal RE goes high, the output PRS of the NAND gate 45i
T goes low once and all the read enable signals RER, REG, REB for each color go high,
According to the internal clock signal INCLK, the values of CH to FH are repeatedly output from the output terminals QA to QD of the counter 45a in order. Each time the output of the output terminals QA to QD becomes DH, the falling edge of the internal clock signal INCLK causes the first stage D flip-flop 45d to output the NAND gate 4D.
The L level output of 5k is latched, and the red read enable signal RER is set to the L level for a period of 1 tIN.
Since the L level is sequentially shifted to the D flip-flops 45e and 45f every 1 tIN, the green read enable signal REG is supplied during the next 1 tIN.
Goes low, and during the next 1 tIN, the blue read enable signal REB goes low. Therefore, the read enable signals RER, REG, RE
In B, each color sequentially becomes L level for a period of 1 tIN with a period of 4 tIN.

The above-mentioned read enable signal RE corresponds to FIG.
As shown in (1), each of the 1H periods after several tens of H has elapsed from the start of the vertical scanning period when the vertical synchronizing signal VSYNC goes to the L level, each becomes the H level (active). The read reset signal RRST is set to the H level (active) only once before the read enable signal RE first goes to the H level within the vertical scanning period.
And the read addresses of the field memories 41 to 43 are returned to the initial values. When the read enable signal RE goes to the H level, the read enable signals RR, REG, REB of the respective colors output by the read timing adjustment circuit 45
When the internal clock signal INCLK rises during the period during which the signal is at the H level, the image data (R0, G0, B0, etc.) of each color stored in the field memories 41 to 43 is sequentially read.

The reading of the image data can be performed asynchronously with the writing. Therefore, in order to maximize the duty ratio of the liquid crystal panel 1, the read enable signal RE should always be at the H level, and reading should be performed uniformly over the entire vertical scanning period and horizontal scanning period. However, in any case, the image data held in the field memories 41 to 43 must not be rewritten before reading. For this purpose, the vertical synchronization signal VSYNC or the horizontal synchronization signal HSY sent to the source driver 2 or the gate driver 3 is used.
The NC may be changed to a different timing or a different cycle from that supplied from the outside. Further, the reading of the image data can be performed almost simultaneously at a timing delayed by several pixels from the writing by setting the frequency of the internal clock signal INCLK to 4/3 times that of the external clock signal EXCLK. For example, an image memory having a sufficiently smaller memory capacity than the field memories 41 to 43 can be used. In the first T1 period T0 after the rise of the read enable signal RE, the image data R0, G0, and B0 are read from the field memories 41 to 43, respectively, and the internal video signal INVS is read.
Becomes However, in the next period T1, the image data G1, B
Only 1 is newly read out, and for red, the read enable signal RER becomes L level and reading is stopped, so that the previous image data R0 is used as it is.
In the next period T2, only the image data R1 and B2 are newly read out, and the reading enable signal REG goes low for green and reading is stopped, so that the previous image data G1 is used as it is. . Further, in the next period T3, only the image data R2 and G2 are newly read, and the read enable signal REB for blue is read.
Becomes L level and reading is stopped, so that the previous image data B2 is used as it is. The same operation is repeated thereafter to partially overlap the image data of the video signal VS having the aspect ratio of 3: 4 and increase the number of pixels in one line to 4/3 times. When the internal video signal INVS is sent to the source driver 2, one line of image data can be displayed horizontally long using the entire width of the display screen having the aspect ratio of the liquid crystal panel 1 of 9:16. Also, the internal video signal INVS
For the original pixel by three image data,
A group of four image data can be considered as a pseudo pixel E. That is, the pseudo pixel E0 is composed of two pieces of image data R0 and one piece of image data G0 and B0, and the pseudo pixel E1 is two pieces of image data G1 and one piece of image data R
The pseudo pixel E2 is composed of two pieces of image data B2 and one piece of image data R2 and G2. Therefore, as the image data, each pixel of the video signal VS corresponds to the pseudo pixel E on a one-to-one basis.
The number of pseudo pixels E in one line of NVS is equal to one in the video signal VS.
This corresponds to the number of pixels in the line, so that the display screen of the liquid crystal panel 1 can reproduce and display without a sense of discomfort.

That is, when the video signal VS before conversion is displayed on a display screen of 640 pixels × 480 lines (aspect ratio 3: 4), as shown in FIG. , One image data Ri, Gi, Bi (i is an integer of 0 or more) of each color. However, the internal video signal INVS after the conversion of the aspect ratio
Is displayed on the display screen of the liquid crystal panel 1, as shown in FIG. 9, three display dots of each pseudo pixel E composed of four display dots include image data Ri, G of each color.
i and Bi are assigned one by one, and one color data of the same image data Ri, Gi and Bi is assigned to the remaining one display dot in an overlapping manner. In addition, the colors assigned to the remaining one display dot are sequentially switched for each pseudo pixel E, and all colors are evenly and redundantly assigned. Therefore, if this internal video signal INVS is used, about 85
640 pseudo pixels E can be displayed over the full width of the display screen of the liquid crystal panel 1 capable of displaying three pixels.

When the signal processing circuit 4 sends the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC to the gate driver 3, as shown in FIG. 10, the vertical synchronizing signal VSYNC becomes L level and the vertical scanning period starts. Each time, the gate driver 3 applies the gate voltages L1 to Ln which become H level sequentially to each gate line of the liquid crystal panel 1 for each horizontal scanning period (1H). When the source driver 2 applies a gradation voltage to each source line of the liquid crystal panel 1 for each horizontal scanning period based on the image data of each line of the internal video signal INVS, the image is displayed on the entire display screen of the liquid crystal panel 1. All images of the signal VS are displayed.
FIG. 10 shows a case where the liquid crystal panel 1 having more than 480 gate lines (n> 480) is used. Therefore, the period during which image data is read from the field memories 41 to 43 excludes the vertical blanking period and the like in the vertical scanning period. However, in the horizontal scanning period, reading is performed uniformly over the entire period including the horizontal blanking period.

As described above, according to the liquid crystal display device of the present embodiment, a video signal composed of a VGA signal having an aspect ratio of 3: 4 (640 pixels × 480 lines) is obtained by simple conversion processing by the signal processing circuit 4. All of the VS images can be reproduced and displayed almost entirely on the display screen of the liquid crystal panel 1 having the aspect ratio of 9:16 without any discomfort.

In the liquid crystal display device of the present embodiment, only the case where the aspect ratio is changed from 3: 4 to 9:16 has been described. However, the conversion of an arbitrary aspect ratio can be performed by the same processing. is there. Also, when the number of scanning lines needs to be changed during the conversion of the aspect ratio, it can be easily coped with by thinning out the scanning lines and overlappingly inserting the scanning lines at appropriate intervals as in the related art. it can. Further, in the present embodiment, the liquid crystal display device has been described, but the present invention can be similarly applied to other image display devices.

[0035]

As described above, according to the image display apparatus of the present invention, the image data of each pixel of the video signal is assigned to each pseudo pixel having a larger number of display dots than the original pixel on the display screen. Can be reproduced and displayed on display screens having different aspect ratios without any discomfort. Moreover,
Since there is no need to perform complicated arithmetic processing, it is possible to prevent an increase in cost of the image display device.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a configuration of a liquid crystal display device.

FIG. 2 illustrates one embodiment of the present invention, and is a block diagram illustrating a configuration of a signal processing circuit.

FIG. 3 illustrates one embodiment of the present invention, and is a time chart illustrating a configuration of a video signal.

FIG. 4, showing an embodiment of the present invention, is a time chart illustrating an operation of writing image data in a signal processing circuit.

FIG. 5, showing one embodiment of the present invention, is a block diagram illustrating a configuration of a read timing adjustment circuit.

FIG. 6 illustrates one embodiment of the present invention, and is a time chart illustrating the operation of the read timing adjustment circuit.

FIG. 7, showing an embodiment of the present invention, is a time chart illustrating an operation of reading image data in a signal processing circuit.

FIG. 8 illustrates one embodiment of the present invention, and is a diagram illustrating image data when a video signal is displayed on a display screen having an aspect ratio of 3: 4.

FIG. 9 illustrates one embodiment of the present invention, and is a diagram illustrating image data when an internal video signal is displayed on a liquid crystal panel having an aspect ratio of 9:16.

FIG. 10 illustrates one embodiment of the present invention, and is a time chart illustrating a configuration of an internal video signal.

FIG. 11 shows a conventional example, and is a block diagram illustrating a configuration of a liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal panel 2 source driver 3 gate driver 4 signal processing circuit 41 field memory 42 field memory 43 field memory 45 read timing adjustment circuit

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Takeshi Fukui 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-8-125553 (JP, A) JP-A-7- 212690 (JP, A) JP-A-1-314084 (JP, A) JP-A-4-54789 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 9/12-9 / 31 H04N 5/66 H04N 7/01 H04N 11/00-11/24 G09G 3/20

Claims (3)

(57) [Claims] 1. An image display device in which each pixel constituting a display screen is constituted by three display dots corresponding to each of the three primary colors of RGB, wherein four or more predetermined numbers of four or more pixels horizontally adjacent to each other on the display screen are provided. A signal processing circuit that supplies image data corresponding to each pixel of the video signal to each of the display dots as a pseudo pixel, wherein the signal processing circuit includes a color among four or more display dots of each pseudo pixel; Are assigned image data of colors corresponding to the three display dots of each pixel in the video signal, and the remaining display dots of the pseudo pixel are assigned to the three display dots of the pixel. An image display device for generating an internal video signal in which image data of a color corresponding to the remaining display dots is assigned in an overlapping manner. 2. The image display device according to claim 1, wherein an image memory for storing image data of each color in a first-in first-out manner, and an image data of each color input serially in accordance with an external clock signal synchronized with the image data. Write control means for sequentially storing the image data in the image memory, and read control means for sequentially extracting image data of each color from the image memory in accordance with an internal clock signal and periodically stopping the extraction of the image data for each color. Image display device. 3. The image display device according to claim 2, wherein the read control unit stops taking out the image data from the image memory once every four times at a different timing for each color. apparatus.