JPS6346437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display device, and in particular includes a control circuit that maintains the scanning period of one screen constant regardless of the number of display columns on a liquid crystal panel and facilitates standardization and integration. This invention relates to a liquid crystal display device.

In general, liquid crystal display devices have been widely used for such purposes because their operating voltage is low and they can be configured as flat panels. In particular, a liquid crystal matrix panel in which liquid crystal is formed into a flat panel shape and used to display characters and symbols has been proposed.

FIG. 1 shows a block diagram of a liquid crystal display device according to this conventional example. In this figure, reference numeral 1 denotes a liquid crystal display panel, in which a desired number of scanning electrodes 2 are provided along the horizontal axis as shown, and signal electrodes 3 are similarly provided corresponding to the scanning electrodes 2 along the vertical axis. It is equipped with The scanning electrode 2 is connected to a scanning circuit 5 via a scanning drive circuit 4, and is sequentially scanned by this circuit 4.
This scanning circuit 5 is configured to receive a timing signal from a control circuit 6 and generate a scanning signal.

On the other hand, the series/parallel circuit 7 is configured to convert the character signal outputted from the control circuit 6 into one line of parallel signals, and is configured to supply the parallel output signal to the line memory 8. There is. The line memory 8 is configured to store signals for a selected time period of one line, and is configured to be controlled in this manner by the output signal _CP2 of the control circuit. This line memory 8
The output terminal of is connected to the input terminal of the signal drive circuit 9. The signal drive circuit 9 is configured to supply the signal voltage to the signal electrode 3.

The operation of the liquid crystal panel configured as described above will be briefly explained. The liquid crystal matrix is driven by a line sequential scanning method in which the scanning electrodes 2 of the liquid crystal matrix panel 1 are sequentially scanned. Scanning circuit 5
forms a line sequential scanning signal based on the timing signal supplied from the control circuit 6 and supplies it to the scanning circuit 4. Then, the scanning circuit 4 generates a scanning voltage and applies it to the scanning electrode 2 of the liquid crystal matrix panel 1.
to be applied.

On the other hand, the serial/parallel conversion circuit 7 converts the character signal supplied from the control circuit 6 into one line of parallel signals and supplies the parallel signals to the line memory 8 .
This line memory 8 holds the character signal for the selection time of one line. Thereby, the signal drive circuit 9 generates a signal voltage and applies it to the signal electrode 3 of the liquid crystal matrix panel 1.

Characters are displayed on the liquid crystal matrix panel 1 by operating as described above.

The control circuit 6 of such a liquid crystal matrix panel 1 is generally shown in FIG. That is,
FIG. 2 shows a block diagram of the general configuration of a conventional liquid crystal matrix panel control circuit. The control circuit 6 takes in information to be displayed on the liquid crystal matrix panel 1 and converts it into a character pattern signal DA, and also the scanning circuit 5,
It is capable of generating signals for controlling the series/parallel circuit 7. That is, reference numeral 6A is an oscillator circuit that generates a reference clock, and is connected to take out the output clock signal _CP1 and to supply the signal _CP1 to the dot counter 6B. The output terminal of the dot counter 6B is connected to the input terminal of the column counter 6C, and the output signal is sent to the column counter 6C.
It is designed to be supplied to C. The column counter 6C counts the supplied signals to form an output signal _CP2 , which is then sent to the line counter 6C.
It is connected to supply D. The output signal of this line counter 6D is supplied to a row counter 6E, which counts it to form an output signal _CP3 , which is output to the outside and also connected to be input to a refresh memory 6F. . This refresh memory 6F is supplied with the output signal of the column counter 6C, and the display information written externally is sent to the character pattern generator 6G.
is configured to supply. This character pattern generator 6G is supplied with the output signal of the line counter and generates a character pattern signal for each line.
Configured to output DA.

Regarding the operation of the control circuit configured as described above, the relationship between the operations of the circuit shown in FIGS. 1 and 2 will be explained with reference to FIG. 3.

FIG. 3 shows a time chart for explaining the operation of the liquid crystal display device and its control circuit shown in FIGS. 1 and 2. The horizontal axis shows time, and each vertical axis shows time. Signal waveforms having the same reference numerals as those assigned thereto are shown. That is, the output signal CP ₃ of the row counter 6E is a frame start signal, and scanning of one screen is started at the timing of this signal CP ₃ . On the other hand, the output signal CP ₂ of the column counter 6C is a line start signal and is used to generate the output signals l ₁ to l _M of the scanning circuit 5.
This signal CP ₂ is also used as a timing signal for loading the contents of the serial/parallel conversion circuit 7 into the line memory 8. Further, the input signal _CP1 of the dot counter 6B is a signal for sending out a display pattern signal DA, and is called a shift signal. or,
The serial/parallel conversion circuit 7 is configured to sequentially take in the display pattern signal DA in response to the shift signal _CP1 . Generally, line-sequential scanning displays that operate in this manner are driven and displayed by setting the time T ₀ used for scanning one frame to 25 to 15 [mS] to prevent display flickering or the frequency characteristics of the liquid crystal. This is often the case.

On the other hand, when displaying characters, symbols, etc. using the dot method in a display device, one character is composed of five dots in a row and seven dots in a column. The so-called 5x7 dot system or the 7x9 dot system was used. However, in liquid crystal display devices, in order to reduce the number of scanning lines, one character is often made up of 5×7 dots. In a liquid crystal display device configured in this way, increasing the number of rows will result in a decrease in contrast, so increasing the number of rows is limited to one or two rows, but increasing the number of display columns is recommended. does not affect the quality of the liquid crystal display in any way.

By the way, as the scope of application of liquid crystal display devices has been expanded, there has been a strong desire to increase the number of display columns of characters. In this case, it is naturally necessary to reduce the cost and size of the device, and for this purpose, standardization and integrated circuitization of the control circuit are required.

On the other hand, if the number of display columns on the LCD panel is different,
In the conventional control circuit shown in FIG. 2, it is necessary to change the frequency division ratio of the column counter 6C each time. Furthermore, when the number of display columns differs by about one order of magnitude, it is necessary to increase the oscillation frequency of the oscillation circuit 6A by about one order of magnitude in order to suppress fluctuations in the frame period T ₀ to about 25 to 15 [mS]. In this case, there was a problem in that the operating margin of the integrated circuit (IC) etc. was reduced.

An object of the present invention is to provide a liquid crystal display device equipped with a control circuit that maintains the scanning period of one screen constant regardless of the number of character display columns on a liquid crystal panel and is suitable for standardization and integration.

The present invention focuses on the fact that character code signals are sequentially written from the low address position to the high address position of the refresh memory when characters are displayed continuously on the liquid crystal panel, and the column counter reads the memory contents of the refresh memory. It consists of a down counter that reads data sequentially from a high address position to a low address position, and has a dot counter with a frequency division ratio equal to the number of horizontal dots in one character, and an up count operation with a frequency division ratio equal to the number of vertical dots in one character. The above object is achieved by reading out the contents of all addresses in the refresh memory regardless of the number of display columns of characters, and displaying only the display information portion on the liquid crystal panel.

An embodiment of the present invention will be described based on the drawings from FIG. 4 onwards.

FIG. 4 shows a block diagram of a control circuit for a liquid crystal matrix panel according to an embodiment of the present invention. In this figure, reference numeral 10 denotes a control circuit, which is configured so that a clock signal _CP1 is supplied from an oscillation circuit 10A to a dot counter 10B, a column counter 10C, and a line counter 10D, respectively. The dot counter 10B is an up counter having a frequency division ratio of one horizontal dot, and is designed to supply a carry output signal _C1 according to the frequency division ratio to the input terminal of the column counter 10C. It is configured. Moreover, the column counter 10C
is configured to form a signal RFAD by a down-count operation to read out the contents stored in the refresh memory 10E from a high address position to a low address position, and supply it to the refresh memory 10E. Then, when the down count value reaches zero, a borrow output signal (digit down signal) _B1 is generated, and this is sent to the line counter 10.
A column counter 10C and a line counter 10D are connected to supply the signal D. The line counter 10D has a frequency division ratio equal to the number of vertical dots in one character and is configured as an up counter, and is configured to return to the initial state with the next input signal _B1 when a predetermined count value is reached. . The carry output signal _C2 of this line counter 10D is
A character pattern generator 1 configured to be able to output to the outside and converting a character code signal from the refresh memory 10E into a character pattern signal.
0F as its low address signal. This character pattern generator 10F is configured so that the output signal DA is supplied to a serial/parallel conversion circuit (not shown).

The operation of the present invention constructed as above will be explained with reference to FIGS. 5 to 9.

FIG. 5 shows an explanatory diagram when the storage capacity of the refresh memory is M, and when the number of displayed characters is m, the code signal of the character to be displayed is written at addresses 0 to m-1. ing. Under these conditions, the number of dots in the displayed character is increased by 5×
The operation of the control circuit 10 when displaying in the 7-dot system will be explained based on FIGS. 6 to 9.

FIGS. 7 to 9 show time charts for explaining the operation of the control circuit shown in FIG. 4, in which each vertical axis represents the signal level of its sign, and each horizontal axis represents time is shown. As shown in FIG. 6, the output signal _CP1 of the oscillation circuit 10A is frequency-divided by 1/5 in the dot counter 10B.
The carry output signal _C1 becomes an input signal to the next stage column counter 10C. Column counter 10C
counts down in synchronization with signal CP ₁ every time carry output signal C ₁ is input, as shown in FIG. When the count value becomes zero, the column counter 10C generates a borrow output signal (carry down signal) _B1 and sets the output to M-1. below,
The above operation is repeated. As a result, the count output signal of the counter 10C
RFAD becomes a read address signal for the refresh memory 10E. On the other hand, the borrow output signal
_B1 is also used as a carry input signal to the next stage line counter 10D.

On the other hand, as shown in FIG. 8, the line counter 10D counts up in synchronization with the signal CP ₁ every time the borrow output signal B ₁ is input, and when the count value reaches 6, the next borrow is counted up. output signal
When B ₁ is input, its output signal C ₂ becomes zero.
This is the carry output signal. The count output signal CGAD of the counter 10D is output as a low address signal of the character pattern generator 10F.

According to the above explanation, the borrow output signal _B1 of the column counter 10C is the line start signal _CP2 ,
Also, the carry output signal of line counter 10D
_C2 becomes the frame start signal _CP3 .

FIG. 9 shows a time chart for explaining the generation state of the character display signal DA, in which each horizontal axis shows time, and the vertical axis shows the signal level of the code assigned to them. It is shown. In addition, FIG. 9 shows an explanatory diagram of the character pattern stored at address zero in the refresh memory.

The display signal DA generated in one period of the line start signal _CP2 is divided into a character pattern established area and an undefined area. (See Figure 9)
In the former case, the contents of addresses 0 to m-1 of the refresh memory 10E are read out, and in the latter case, the contents of addresses m to M-1 are read out, and therefore, as described above, the established area and the undefined area are separated. There is a separation between the two.

For example, if the character code "A" of Alphabet is written in the zero address of the refresh memory 10E, the last character pattern during the scanning period of one line will be the character code as shown in FIG. 9 and the same figure. This becomes the second line pattern of “A”.

After the serial/parallel conversion circuit 7 takes in the character pattern signal written in address 0 of the refresh memory 10E and converts it into a parallel signal,
This is held in the line memory 8 at the timing of the line start signal _CP2 . That is, the serial/parallel conversion circuit 7 takes in character pattern signals written in all addresses of the refresh memory 10E, but the line memory 8 retains only valid signals among these signals.

As a result, since the frequency division ratio of the column counter is not changed at all, the scanning period of one screen can be stabilized. Furthermore, by making the storage capacity of the refresh memory 10E sufficiently large, it can be applied to small to large liquid crystal display devices.

FIG. 10 shows a block diagram of an application example of the control circuit according to the present invention. In this diagram,
Reference numeral 11 is a liquid crystal display device, which is shown in FIGS. 1 and 4.
Elements that are the same as those in the figures will be described with the same reference numerals. In the embodiment shown in this figure, the output signal of the oscillation circuit 10A is
CP ₁ is input to the serial/parallel conversion circuit 7, and the output signal DA of the character pattern generator 10F is also supplied, and in addition, the signal CP ₂ is input to the scanning circuit 5 and The configuration is such that the signal CP ₃ is input to the line memory 8 and is also supplied to the scanning circuit 5 . The control circuit 10 also includes a control device 1 such as a microcomputer, for example.
An interface circuit 10H with 2 is provided.

The applied example of the present invention configured in this manner can fully exhibit its functions as described above.
Therefore, by converting the control circuit 10 including the illustrated interface circuit 10H into an IC, a simple liquid crystal display device can be constructed. Furthermore, since the refresh operation is performed by the control circuit, the burden of display control on the control device 12 can be reduced.

According to the present invention, as described above, the scanning period of one screen can be kept constant regardless of the number of character display columns on the liquid crystal panel, which facilitates standardization of control circuits and LSI implementation. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional liquid crystal display device, FIG. 2 is a block diagram showing a conventional control circuit, and FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2. FIG. 4 is a block diagram of a control circuit according to an embodiment of the present invention, FIG. 5 is an explanatory diagram showing the contents of the refresh memory, and FIGS. 6 to 9 are diagrams for explaining the operation of the present invention. The time chart, FIG. 10, is a block diagram showing an example of application of the present invention. 1...Liquid crystal matrix panel, 4...Scanning drive circuit, 6, 10...Control circuit, 9...Signal drive circuit, 10B...Dot counter, 10C...Column counter, 10D...Line counter, 10E...
Refresh memory, 10F...Character pattern generator, 11...Liquid crystal display device.

Claims (1)

[Scope of Claims] 1. A liquid crystal matrix panel 1 that displays characters and symbols, and a scan drive circuit 4 that generates a line sequential scan drive voltage and supplies this line sequential scan drive voltage to the row electrodes of the liquid crystal matrix panel 1. a refresh memory 10E that stores character codes for one screen; a character pattern generator 10F that receives this character code and generates a serial character pattern signal for each line corresponding to this character code; a serial/parallel conversion circuit 7 that sequentially takes in the one line of serial character pattern signals in synchronization with the clock signal _CP1 of clock signal CP1 and converts them into one line of parallel signals;
a line memory 8 for storing the one line of parallel signals for one line scanning period; generating a signal voltage according to the output of the line memory 8 and supplying this signal voltage to the column electrodes of the liquid crystal matrix panel 1; and a refresh counter for controlling the scan drive circuit 4, the refresh memory 10E, and the character pattern generator 10F; a dot counter 10B which receives one clock signal _CP1 and generates a first carry output signal _C1 according to a frequency division ratio equal to the number of horizontal dots of one character pattern; Each time C ₁ is input, it counts down in synchronization with the first clock signal CP ₁ to generate a first count output signal (RFAD), and the number of characters displayed on the liquid crystal matrix panel 1 is greater than or equal to the number of display columns. a column counter 10C that generates a borrow output signal _B1 according to a frequency division ratio of the number of; and a column counter _10C that counts up in synchronization with the first clock signal _CP1 every time the borrow output signal B1 is input. A second carry output signal C 2 that generates a second count output signal (CGAD) and follows a division ratio equal to the number of vertical dots of one character pattern _.
the first count output signal (RFAD) of the column counter 10C is sent to the refresh memory 10E.
A second count output signal (CGAD) of the line counter 10D is supplied to the refresh memory 10E as a read address signal of the character pattern generator 1.
0F address signal to the character pattern generator 10F, and the borrow output signal _B1 as a line start signal.
A liquid crystal display device characterized in that the _second carry output signal C2 is supplied as a frame start signal _CP3 to the scan drive circuit 4 and the line memory 8, and the second carry output signal _C2 is supplied as a frame start signal CP3 to the scan drive circuit 4. .