JPS60136828A - Signal processor - Google Patents

Abstract

PURPOSE:To execute the real time processing of a video signal simultaneously with the input processing of a picture to a computer by forming an exclusive bus for transferring picture signal data directly between peripheral devices. CONSTITUTION:A video signal VI is transferred to a display device through a decoder 2, an A/D converter 3, a bus controller 15, a bus B, a bus controller 17, a D/A converter 13, and an encoder 14 under control by a bus controller 16. Data registered in a memory 7 and a disc 9 are also transferred to the bus controller 17 through buses 11, 12 which are not used by a computer 6, a bus interface 18 and the bus B and data in the bus controller 15 are also transferred to the memory 7 and a disc controller 8 through the bus B and the bus interface 18. The computer 6 can transmit/receive data from/to the memory 7 and the disc controller 8 through the buses 11, 12 simultaneously with said operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal processing device that data-processes a video signal.

[Prior art]

In order to display a moving image on an image display device, K is required to be able to perform certain image processing at least within each field (usually 60 fields/sec).

Conventionally, there has been a device of this type as shown in FIG.

In the figure, 1 is a line leading to a video signal V including horizontal and vertical synchronization signals and encoded color signals, 2 is a decoder that separates this video signal VI into color signals R, G, and B, and 3 is a color signal R1B. , G into a digital signal format; 4 is a frame memory that stores the digitized color signals d, B', and σ in units of frames; 5 is a frame memory 4; 6 is the ink face for transferring the data D of the
), 7 stores the program and data of the computer 6 (
8 is a disk controller that stores the data of the computer 6, 9 is a disk that stores the data of the computer 6, 10 is an input/output device for the data of the computer 6, 11 is a bus that connects the interface 5 to the disk 9, 12 is a PCCH (program control channel) that connects the interface 5 to disk 9, and 13 is a digital/analog (D/A) channel for data D of the frame memory 4.
The converting D/A converter 14 is an encoder of the output of the DA converter 13.

The video signal VI is first decoded by the decoder 2, and red, blue, and green color signals R, G, and BK are separated. Next, the color signal RGB is converted into a digital color signal R' by the A/D converter 3.
, n', and σ, and input into the frame memory 4, where one screen (one field or l frame) of the data is stored. The data D in the frame memory 4 is transferred to the memory 7 via the interface 5 under the control of the computer 6.
MA is transferred. The data transferred to the memory TK is then subjected to image processing by the computer 6. The processed results are sent to the disk 9 via the disk controller 8 and stored therein. The data stored on the disk 9 is transferred to the frame memory 4 via the bus 11 and interface, then converted into an analog level color signal by the D/A converter 13, and further converted into a video signal v0 by the encoder 14. encoded and output. The input/output device 10 issues a transfer request (command) to the AD converter 3, frame memory 4, and D/A converter 13 when reading and outputting data.
It has a function to output and understand these statuses.

Since the conventional device is configured as described above, the time T required to input one image to the computer is, for example, N
In the case of a TSC signal, if the resolution of the display image is 480 lines vertically and 512 lines horizontally, the number of A/D conversion bits is 8 bits, and the transfer rate of the DMA bus interface is 64 bytes and 7 seconds, then T = 480x512x8x3 = 11 .2 seconds 6
It becomes 5536X8. Also, when displaying, the same amount of time is required since the operation is the reverse of inputting. Therefore, if such input/output processing is performed simultaneously, a processing time of 20 seconds or more is required. Also, during online image processing, the computer can directly download data from the frame memory via a common bus.
/ Since the image data is output to the A converter, there is a drawback that other processing cannot be performed during that time.

[Summary of the invention]

This invention eliminates the drawbacks of the conventional ones as mentioned above,
In addition, by providing a dedicated bus for directly transferring image signal data between peripheral devices, we have created a 5K signal processing device that can perform real-time processing of video signals and input processing of images to a computer in parallel. is intended to provide.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, the same symbols as in FIG. 1 indicate the same parts,
Reference numeral 15 denotes a bus controller, which inputs the data of the A/D converted video signal VI and sends it onto the bus B. 1
6 is a path controller 2 which controls the transfer of data on bus B in synchronization with the video signal of 1; 17 is a bus controller which controls the transfer of data on bus B to the cyclic KDA converter 13; 18 transfers data from bus B to bus 11
This is a pass interface that transfers data on bus 11 to bus B. Bus B is pass con draw 2
A line that is commonly connected to 15.16.17 and the interface 18 and transfers mutually exchanged data signals, a line that transfers horizontal and vertical synchronization signals detected from the video signal vl, and a line that is synchronized with these synchronization signals, and lines that transfer timing signals for strobing data signals.

The horizontal and vertical synchronization signals and timing signals are sent onto bus B from bus controller 16.

In operation, the video signal VI is connected to the bus controller 1
6, the decoder 2, A/D converter 3, bus controller 15. Bus B, bus controller 17, D/
The signal is transferred via the A converter 13 and encoder 14 to an image display device (not shown) and displayed there. Similarly, the data registered in K, memory 7 and disk 9 is transferred to bus controller 217 via bus 11 or 12, bus interface 18 and bus B which are not used by computer 6.
&C to transfer the data of the bus controller 15 to the memory 1 and the disk controller via the bus 11 or 12 which is not used by the bus B, the bus interface 18 and the busy computer 6? 8 is also performed.

Even if such data transfer is performed, the computer 6
In parallel with this, data processing involving data transfer between the memory 7 and the disk controller 8 via the bus 12 or 11 can be executed. This data processing also includes background processing for displaying moving images, which requires a large amount of processing time.

In the above embodiment, the image signal is a color video signal, but it may be a signal for cyclically displaying an image, such as a black and white video signal.

Further, in FIG. 2, a plurality of devices other than the bus controller 16 and the computer 6 can be connected and used.

〔Effect of the invention〕

As described above, according to the present invention, since the image signal bus synchronized with the image signal pressure and its controller are provided in the signal processing device, image signal data can be registered and searched in real time without interrupting computer processing. It has the effect of processing things such as display.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional signal processing device, and FIG. 2 is a block diagram of a signal processing device according to an embodiment of the present invention. 2... Decoder, 3... A/D converter, 4... Frame memory, 6... Computer, I... Memory, 8
...Disk controller, 9-...Disk, 10
...input/output device, 11, 12. n...bus, 13.
...D/A converter, 14...encoder, 15.16
．． 17... Passcondronia, 18... Bus interface. In addition, in the figures, the same reference numerals indicate the same parts. Patent applicant: Mitsubishi Electric Co., Ltd. Agent Patent attorney 1) Hiroshi Sawa, Showa 1゛: □! 1 ÷ 1- 1・-i

Claims (1)

[Claims] A signal processing device equipped with a computer that reads the data from an image memory that stores continuous video signal data via a first bus and executes predetermined image processing in real time according to a program stored in the main memory. In,
a second bus that connects the computer and the peripheral device including the main memory; an interface that connects the first and second buses and the image memory; and one of the first and second buses. a controller for directly accessing data between the other peripheral devices via the other first or second node while the computer is transferring data with one of the peripheral devices via the other first or second node; A signal processing device comprising: