JPH059832B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an image processing method and apparatus, and in particular,
The present invention relates to an image input device that automatically updates an address register of a frame memory that stores image information at the timing of access from a processing device.

[Background of the invention]

Conventional image input devices contain a huge amount of image information, so in the case of processing devices with small memory areas such as microcomputers, it is necessary to control the frame memory address with a register or expand the address bus signal line of the processing device with a register. It was controlled in this way. Therefore, in order to read one pixel of data from the frame memory, set the X address and Y address, read the data, then determine the update address, set this update address, and read the data. In this way, the address control command and the data read command must be repeatedly executed.

For example, the full screen is 256 (horizontal address) x 256
(vertical address), 65,536 operations were required for each instruction, which caused the problem of slow processing speed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image input device in which a frame memory address is controlled by a register, and which can update an address without executing an address control command other than setting a data read start address. be.

[Summary of the invention]

The present invention allocates multiple addresses from the CPU to the frame memory, and uses these multiple addresses to uniformly specify the address of the pixel currently being accessed and the update addresses of pixels in eight directions adjacent to it. , the next access address can be automatically updated without using an address control command except for setting a predetermined start address.

According to this, the processing operation for updating addresses is reduced, and the processing speed of image data consisting of a huge amount is greatly improved.

In other words, the present invention provides a processing device (hereinafter referred to as a CPU)
In an image processing method that accesses frame memory and reads/writes image data according to address control instructions from the CPU, the CPU sets multiple address ports in the CPU memory to allocate multiple addresses to the frame memory The address control command including the access address which is a predetermined starting point address for accessing the frame memory is pre-written in order to set one of the addresses in multiple directions including diagonal directions adjacent to the access address as the next update address. The image input device outputs data using a predetermined address port corresponding to each update direction, and upon receiving the address control command, sets an access address in an address register that specifies a pixel point in the frame memory, and receives data from the CPU. The present invention is characterized in that an access instruction is made executable, and the contents of the address register are updated by increasing or decreasing two-dimensionally in accordance with the update direction of the predetermined address port at the execution timing of the access instruction.

[Embodiments of the invention]

FIG. 1 shows a block diagram of an image processing device including an image input device of the present invention.

The video captured by the industrial television camera 4 is converted into a composite video signal and input to the image input device 3. The input composite video signal is connected to an A/D converter 6 and a synchronous separation circuit 7 via a video amplifier 5.

The timing control circuit 8 generates sampling pulses for decomposing a video signal obtained by horizontal scanning of the industrial television camera 4 into pixels, and controls the A/D converter 6 and the D/A converter 15.

The address generation circuit 9 counts the sampling pulses output from the timing control circuit 8 at the timing of the synchronization signal detected by the synchronization separation circuit 7, and generates a frame memory capture address.

Reference numeral 10 denotes an address signal multiplexer that selects either the address specified by the address generation circuit 9 or the address specified from the address register 18 and connects the selected address to the frame memory 12. Further, 11 is a multiplexer for write data which selects either the write data from the processing device 1 or the input data obtained by the A/D converter 6 and connects the selected data to the frame memory.

The address of the frame memory 12 is expressed by two-dimensional coordinates in the horizontal and vertical directions, with the horizontal direction being indicated by the number of samples on the scanning line of the television camera, and the vertical direction being indicated by the number of scanning lines. The data indicates grayscale information of the pixel. The frame memory according to this embodiment is a 32 kbyte memory with 256 horizontal points, 256 vertical lines, and 4 bits of video data.

The memory control circuit 13 includes an address selector 10
and the data selector 11 to control read and write timings of the frame memory.

The monitor television 14 is used to view the video stored in the frame memory 12. The digital video data in the frame memory 12 is D/A
It is converted into an analog video signal by the converter 15,
After being converted into a composite video signal including vertical and horizontal synchronizing signals by the synthesis circuit 16, it is connected to a monitor television.

Reference numeral 17 denotes a control circuit for connecting the processing device interface bus 2 and the image input device 3, which allocates the image input device in the memory space of the processing device and controls data transfer timing of the data buffer 19.

The address register 18 has a function of setting an address of the frame memory to be accessed (read/written) from the processing device 1 and also automatically updates the access address. Addresses are set in the registers in correspondence with the image processing address space (FIG. 4) allocated to the frame memory.

By the way, the processing device 1 has a frame memory (1
In order to allocate multiple addresses to a device (machine), multiple address ports are set in its main memory, and as shown in Figure 4 below, each address port corresponds to the direction of the address to be updated. be done.
Therefore, the address register 18 checks which address port the address control command sent from the processing device via the bus 2 belongs to, and according to the update direction set in advance for the address port, Update the next address to access. The update is performed at the timing of the end of the access operation.

FIG. 2 shows a block diagram of an address register section in which the present invention is implemented using an 8-bit microcomputer 6800 (hereinafter abbreviated as MPU) as a processing device.

Data transfer between the MPU and the image input device is performed by the MPU.
A transfer address and a transfer timing are given to the interface bus 2.
The transfer address is given by the A15 to A0 and VMA signals of the bus, and the transfer timing is φ2, R/W.
controlled by the signal.

20 is an address comparator for allocating an image input device in the address space of the MPU;
1 is a switch for setting the address of the image input device. The address comparator 20 compares the address set by the switch 21 with the address signal on the interface bus 2, and outputs an address match signal when the same address is detected.

Additionally, a VMA signal indicating that the memory address on the bus is valid is input via the bus receiver 22, and an address match signal is sent to the NAND gate 23.
performs a logical AND operation, and outputs a select signal indicating that the image input device has been designated. Only when the image input device receives this select signal,
Connected to the MPU interface bus.

24 indicates an address register control circuit;
5 indicates a transfer data control circuit. These decode the bus timing signals φ2 and R/W and the lower 4 bits of address signals A3 to A0 to control transfer data and address update contents.

Further, the NAND gate 26 performs a logical product of φ2 and R/W to control the transfer timing of the data buffer 19. D7-D0 are data signals.

27 and 28 are address registers, 27 stores addresses in the horizontal direction, and 28 stores addresses in the vertical direction. This address register uses an up-down counter whose count data can be preset and has separate count inputs for count-up and count-down. A command to preset address data in the counter and a command to update the address data are output from the address register control circuit 24 in accordance with an address control command from the MPU.

The contents of the command signal line 29 consist of four types: count-up pulse, count-down pulse, data load, and counter clear, each with a value of 27 and 28.
independently connected to the counter.

30 is a data selector for the vertical address register, which is used to read address data necessary for updating only the effective address of the frame memory from the setting switch 31, or to read address data transferred from the MPU to the vertical address register. Connect to register 28.

An address management circuit 32 refers to the contents of the address registers 27 and 28 and outputs position information necessary for the address register control circuit 24 to output the control command 29.

33 is a data selector, and address register 2
Select either the contents of 7 or 28 or the video data in the frame memory, and save the data to the data buffer 19.
The transfer data control circuit 25 controls the transfer data control circuit 25.

FIG. 3 shows the contents of address update.

Generally, in image recognition processing, the outline of the image is first identified. In this case, the outline can be identified by knowing which pixels in the vertical, horizontal, or diagonal direction the image information continues from the currently accessed pixel, and making the next access in the direction of the consecutive pixels. becomes. In order to facilitate such processing, it is desirable that the image input device be able to automatically update the next access address from among pixels in eight directions adjacent to the pixel currently being accessed. As shown in FIG. 3, the image input device of the present invention accesses the pixel point P specified by the horizontal address The contents of the address register are automatically changed to the addresses of adjacent pixels a to h.

FIG. 4 shows a frame memory access method when the image input device is allocated to addresses E100 to E10F in the memory area of the MPU, and address update contents corresponding to FIG. 3.

Address E100 is an address port for setting data in horizontal address register X, and address E101 is an address port for setting data in vertical address register Y. Also, address E102 ~ E10A
The address is an address port that accesses the contents of the frame memory indicated by the X and Y address registers.

The present invention provides a plurality of address ports to access the frame memory, and increments the X and Y address registers depending on which address port the frame memory is accessed from.
Updates the address by controlling decrement, data loading, and address clearing. For example, in FIG. 4, even if an access operation is performed at the port that accesses the pixel data at point P at address E102, the address is not updated. Also, address E103 is
This port adds +1 to the contents of the X address register after accessing the pixel data at point P, and updates the address at point a. In this way,
The address register control circuit automatically updates the X and Y address registers depending on the position of the address port from which the MPU accesses the frame memory.

FIG. 5 shows the horizontal data scanning operation when data is accessed continuously from address E103. Further, FIG. 6 shows a vertical data scan operation when data is accessed continuously from address E105. In the figure, pixel addresses from 0 to 239 in the Y direction indicate an effective memory area, and pixel addresses from 240 to 255 indicate an invalid area. If the content of the horizontal address register is 0 or 255, and if the content of the vertical address register is 0 or 239, the address management circuit will
Position information is transmitted to the address register control circuit in order to update only addresses within the valid memory area.

Address updates in the effective memory area are executed by applying count-up or count-down pulses to the up-down counter used in the address register, and at the end of the effective memory area, by applying counter clear or data load pulses. do. Also, in order to efficiently access only the valid memory area in the vertical direction, if you want to update the address from 239 to 0 at the end of the valid memory area in the vertical direction, use the counter clear pulse to update the address from 0 to 239. In this case, it is controlled by a data load pulse and the address is updated at the same time as the data is accessed. Other operations are controlled by count-up pulses or count-down pulses, and the address is updated at the end of the data access operation.

FIG. 7 shows a timing chart for generating each control pulse when reading data from the MPU.

Each control pulse is selected by an address register control circuit and output to a horizontal address register X and a vertical address register Y. Note that φ ₁ indicates a synchronization signal having an opposite phase to φ ₂ .

〔Effect of the invention〕

According to the present invention, not only can addresses in any direction be updated without complicated address calculations, but frame memory data can be accessed continuously by simply setting the address to start accessing once, which reduces processing time. Can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image input device incorporating the present invention, FIG. 2 is a block diagram of an address register with an address updating function according to an embodiment of the present invention, and FIG. 3 is a diagram showing the direction of address updating. , Fig. 4 is a diagram showing the correspondence between address update contents and MPU memory area addresses, Figs. 5 and 6 are diagrams showing an example of scanning within the frame memory by the address update function, and Fig. 7 is a timing chart of the control clock. It is. 18...Address register.

Claims (1)

[Claims] 1. In an image processing method in which a frame memory is accessed and image data is read/written in accordance with an address control command from a processing device (hereinafter referred to as a CPU), the CPU allocates a plurality of addresses to the frame memory. If multiple address ports are set in the CPU memory in order to The image input device that has received the address control command outputs one of the access addresses as the next update address using predetermined address ports that correspond to each of the update directions, and the image input device that has received the address control command outputs the access address as the next update address. Setting a pixel point in an address register to enable execution of an access command from the CPU, and two-dimensionally increasing or decreasing the contents of the address register according to the update direction of the predetermined address port at the execution timing of the access command. An image processing method characterized by updating the image by updating the image. 2. The image according to claim 1, wherein when the access command is data read, the updated access address specifies the update direction so that the image data is continuous pixel points. Processing method. 3 The processing unit (hereinafter referred to as the CPU), the frame memory, and the CPU are connected by an interface bus.
In an image processing device that reads/writes image data and includes an image input device that controls access to a frame memory according to an address control command from a CPU, the CPU allocates a plurality of addresses to the frame memory. corresponds to each of a plurality of address ports in the CPU memory, an access address for setting a predetermined starting point for accessing the frame memory, and a plurality of update directions including a diagonal direction adjacent to the access address for updating the access address; an address control command output means for outputting the access control command including a designation of one of the address ports, and an access command output means for outputting an access command for reading/writing the frame memory; , an address register that stores the access address of the address control instruction, and an update address that increases or decreases the access address of the address register two-dimensionally according to a predetermined update direction of a predetermined access port specified by the address control instruction. address updating means for setting an address, address management means for checking whether or not the updated address is within a valid access range of the frame memory, and shifting the updated address to a predetermined valid address if not; An image processing device comprising a data transfer means for transferring data from the frame memory to a CPU.