JPS5851373A - Picture storage device - Google Patents

Abstract

PURPOSE:To rewrite contents of a control storage in respect to the address designation sequence to apply a titled device to various use modes, by using a high-speed control storage in the control part and reading out control information by a picture scanning signal. CONSTITUTION:Output video signals of a television camera are digitized and are inputted to a titled picture storage device 20. Signals Mphi, Lphi, and Fphi required for the operation of the picture storage device 20 are supplied from a television monitor controlling part 24. Output picture elements from the picture storage device 20 are made analog by a DA converter 25 and are displayed on a television monitor 26. Output picture elements from the first picture storage device 20a are operated by a picture operator 28, and the results are stored in the second picture storage device 20b.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image storage device. BACKGROUND ART Conventionally, as image processing technology has become more sophisticated and put into practical use, various types of image processing devices and image display devices have been developed. These devices require mass storage capable of high speed read and write operations. Such a storage device not only needs to operate in synchronization with the image scanning signal, but also needs to be able to use various reading and writing methods, primarily changing the order in which addresses are specified. For example, in the case of single display, zooming/guising operations, shift operations, and transposing operations are required, and in the case of input, interlaced scanning is required.

Furthermore, when combined with an image calculation device, a special read/write method (addressing method) is required depending on the type of calculation. Further, in the future, a multiple use function such as reading and writing to one storage device at the same time is required.

Conventionally, in such cases, a method has been adopted in which dedicated control circuits are provided for each function and these are switched depending on the required operation. However, this method has the disadvantage that the entire control circuit becomes complicated and the functions that can be realized are limited to a narrow range.

The present invention has been made in view of the above, and it is an object of the present invention to provide an image storage device that can uniformly change the read/write method or address designation order used during image display, image input, and image calculation. It is something.

The details of the invention will be described below.

PX' Two images consisting of 7 pixels are I, , I.

shall be. When I, , and I are viewed as two-dimensional matrices, their column numbers and row numbers are respectively tt+rAノSL
Let l+Mj(1(, i<p, 1<J≦q), and create the following two permutations.

Then, the reading/writing method of the storage device required for the above-mentioned image display, image input, and image one-image calculation can be expressed by equation (1). For example, in the case of double zoom display, the result is as follows.

Let (2) be an image stored in a storage device, and (2) be an image displayed on a display device. The required replacement can be expressed as . However, for simplicity, P and 9 are set as even numbers. In the case of transposition, it can be expressed in the following form by exchanging the column numbers and row numbers in equation (1).

In order to realize this replacement operation, the present invention introduces a high-speed rewritable control storage section at least regarding addresses, preferably also regarding write/read control and peripheral circuit control. Generally, three types of signals are required to scan an image. That is, a pulse signal Fφ indicates the start of one screen, a pulse signal Lφ indicates the start of one scanning line, and a pulse Mφ indicates the position of a pixel. This image storage device is also driven by these three pulses. FIG. 1 shows a schematic configuration of one embodiment, and the entire device is designated by the symbol -.

Counter 1. This counts pulse signals. Counter l is Mφ
is counted and reset at Lφ.

The counter counts Lφ and is reset at Fφ.

Control memory 3. ψ is read out using the count value of counter I as an address and is stored in control memory! , 4 are read out using the count value of the counter as an address. As shown in Figure 2, the X coordinate of the image,
Once the X coordinate is defined, the control memory 3 provides control information on the X coordinate for reading, the control storage section provides control information on the X coordinate for writing, and the control memory S provides control information on the X coordinate for reading. Control information for the X coordinate for writing is read out from the control memory 6, respectively.

The readout information of the control memories 3 and 5 is combined and used for readout control of the storage section /l. register 7, ff,
Reference numerals 9 hold these control information, and they are a read address register, a storage section control register at the time of reading, and an output control register, respectively. The read information of the control memories q, 6 is used for write control of the storage section /I, and these are stored in the write address register 10. Write storage control register //, input buffer control register 1
2.

The control information of the read storage control register t and the write storage control register // is held in combination in the storage control register 13. For example, this information may include:
These include read/write instructions for the storage unit 11, instructions to validate/invalidate the storage unit control information itself, and the like.

Depending on the read/write instruction from the storage control register 13, one of the read address and write address is selected by the address selection unit/44 and held in the address register/j, and is used as the address for the storage unit/1. Become.

The storage unit it consists of a memory integrated circuit.

The reading and writing speed of an image storage device determines the quality of the images handled, so the faster the better. On the other hand, the reading and writing speed of a large-capacity memory integrated circuit is not necessarily sufficient. Therefore, an output buffer /4. Place the input cross 7 a 17. The output buffer control register t controls the input buffer of the output buffer 'γ16, and the register 1 holds control information for the input buffer 17.

FIG. 3 shows an example of the word structure of the control memory of the storage device for an image of maximum 512 x 512 pixels. output buffer,
The size of the input buffer is 8 pixels. The meaning of each bit is as follows.

ν勺. , nfit: Storage device read/write specification.

axo, , wxo, + 'ayo1. wyo,
: Indicates whether the read word is valid or invalid.

RXO,, RYOo: Indicates whether to replace the output pixel from the storage unit with 0.

wxo, wyc, : Indicates whether to replace input pixels to the storage unit with 0.

RXA, , RBF, ~. : Specify the X coordinate when reading.

RBP, ~. is the address of the output buffer, RXA, ~.

are the lower 6 bits of the address of the storage unit.

R”8MI: Y coordinate at the time of reading. Corresponds to the upper 9 bits of the address of the storage unit.

WXA, , WBF, ~. : Specify the X coordinate when writing.

WBF, ~. is the address of the input buffer, WXA, ~.

are the lower 6 bits of the address of the storage unit.

WYA... : Y coordinate when writing. Corresponds to the upper 9 bits of the address of the storage section.

RXO, Near address RYA, -6, RXR, ~. Instructs to write the information in the storage specified by to the output buffer.

WXO0 near address wY person, ~. 1w'xinstructs to write the contents of the input buffer to the designated storage section.

The period is t(!rMφ. Regarding the control of the output buffer and the input buffer, taking the read time as an example, considering the read time of the storage section, BY, ~. and R are set in advance.
XA, ~. The storage unit address is specified by 81, and after 81 elapses, the read information for 8 pixels is written into the output buffer, and then one pixel at a time is outputted at a period l according to RBF, . The same applies when writing. Also, R/V
, , R/V, since the read/write operation of the storage section is changed every 81 times, it is possible to read and write at the same time, although it looks good. However, in this case, the read/write speed is halved.O Substitution α) Each term in each row of the equation corresponds to one word. Each line of the substitution (1) formula, in which the addressing part in the word represents a column number or a row number, can be relatively easily converted into a sequence of control words (a type of microprogram). Connect a minicomputer or microcomputer to this image storage device,
By generating word strings and loading them into control memory,
All operations expressed in the form of substitution (1) can be executed.

Note that each control memory 3, 44 . ! , 4, the shift operation is possible by changing the load address of the word string. However, the transposition operation can be performed by changing the contents of control memories 3 and ψ, and control memories S and 6, respectively. 〇The image storage device 20 can be used as an image input device or an image display device. , an example of application in combination with an image processing device is shown in Fig. 4,
It is shown in FIGS. 5 and 6.

In FIG. 4, a signal M necessary for the operation of the image storage device J
φ, Lφ, and Fφ are supplied from the television camera control section 1. The output video signal of the television camera n is digitized by an AD converter and input to the main image storage device J. It is assumed that television camera n takes images using interlaced scanning, and the size of one input image is 512 x 480 pixels. If the captured image is Can store input images. (4)
The first row of both permutations of the equation represents the pixel sequence of the input image. The second line is stored in the image storage device 20 as described above.
This can be realized by the control memory of It is sufficient to load the control word string corresponding to the second row of column permutation into the control memory 6 of FIG. 1 and the second row of row permutation into the control memory 6.

In FIG. 5, a signal M necessary for the operation of the image storage device I is shown.
φ, Lφ, and Fφ are supplied from the television monitor control section J. The output pixels from the image storage device J are converted to analog by a D-person converter j and displayed on a television monitor J. The image stored in the image storage device J is displayed! , then the image size is set to 512 x 512, and the following replacement can be considered. For this purpose, the control memory 3 in FIG. 1 must contain the first row of column permutation, and the control memory S must contain the first row of row permutation.
Loads the control string corresponding to the row.

In the application example shown in FIG. 6, two image storage devices I (θa and θb) are used, and the signal M required for operation is
φ, Lφ, and Fφ are supplied from the one-image calculation control section 27. The image processor U performs calculations on the output pixels from the first image storage device f and θα, and the result is transferred to the second image storage device θb.
is stored in

As an example, if we consider an operation in which the image 2, which is the result of adding a constant value 1 to the image 1° in the first image storage device θa, is stored in the second image storage device θb, the required replacement is 6
) is the formula. Of the open side memory of the first image storage device Of the control memory of the image storage device θb, the portions d and 6 in FIG.
5) Load the control string corresponding to the second row of both permutations of the expression. Note that depending on the type of calculation, the image storage device
, θb may be present in plural numbers.

Also, one image storage device m is connected to both of these image devices θ.
It may also serve as the functions of α and 0h.

It is also possible to construct an image processing apparatus that integrates the input, display, and calculation functions shown in FIGS. 4, 5, and 6, and FIG. 7 shows an example of such an application. Here, seven image storage devices are used (21 each)-,,20-,.

...indicated by r+).

The image input section X is constructed using the television camera n, television camera control section J/, and AD converter shown in FIG. 4 as elements. This image input section X and each image storage device J-1 to J6. are combined in the manner described in connection with FIG. 4, so the input t! These image storage devices 20-, ~co0- from A30.

You can input images to.

The image calculation unit 3/ is constructed using the image calculation unit U and the image calculation control unit core shown in FIG. 6 as elements. Each of the image storage devices J-1 to m-7 in FIG.
This corresponds to the output side image storage device 0a and the input side image storage device θb in FIG. Since the image calculation unit 31 in FIG. 7 and each image storage device are coupled in the manner described in connection with FIG. By using it as , calculation becomes possible.

The image display section 32 is constructed using the D person converter j, the television monitor control section, and the television monitor control section shown in FIG. 5 as elements. Signals Mφ necessary for the operation of the image calculation section 3/, the three image display sections, and the image storage device I~& in FIG.
, Lφ, and Fφ are common. Since the image display section 32 is connected to the data fin that inputs the output signal of the image calculation section 31 to each image storage device, it displays the calculation results by the image calculation section 31. If the operation of converting an input pixel directly into an output pixel is viewed as one operation, the contents of each image storage device will be displayed.

As explained in detail above, the present invention provides image input,
In the image storage device required for display and calculation, high-speed control storage is preferably used in the control section, and control information is read out using image scanning signals, which not only simplifies the circuit, but also Since the contents of the control memory can be rewritten at least in the order of address designation, and preferably in relation to other information as well, it is possible to adapt to various forms of use, and thus provides an extremely effective means for configuring an image processing apparatus. be.

[Brief explanation of drawings]

Fig. 1 is a schematic configuration diagram of one embodiment of the present image storage device;
Figure 3 is an explanatory diagram showing a coordinate system on an image, Figure 3 is an explanatory diagram showing an example of the word structure of control memory, Figure 4 is a schematic configuration diagram of an example of an image input device, and Figure 5 is an image display device. FIG. 6 is a schematic diagram of an image processing device as a first application example of this device, and FIG. 7 is a schematic diagram of an example of application to an image processing device. In the figure, 3. u, 3.4 is a control storage unit, l♂ is an image storage unit, 21), :10a, 20h, 20, ~
20-. li is the entire image storage device. Fang 2 figures, 3 figures, 7'4 figures, 5th! ! 1 1@, Yu, FΦ

Claims (1)

[Claims] An image storage unit comprising a pixel storage unit with multiple rows and multiple columns,
In an image storage device that selectively writes and reads pixels in each of the pixel storage units corresponding to addresses specified by addressing information, storing the addressing information in a rewritable control storage unit; An image storage device characterized in that reading is performed in synchronization with an image scanning signal.