JPS61186993A - Frame memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for displaying an image on a raster scanning display section and performing various image processing.

[Prior Art] Conventionally, there is a device of this type as shown in FIG. In the figure, (1> is a memory that stores display signals for multiple pixels at one address, and (2) is a memory that counts the master clock φ of a predetermined period and transfers the display signals stored in the memory (1) to an address. An address counter that generates an address signal ADR for reading in units, (3) is an address signal A output from this address counter (2).
a display control signal generation circuit that generates a display control signal DCNT for a raster scanning display section (not shown) based on the
4> is an address signal conversion circuit that changes the address signal ADR output from the address counter (2) by one address in the middle and inputs it to the memory (1); A parallel/serial converter (6) is the address counter (2) which converts the display signal DD in units of one address into a display signal dd in units of one pixel and outputs the same.
A memory control circuit (7) generates a read/write control signal RWC for a display signal to the memory (1) and a conversion control signal CC to the parallel/serial converter (5) based on an address signal ADR output from the memory (7). When accessing the memory (1) from the processing device (not shown), an address switcher selects the address signal ADRo for the access and inputs it to the memory (1); (8> is the memory from the data processing device); (1) A data bus switch that couples the display signal DD to be read/written by accessing to the data bus DB of data processing 1; (9) controls the display signal DD in units of one pixel by the display control signal DCNH; A video control circuit that supplies a video signal input to a raster scan type display.

By the way, when the memory control circuit (6) receives the read/write signal R/W from the data processing device to the memory (1), it switches the address switch (7) to the data processing device side, and also switches the address switch (7) to the data bus switch ( 8) to the data bus DB of the data processing device.

In this configuration, when the data processing device is not accessing the memory (1), the address signal ADR output from the address counter (2) is sent to the address converter (4) and the address switch (7). to the address input of the memory (1). Further, the address signal ADR is input to the display control signal generation circuit (3) and the memory control circuit (6>.
), a display control signal consisting of a synchronization signal synchronized with the raster scanning of the raster scanning display section and a signal indicating an effective display period is generated and input to the video control circuit (9).

On the other hand, in the memory control circuit (6), a read/write control signal RWC for reading out the display signal DD in units of one address in the memory (1) is formed, and the read/write control signal RWC in units of one address is read out in units of one pixel. display signal dd
Control 11 signal CC and load signal L for converting to
D is formed, the signal sRwc is input to the memory (1) and the signals CC and 1, D are input to the parallel/serial converter (5).

As a result, the display signal DD stored in the memory (1)
is sequentially output in units of one address, and after being converted into a display signal dd in units of one pixel in a converter (5), it is input to a video control circuit (9). Then, the video control circuit (9) synchronizes the pixel-by-pixel display signal dd with the raster scan and sends it to the display section as a video signal V within the effective display period. As a result,
An image corresponding to the display signal DD stored in the memory (1) is displayed on the display section.

FIG. 6 shows the address signal conversion circuit (4) assuming that display signals raJ, rbJ, rcJ, and rdJ for four pixels are stored in one address of the memory (1).
Display control signal DCNT, address signal ADR1 display signal DD, control signals LD and CC, master clock φ when address offset value AOF is A OF, = O
, is a time chart showing the display signal dd, and the signal DC
This shows that the period after time t1 when NT becomes '1'' is an effective display period.Furthermore, in the display signal DD for four pixels read from the memory (1), the signal LD is non and the signal CC It is shown that the signal is loaded into the circuit (5) at the timing when IP I I+ rises, and is then sequentially sent out pixel by pixel by the signal CC.

By the way, when the address offset value AOF in the address signal conversion circuit (4> is set to AOF=1), as shown in the time chart of FIG. 7, the output from this conversion circuit (4) is The address signal @ADR- to be sent is advanced by one address, and at time t1J, the image corresponding to the display signal Doi, :w stored at the second address is displayed at time t1J, fourth down.

Therefore, by appropriately setting this address offset value AOF by the data processing device, it becomes possible to move and display an image in units of 4 pixels on the display screen.

[Problems to be solved by the invention] However, in the conventional device described above, the address counter (
Since the signal ADR, which is converted by adding 〇F to the offset value to the address signal ADR generated from 2), is simply input to the memory (1), the display image moves in units of one address. This method has the disadvantage that it is not possible to move images such as figures in desired pixel units.

The present invention has been made to solve these drawbacks, and its purpose is to provide a F&-/Me'E9 device that can move a displayed image in units of desired pixels. be.

Means for Solving Problem F J The present invention generates control signals etc. output from a memory control circuit based on address signals, and corrects the timing of control signals for the memory etc. in accordance with the address offset value. This is what I did.

[Function] Since the timing of control signals for memory, etc. is corrected according to the address offset value, the display start position moves according to the amount of timing correction, making it possible to display movement in the desired pixel unit. .

[Embodiment] Fig. 1 is a block diagram showing an embodiment of the present invention, which differs from the conventional one in that the address signal input to the memory control circuit (6) is given from the address signal conversion circuit (4). That's true.

FIG. 2 is a diagram showing the internal configuration of the address signal conversion circuit (4), in which an address offset value AOF given from a data processing device (not shown) is latched into a latch 40,
This latched address offset (address signal ADR output from the direct AOF and address counter (2)
are added by the adder 41, and the added value is sent to the address signal A.
It is configured to output as DR'''.

In this configuration, the address offset value AOF is AOF
When F=O, each circuit operates as in the conventional case, the timings of various signals are as shown in FIG. 3, and the amount of movement of the image on the display screen is rOJ.

However, when AOF=-5, the pixel period (indicated by the control signal CC) corresponds to two periods of the master clock φ, so the address signal ADR- is 2.5 times larger than the start time t1 of the effective display period. It is converted into a signal advanced by a pixel (5/2 pixels). Therefore, the read/write control signal R formed based on this address signal ADR''
WC, load signal LD and conversion control signal CC are also 2.5 at time t1 as shown in the time chart of FIG.
It is generated at a timing earlier by the number of pixels. As a result, 1-a is loaded into the converter (5) at time t2 in FIG.
The image is displayed starting from the f'cJ pixel among the pixel signals of ~rdJ.

In this embodiment, one pixel period is made up of two periods of the master clock φ, but it may be made up of one or more periods. Furthermore, one address of the memory (1) stores display signals for four pixels, but as explained above for two or more pixels, in the present invention, not only address signals for the memory but also display signals for the memory are stored. The timing of control signals, etc. is also modified according to the address offset value with respect to the signal that is the basis of the display section, so the display image can be moved by the desired number of pixels with a simple circuit configuration, and the display image can be moved by the desired number of pixels. This is extremely convenient for image processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the internal configuration of an address signal conversion circuit, FIGS. 3 and 4 are time charts for explaining the operation of the embodiment, FIG. 5 is a block diagram showing the configuration of the conventional device, and FIGS. 6 and 7 are time charts for explaining the operation of the conventional device. (1)...Memory, (2)...Address counter,
(3) Display control signal generation circuit, (4) Address conversion circuit, (5) Parallel/serial converter, (6)
...Memory control circuit, (9)...Video control circuit. Agent Patent attorney Masuo Oiwa (2 others) Figure 1 Figure 2 4 years old 1--------1-----J5 Kiromoto''c3 minutes stone.<6 Kuro 88° call

Claims (1)

[Claims] a memory that stores display signals for a plurality of pixels in one address; an address counter that counts a master clock of a predetermined cycle and generates an address signal for reading out the display signals stored in the memory in units of addresses; a display control signal generation circuit that generates a display control signal for the raster scanning display section based on the address signal output from the address counter; a parallel/serial converter that converts a display signal in units of one address read from the memory into a display signal in units of one pixel and outputs the display signal, and an address signal output from the address counter. a frame memory device comprising a memory control circuit that generates a read/write control signal for a display signal to the memory and a conversion control signal for the parallel/serial converter based on the memory control circuit, wherein the memory control circuit is changed by the address signal conversion circuit. A frame memory device characterized in that the frame memory device is configured to generate the read/write control signal and the conversion control signal based on the address signal.