SU1536368A1 - Information input device - Google Patents

Abstract

The invention relates to automation and computing and can be used in technical vision systems and in automated image processing systems as a means of inputting visual information into an electronic computer memory or temporarily storing it in its own memory. The purpose of the invention is to expand the functionality of the device by providing two-way communication with the EMW and by providing autonomous and synchronous with the external video signal modes of operation. In the device, in comparison with the prototype, the functionality is expanded by providing the possibility of visual observation of the information stored in the device memory, by providing the possibility of exchanging information with a computer on rectangular image fragments, by allowing the exchange of information not only in the direction from the device memory to computer memory, but also in the opposite direction, by ensuring reliable regeneration of the stored information in the device memory and by ensuring the operation of the device offline mode and in synchronous with an external video signal mode. In addition, in the proposed device, the memory requirement is reduced by M times, where M is the size of the group shift registers used. 1 hp ff, 6 ill.

Description

viaanagroup comz formation of television sweep signals.

The device includes a de-information sensor, video amplifier 2, logo-digital converter 3, pu 4 shift registers, a group of data mutators, a group of 6 buffer registers, a group of 7 memory blocks, a video signal forming unit 8, a video control unit 9, a synchronization unit 10, a control unit 11, address switch I2, address counter 13, regeneration counter 14, counter Y coordinates 15, counter K coordinates 16, fragment width counter 17, register X coordinates 18, fragment width register 19, first 20, second 21 and third 22 elements OR, first driver 23 impulses c, the fourth element OR 24, the first 25 and the second 26 elements AND, the memory filling counter 27, the second formaker 28 pulses, the third element AND 29, the first 30 to the second 31 triggers, the computer interface unit 32, the delay element 33, the fifth element OR 34, the generator of 35 clock pulses, the third trigger 36, the counter 37 points in a word, the counter 38 words in a line ,, - the counter 39 lines in the frame, the first 403 second 41 and the third 42 decoders, output register 43, block 44 sync pulse from the full video signal, fourth 45, fifth 46, sixth 47, seventh 48, eighth 49, ninth 50, tenth 51 and eleventh 52 elements AND, 53 and seventh 54 elements OR, delay element 55, fourth 56, fifth 57 and sixth 58 triggers, third 59, fourth 60 and fifth 61 pulse shapers and comparator 62,

Video sensor 1 (FIG. 1) is a functional module designed to receive a standard video signal. Video amplifier 2 is designed to enhance the video signal to the level necessary for normal operation of the analog-digital converter 3.

The synchronization unit 10 is designed to: generate clock sampling pulses controlling the operation of the analog-digital converter 3 and moving the digitized information in the group of shift registers 4; to generate control signals generated during each cycle of accessing the PA

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m tee; for generating television sweep control signals; to synchronize the generated signals in accordance with the external video signal coming from the video amplifier 2.

Discretization clock pulses (first output of synchronization unit 10) are generated by a clock pulse generator 35 (Fig 2). The control signals of the memory access cycles (the third output of the synchronization unit 10) are generated using a 37 point counter in the word and a third decoder 42. The 37 point counter in the word counts from the generator 35 modulo m clock, where m is the number of dots in word or number of bits of each shift register group 4 (figure 1). From its output, the 1-bit code of the sequence number of a point in the next word, where 1 is equal to the number 1 G (t), rounded to the whole upwards, a log (-) indicates the binary logarithm function, is fed to the input of the third decoder 42, which made in the form of a permanent storage device (ROM) programmed so that its output bits generate signals whose frequency is m times less than the frequency of the sampling clock, and the beginning and end times of each pulse depend on the requirements for work co indiscrete memory chips used in the memory group 7. These output signals of the third sync block 10 is supplied to these blocks of memory cycles and form an access to its cell. In one of the bits of the third decoder 42, at the end of each memory access, a short signal is generated. The end of the call is sent to the fifth input of the control unit 11 via the third output of the synchronization unit 10 (FIG. 1), where depending on its mode of operation.

The television sweep control signals are generated. With the help of the word line 38, the line 39, the first 40 and second 41 decoders, and the output register 43 (FIG. 2), the counters 39 and 38 divide one frame of the television time base, respectively. lines in the frame and C words in each line, where, and

B - the number of points in each row. The number of lines in frame A depends on the standard used by the video signal, and the number of words in each term C must be an integer and satisfy the equation ,.

de

-sgr t

trH

Pp

ftr-m-C or C tcrp ---,

the period following the television sweep lines,

respectively the period and the frequency of the sampling clock

one

(tr- | -r).

: standard TV (ms,),

g

For example, when a hot signal

at a clock frequency of 13.5 MHz and at m 16, the number of words in a line is equal to C 54.

The counter 38 words per line counts modulo C the overflow pulses from the counter 37 points in the word. The counter of 39 lines in the frame, in turn, modulo A counts the overflow pulses from the counter to 38 words per line. Consequently, at each time point, the output of the counter is 39 lines per frame

and is displayed on the screen during storage. For example, in Fig. 6, all possible groups of lines are shown with the same television sweep signals in the case of forming a full standard television signal with A 626, m 16, C 54 depicting a white square of dimensions

About 512x512. Letters a, b, c, d in Fig. 6 indicate the level of the synchronization signal, the level of the blanking signal and the level of the black and white information signal, respectively.

5 The second decoder 41 is made in the form of a ROM programmed so that, in accordance with the increasing from time to time code, the number of the word in the line coming from the counter 38 and

0, in accordance with the line group code from the decoder 40, separate television scan signals necessary for the device are formed at the individual bits of its output (the input address of the second decoder 41 is formed by combining the bits of both of its inputs) "These signals through the output register 43 are fed to second, fifth and sixth exits of block 11

There is information about the current synchronization number 30. Output register 43

TV scan lines that enter the input of the first decoder 40e and the output of the 38 words in a line counter shows information about the current word number in the next scan line received at one address input of the second decoder 41, to another address input of which information comes from the output of the first decoder 40 .

The first decoder 40 is made in the form of a ROM programmed so that for each line of the next frame of the video signal, in accordance with the code of its number received at the input of the decoder from the counter 39, the output of the group of lines to which the given line belongs is output. Telescoping lines that have the same video signal form over the length of the entire line belong to one group of lines, subject to the condition that

Depending on the program stored on the ROM, the second decoder 41 can generate the following television sweep signals at the output bits: a signal of a mixture of horizontal and frame sync pulses that receive a high level only at those times when the video signal being generated must be above the synchronization level a ( 6); The signal is a simulated video signal that depicts a simple figure — a white rectangle, a set of blanking pulses that accept the determining format and location of the level at those moments of time, that part of the video information frame, when the generated video signal of the torus is processed by the device, t. e. is remembered when entering to exceed the level of quenching b (Fig. 6);

Signal Frame receiving active

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It is used to eliminate interference received during transients when switching ROMs from one address to another. Register 43 is gated with an overflow signal from a counter of 37 points in a word. The leading edge of this signal records the steady state information in the output register 43, and the falling edge changes the contents of the 38 words in a row counter and 39 rows in a frame, and thus starts the next process of switching the decoders 40 and 41 to a new address.

Depending on the program stored on the ROM, the second decoder 41 can generate the following television sweep signals at the output bits: a signal of a mixture of horizontal and frame sync pulses that receive a high level only at those times when the video signal being generated must be above the synchronization level a ( 6); a signal of a damping pulse signal that takes a high level at those times when the video signal being formed must

blanking pulses that receive a high level at those times when the video signal being formed must

exceed the level of quenching b (Fig.6);

blanking pulses that receive a high level at those times when the video signal being formed must

Signal Frame receiving active

the level when the formed video signal must be higher than the black level in or equal to the white level g (Fig.6); a short frame sync pulse generated at the end of every second half-frame.

The signals of the mixture of lowercase and frame sync pulses and a mixture of damping pulses taken from two bits in the main decoder 41 through the corresponding bits of the output register 43 form the second output for synchronization 10 and arrive at the second input of the video signal forming unit 8 (, Fig.))) Signal The frame formed by the third bit of the output register 43 () or the fifth output of the synchronization book 10 (FIG. 1) goes to the second control input of the switch -.2 of the address and to the fourth input of the control unit 11. The frame clock generated at the fourth bit of the output register 43 (.2) or at the sixth output of the synchronization unit 10 (FIG. L) is fed to the second run of the address counter 13 and to the clock input of the second trigger 31.

The signals generated by the external video signal received from video amplifier 2 are synchronized with the help of block 44 more than the sync pulse from the full video signal (figure 2) and the third trigger 36. If an external video signal starts at the input of block 44, then output signals appear in cip and frame pulses, which post / pack on the cleaning inputs of the counter 38 words in a line and the counter 39 lines in a single bed and seven together cause the television sweep control signals to be generated (blocks 38, 39, 40 , 41 and 43) work synchronously with an external video signal. In addition, the lower-case pulse, the duration of which is more than one but less than two cycles of accessing the memory, comes from block 44 to the reset input of the third trigger 36 and allows it to go into one state at the moment when the counter overflow pulse appears on its clock input 37 points in a word, i.e. at the end of the next cycle of memory accesses. The active signal from the trigger output

36 arrives at the counter reset input

37tochek in the word and forbids him to count the clock pulses from the generator 35 and thereby delays the production

the next memory access cycle. At the moment of termination of the line pulse from block 44, the trigger 36 goes to the initial state and the counter 37 begins to count the cycles of the new memory access cycle. Thus, the trigger 36 during the action of the line pulse from the block 44 allows the counter of 37 points in the word and the third decoder 42 to complete the next memory access cycle, and the new cycle to start exactly at the moment of the end of this pulse, thereby exacting the synchronization block 10 generated signals to an external video signal

Fig. 4 shows one of the possible variants of the sync pulse allocation unit 44 from the full video signal; Fig. 5 shows timing diagrams explaining its operation.

The full video signal from video amplifier 2 (Fig. 1) is fed to one input of comparator 62 (Fig. 4), to the other input of which a threshold voltage is applied. The threshold must be selected between the level of the synchronization signal and the level of the blanking signal. In this case, a mixture of sync pulses (figure 5) appears on the output of the comparator, which sets the fourth trigger 56 on the leading edges of its pulses. The signal from the output of the trigger 56 on the leading edges of its pulses triggers the third 59, fourth 60 and fifth 61 drivers of the pulses. Fourth shaper 60 produces pulses whose duration is longer than half the length of one scan line. Thus, each pulse generated by shaper 60e begins at the moment of arrival of the next leading edge from trigger 56 (at the beginning of the line) and ends in the second half of the line. Here, the pulse from the inverting output of the former 60 begins in the second half of the next row and ends at the end of this row (Fig. 5). Immediately after starting the imager 60, the pulse from its inverting output resets the trigger 56 and, until the second half of the next line, does not allow it to go back to the unit state again. Thus, the establishment of the trigger 56 by the leading edges of control pulses starting from the middle of the unwind line is prohibited.

The third driver 59 generates pulses whose length is more than one and less than two memory access cycles. These pulses are the output horizontal pulses of a block (Fig. 5).

The fifth pulse shaper 61, similarly to the fourth shaper 60, at the inverting output produces pulses starting in the first half of the next row and ending at the end of the row (Figure 5). The frame sync pulses of the first and second half-frames are different in that in the first half-frame they start from the beginning of the line, and in the second from the middle. Trigger 57 produces half-frame pulses starting in the second half of the line (Figure 5). These pulses reset the trigger 58. Thus, the trigger 58 is set only if the half-frame pulse starts at the beginning of the line and is reset after the trigger 57 is set. Therefore, a sync pulse generated during the half-frame pulse of the first pulse is formed at the output of the trigger 58 a half frame starting in the first half of a line and ending in the second half (figure 5).

Introduction to the device above

The described synchronization unit 10 (Fig. 1) allows processing the video signal from any sensor: a television camera, a video recorder, a communication line, a video signal simulator or synthesizer. The ability to change the programs stored in the ROM of the decoders 40 and 41 (Fig. 2) allows changing the standard of the video signal used, as well as generating additional television scanning signals. For example, if a television sensor is used, which requires horizontal and vertical sync signals for operation, then additional bits of the second decoder 41 can be programmed to generate such signals, and additional outputs of the synchronization unit are connected to the inputs of such a video signal sensor. In this case, the generated signals are not synchronized with the external video signal. The described features of the synchronization unit, as well as 5 0 5 o

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the same possibility of its operation both in autonomous mode and in synchronous mode with an external video signal expands the functionality of the device.

The video signal generator 8 (FIG. 1) is designed to receive an analog video signal that is used by the video control unit 9 to display information. The imaging unit 8 may be implemented as a digital-to-analog converter and an analog adder, the k-bit codes of the video information points received from the serial outputs of the shift registers of group 4 are converted into an analog signal by the digital-analog converter. To this signal, the signal of the mixture of horizontal and frame sync pulses and the signal of a mixture of damping pulses produced by the synchronization unit 10 are summed. The resulting analog signal is a complete video signal suitable for display by unit 9 of the video monitor.

Groups of 4 shift registers, data switches 5, buffer registers

6 and memory blocks 7 contain k identical shift registers, k identical data switches, k identical buffer registers and k identical memory blocks, respectively, where

k is the number of bits of the analog-to-digital converter 3 or the number by the device of the processed bits of the video information. In each memory block of group 7, a PG-bit word is written or read simultaneously, where m is the number of bits of each shift register of group 4 or the number of video information points processed in parallel. Group

7 memory blocks in one cycle of a call simultaneously write or read k itr of the data bit word, i.e. m k-bit video reference points.

Each buffer register of group 6 is a shift register. Shifting the information of none of the bits in the g-bit registers occurs at the falling edge of the signal from the seventh control output of the computer interface unit 32 to the first control inputs of the buffer registers of group 6.

The number r is equal to the ratio

to the whole in the direction of the smaller

value, and the number n - the computer word width of the computer. The buffer registers of group 6 are connected to the computer interface unit 32 so that the j-th bit (r) of the serial input and the serial output of the i-th (, k) buffer register of group 6 is connected to (j-) ki-i-th Discharge the output and input data bus of a block of 32 interface with a computer. Depending on the particular application of the device, the order of the connection may be different.

The memory filling counter 27 is designed to determine the point in time when either all information is transmitted via the serial outputs of the buffer registers of group 6 via the input bus of the interface 32 to the computer memory, or the buffer registers of group 6 are completely filled with information from the computer via the output bus of the block 32 mates The module p of the filling counter 27 is equal to

m

-, rounded to the whole side

Well, a larger value.

The computer interface unit 32 is intended for organizing the connection of the device with the computer when reading and writing visual information. This block implements the direct and program modes of computer memory access and contains input and output data registers for exchanging information of buffer group 6. registers, control per-control unit, allowing a computer to programmatically generate an active control signal from one of the six first control outputs of the block, and a computer memory direct access control circuit, which allows: to generate a start signal al at the eighth control output of the block at the beginning of the exchange of information between the computer memory and the device memory; receive a direct memory access cycle start signal at the control input; produce a signal for the end of the next cycle of direct memory access (FPI) at the seventh control output of the block. For example, as an interface unit with 3Bh of type Electronics 60 or DVK, an interface for direct access to memory of type IZ can be used, the decoder whose outputs are controllers is connected to the three output bits of the control register.

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the block outputs (from the first to the sixth).

The information input device operates in four modes: in the information storage mode; in the recording mode information; in the mode of transferring a fragment of the image from the device memory to the computer memory; in the mode of transferring a fragment of the image from the computer memory to the device memory.

When the device is turned on and in the absence of control signals from the computer interface unit 32, the device is in the information storage mode. On the closest frame clock from the sixth output of the synchronization unit 10, the address counter 13 is transferred to the initial (zero) state. The frame signal is generated at the fifth output of the synchronization unit 10 is fed to the second control input of the address switch 12, which, if there is no active level of this signal, connects to the address inputs of the memory blocks of group 7 the regeneration counter 14, and with the active level of this signal - counter 13 addresses. In addition, the Frame signal is fed to the fourth input of the control block 11, and in this block to the second inputs of the fourth 45, eighth 49, ninth 50 and eleventh 52 I elements (FIG. 3). In the absence of a signal, the ninth 50 and eleventh 52 elements And are closed, and the eighth element And 49 is open. The active signal level Frame ninth 50 and tenth 52 elements And opens, and the eighth element And 49 closes.

At the initial moment of time (after the frame sync pulse, the Frame is inactive and therefore the output of the memory blocks of group 7 (figure 1) is connected to the output of the regeneration counter 34. The signals from the third output of block 10 synchronization to the first control inputs of the memory blocks of group 7 reads the k tn-bit word at the address generated by the regeneration counter 14. At the end of the next memory access cycle, the fourth output of the synchronization unit 10 is generated Finished with a short signal handling, which is supplied to the fifth input 11 of the control unit, and this unit - the first

inputs 46, seventh 48, eighth 49, ninth 50, eleventh 52 elements AND to the input of the second delay element 55 (Fig. 3). At this time, only the eighth element AND 49 is open. the output or the fifth output of the control unit 11 (Fig. 1) enters the input of the regeneration counter 14 and increases its contents by one. During the next circulation cycle, the next word is read in the memory blocks of group 7 at the following address of the regeneration counter 14, Next reading process is similar to olzhaets until the occurrence of an active signal level frame. The regeneration counter 14 is not reset to the initial position. It always generates an increasing sequence of addresses. If counter 14 overflows, it continues operation from zero address.

At the time of the occurrence of the active signal level Frame at the fifth output of the synchronization unit 10, the address switch 12 connects the address of the address 13 to the address inputs of the memory blocks of group 7. During the next memory access cycle, the k-m-bit word from the memory blocks of group 7 is read at the address of this counter. At the end of the memory access cycle, the signal is the End of address, appearing at the output of the ninth And 50 (Fig 3), or at the fourth output of the control unit 11 (Fig. 1), enters the first input of the address counter 13 and increases its content by one. In addition, the End of Address signal appears at the output of the eleventh And element 52 (FIG. 3) or at the first output of the control unit 11 (FIG. 1). This signal is fed to the second control inputs of the shift registers of group 4 and, in parallel, writes to these registers just-read k m-bit information from the memory blocks of group 7.

During the next memory access cycle, the information stored in group 4 of the shift registers using clock sampling pulses arriving at the first control inputs of these registers from the first output of the synchronization unit 10, after 0

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The video signal is brought to the input of the imaging unit 8, where it is converted to analog form, summed with the signals from a mixture of horizontal and frame sync pulses and a mixture of blanking pulses from the second output of the synchronization unit 10. The thus obtained full video signal from the output of the imaging unit 8 is supplied to the video control unit 9, where it is displayed on the monitor screen. Simultaneously with the advancement of information in group 4 of shift registers, a group of 7 memory blocks reads the kim-bit word of information at the following address produced by the counter 13 of the address. By the end of the access, the read information is again recorded in parallel into the shift registers of group 4, of which by this time all the information of the previous cycle has already been pushed onto the video signal generator 8. Further, the process is similarly repeated until the point in time when the Frame signal ceases to be active. At this point in time, the address inputs of the memory units of group 7 are reconnected to the output of the regeneration counter 14 and the memory regeneration process begins again. In this case, k m-bit words read from the memory blocks of group 7 are not written to group 4 of the shift registers. In this case, the shaper 8 of the video signal receives information from the analog-digital converter 3, which is delayed by the shift registers of the group 4 by M sampling cycles. When the Frame signal becomes active again, the process of reading information with its display on block 9, the video control continues to incremental addresses generated by the address counter 13. At the end of the frame, the counter 13 of the addresses is reset to the initial state by the frame sync pulse from the sixth output of the synchronization unit 10 and the operation process of the device in the information storage mode starts to repeat in a similar way.

The transfer of the device to the information recording mode is performed by software on the initiative of the computer. For this, at the sixth output of the computer interface unit 32, an active signal appears, which is fed to the information input of the second trigger 31. According to

the leading edge of the nearest frame sync pulse coming from the sixth output of the synchronization unit 10 to the clock input of this flip-flop, which translates to a single state, which means switching the device to the information recording mode. A single signal from the output of the trigger 31 is fed to the control inputs of data switches of group 5, which in this case connect the parallel outputs of the shift registers of group 4 to the parallel inputs of the buffer registers of group 6, In addition, a single signal from the output of the second trigger 31 also goes to the third input of control block 11, and in this block - to the fourth input of the eleventh element I 52 (fig. 3), thereby prohibiting the passage of the parallel information recording signal to the shift registers of group A, and to the first input of the fourth element And 45, allowing the passage of the signal Frame arriving at its second input. Active signal The frame from the output of the fourth element I 45 is fed to the input of the seventh element OR 54, from the output of which or from the third output of control block 1 (Fig. 1) is fed to the second control inputs of the memory blocks of group 7 and for the duration of this slope translates these blocks in the recording mode information. In addition, the signal frame from the output of the fourth element And 45 (Fig. 3) is fed to the second input of the tenth element 51, which begins to pass the Start Start signals arriving at its first input from the second delay element 55. The Start Start signal is formed from the End signal circulation by delaying its element 55 la. the time required for the complete end of the next cycle of accessing and before the next cycle of accessing; In the information recording mode from the video information sensor 1, it scares the video amplifier 2 "where it is amplified to the level necessary for normal operation of the analog-digital converter 3 and is fed to the input converter A part of the video information signal is branched to the input of the synchronization unit 10, where it synchronizes the process of forming the internal clock signals of the device. On the analog-digital converter 3 signal

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video information on sampling clock pulses from the first output of synchronization unit 10 is converted into a sequence of k-bit codes, which are then fed to the serial inputs of group 4 shift registers. By sampling clock pulses, and to the first control inputs of shift registers Groups 4, video sample codes are advanced by filling in these registers. After m ticks, the shift registers of group 4 are fully loaded with video information about ha points of the image. If at this time the Frame has an active level j, then at the beginning of the next memory access cycle, the Start of Access signal coming from the output of the tenth element AND 51 (FIG. 3) to the input of the sixth element OR 53, and from the output of this element or s The second output of the control unit 11 (Fig. 1) onto the second control inputs of the buffer registers of group 6, writes into these registers k "m bit words of information received at the parallel inputs of these registers from the parallel outputs of the group 4 shift registers via data switches of group 5 So m points from The images loaded into the shift registers of group 4 through their serial inputs are transferred to the buffer registers of group 6, from where they arrive at parallel inputs to the information inputs of the memory blocks of group 7 and during the memory cycle writes to these blocks at the address generated by the counter 13 addresses. At the end of the memory access cycle, the End of Access signal, similarly as in the information storage mode, increases the contents of the address counter 13 by one. In the next cycle of accessing the memory by a signal, the Start of accessing the buffer registers of group 6 is written down a new k nr-pa3-r information word, which up to this point in time has already been loaded via serial inputs to the shift registers of group 4 from analog-digital converter 3 Next, the process of recording this word in the memory blocks of group 7 is repeated at the new address of the address counter 13. Parallel to the process of recording information in the memory blocks of group 7, the process of advancing information in the group 4 shift registers takes place. The successive inputs of these registers receive codes of new and new video information samples, and after m ticks these codes appear on the serial outputs of the registers of group 4 and are fed to the input of the imager 8 of the video signal, and about it to the input of the block 9 of the video controller, where they are displayed on the screen.

In the absence of an active signal level Frame, the output of the regeneration counter 14 is connected to the address inputs of a group of 7 memory blocks and the regeneration process is similar to the regeneration process in the information storage mode.

When the active signal level is removed at the sixth output of the 32 32–20 16 block, X coordinates. During computer operation, the second trigger 31 of the transmitted pulse, information is output from the leading edge of the nearest frame sync pulse from the sixth output of the synchronization block 10 the zero state, the device goes into the information storage mode and the last entered frame of video information remains recorded in group 7 of memory blocks. At the same time, the storage of information takes place 30 on the screen of the video control unit 9.

Before transferring the device to the modes of transferring a fragment of the image from the memory of the device to the computer memory or from the computer memory to the memory of the device, the parameters of this fragment are first programmatically set. For this purpose, the address of the coordinate At the upper edge of the fragment of the image is set on the output bus of the computer interface unit 32. A short pulse generated at the fifth control output of this block arrives at the second input of the counter 15 of the coordinate Y and records in it the information on the output bus. The module E of the counter 15 of the coordinate Y is equal to the number of lines of video information stored in the memory blocks of group 7, and its width is equal to the number of log (E), rounded up to the integer towards the larger value. If the device uses, through a horizontal scan, to ensure correct addressing of the video information lines, the low-order counter of the 15 coordinate Y is connected instead of the high-level discharge both at its input and at its output, and all

Noise bus of the interface with the computer is recorded in the register 18 of the X coordinate and from the output of the latter enters the information input of the counter 16 of the X coordinate. On the falling edge of the pulse, the information on the X coordinate is stored both in register 18 and in the counter 16. Module counter 16 x is equal to

-, which must be an integer, m

where F is the number of processed points from one line of video information.

2g The width g of the register 18 and the counter 16 of the X coordinate is equal to the number of log (G), rounded to a whole in the direction of a larger value. The output bits of the counters 15 and 16 of the Y and coordinate X ordinates are combined into one address bus, which determines the current address of the m-fc-bit cell in group 7 of memory blocks, into which m k-bit layer is written or read. during the communication cycle

 with a computer.

Similarly, the fragment width information is loaded. In this case, the computer on the output bus of the interface block 32 exposes information about the fragment width in the binary-additional code, i.e., in the form of a negative number defining the number of cycles. information exchange with a computer when transmitting one line of a fragment of the image. The signal at the third control output of the interface 32 of the fragment width information is recorded in the register 19 and the counter 17. Module and rae50

55

the remaining bits are shifted, respectively, by one bit to the left. Such a connection, with a sequential increase in the contents of counter 15, allows odd lines of the entered information to be addressed in the first half-frame, and even even in the second half-frame.

After the counter 15 is loaded, the computer coordinates, on the output bus of the interface block 32, exposes the address of the X coordinate of the left edge of the image fragment and programmatically generates

the fourth control output of this block is a short impulse c, which is fed to the control input of the register 18 of the X coordinate and through the second element OR 21 to the second input of the counter

16 coordinates X. During the action of a given pulse, information from the output

Noise bus of the interface with the computer is recorded in the register 18 of the X coordinate and from the output of the latter enters the information input of the counter 16 of the X coordinate. On the falling edge of the pulse, the information on the X coordinate is stored both in register 18 and in the counter 16. The counter module 16 x coordinates equals relation

-, which must be an integer, m

where F is the number of processed points from one line of video information.

The width g of register 18 and counter 16 of X is equal to the number of log (G), rounded to a whole in the direction of a larger value. The output bits of the counters 15 and 16 of the Y coordinate and the X coordinate are combined into one address bus, which determines the current address of the m-fc-bit cell in group 7 of memory blocks, into which m k-bit word is written or read from information exchange cycle time

with a computer.

Similarly, the fragment width information is loaded. In this case, the computer on the output bus of the interface block 32 exposes information about the fragment width in the binary-additional code, i.e., in the form of a negative number defining the number of cycles. information exchange with a computer when transmitting one line of a fragment of the image. The signal at the third control output of the interface 32 of the fragment width information is recorded in the register 19 and the counter 17. The module and the rae

1915

The width of the fragment width counter 17 coincides with the modulus and resolution of the counter 16 of the X coordinate.

The device is transferred to the mode of transferring a fragment of the image from the memory of the device to the computer memory when the active level is developed at the first control output of the computer interface unit 32 and at the software level on this unit to receive information from the input data bus to record it. in the computer memory via the direct access channel.

The active signal from the first control output of the computer interface unit 32 is fed to the first input of the first element AND 25, opening it, and through the third element OR 12 to the second input of the second element AND 26, also opening it. In addition, this signal is fed to the second input of the control unit 1 5, and in this block to the second input of the sixth element I 47 (Fig. 3), closing this element with the third input of the fifth element And 46 which opens ,

After the computer allows the interfacing unit 32 to operate in the direct memory access mode, a short Start signal is generated at the eighth control output, which goes to the second input of the filling counter 71 and converts it to its initial state. In addition, the Start signal through the first first element AND 25 and the fifth element OR 34 starts the first driver 23 pulses. This shaper produces pulses whose duration is more than one but less than two memory access cycles. The generated signal arrives at the second input of the third element AND 29: which is currently open by a high level signal that arrives at its first input from the second output of the first trigger} 0, the signal from the output of the third element and 29 through the second input of the fourth element OR 24 enters to the control input of the computer interface unit 32, thereby beginning the process of forming the signal. Starting the PDU cycle, which, on the trailing edge, will start the cycle of memory access. In addition, the signal from the output of the third element And 29 is fed to the information input of the first trigger 30, which is on the closest signal

o

five

0

6

L1

 15

50

45

6820

batted at the fourth output of the synchronization unit 10 and through the delay element 33 arriving at the clock input of the trigger 30, is translated into one | There is no condition. At the second output of the trigger 30, a low level signal f appears, which, having entered the second input of the element 29, prohibits the passage of the signal from the first generator of 23 pulses to the information input of the first trigger 30 and the second input of the fourth element OR 24. However, signal generation at the output of the element OR 24 continues, since at its third input there appears a high level signal (Exchange signal) from the first output of the trigger 30. This signal also goes to the first control input of the address switch 12 and is independently from the Ram-s signal arriving at its second control input, connects the output of the counters 15 and 16 to the address inputs of the memory blocks of group 7, the coordinates of the Y coordinate X, the exchange signal goes to the first input of the control unit 11, and this block - to the third inputs of the eighth 49 and eleventh 52 elements And, and closes them, to the second inputs of the fifth 46 and seventh 48 elements And, and opens them to the first input of the closed sixth element And 47. During the next memory access cycle from memory blocks of group 7 are read k m-bit words of information n About the address determined by the contents of the counters 16 and 15, the X coordinates and the Y coordinates (figure 1). At the end of the memory access cycle, the signal. The end of the access from the fourth output of the synchronization unit 10 is fed to the input of the delay element 33 and to the fifth input of the control unit 11. In this block, the End of Address signal passes through the open Fifth 46 and Seventh 48 And elements, as well as the Ninth And 50 element, which is open only if the Frame signal is active. From the output of the fifth element AND 46, the signal of the exchange ends to the input of the sixth element OR 53, from the output of which, or from the second output of the control unit 11 (FIG. 1), goes to the second control inputs of the buffer registers of group 6 and writes these to the parallel inputs registers just in group of 7 memory blocks read

211

information, since the information outputs of group 7 of memory blocks are currently connected to the parallel inputs of group 6 of the buffer registers via group 5 of data switches, and the control inputs of the latter lack the active level of the control signal. If the signals Exchange, Frame are active at the time of occurrence, the signal End of reversal from the output of the ninth element I 50 (FIG. 3) or from the fourth output of the control unit 11 (Fig. 1) goes to the first input of the counter 13 of the address and increases its content per unit. In addition, the signal End of the appeal from the output of the seventh element And 48 (Fig. 3) or from the sixth output of the control block 11

laziness (figure 1) is fed to the first input of the third element And 29

the counter dips 16 coordinates X and the counter-and prepares the trigger 30 to receive

ka 17 fragment width and increases the next signal from the first form their contents by one. If the level of 23 pulses is increased, the counter content increases by 17; the duration of the pulse produced by the width of the fragment occurs when it is transferred by the first driver 23,

completion, which means that all the words of the current line of the image fragment are transmitted, the overflow pulse from its output goes to the first input of the counter 15, the Y coordinate, increasing its content by one, and to the second inputs of the first 20 and second 21 OR elements. From the output of the first element OR 20, this pulse arrives at the second input of the fragment width counter 17 and loads it with the information input about the initial fragment width stored in the register 29. Similarly, the overflow pulse from the output of the second element OR 21 goes to the second input of the counter 16 of the X coordinate and loads it with information about the starting coordinate of the left edge of the fragment from the register 18 of the X coordinate. Therefore, by the signal End of the call coming from the sixth output of the control block 11 to the inputs of counters 15 and 17 the X and X widths of the fragment, the contents of the counters 15 and 16 of the Y coordinate and the X coordinates are modified so that if not the entire current line of the image fragment is processed, the address of the next word in this line is formed, i.e. the contents of counter 15 are unchanged, and the contents of counter 16 are incremented by one. If the entire current line of the image fragment is transmitted, then

22

The address of the first word in the next line of the fragment, i.e. the contents of the counter 16 coordinates X takes the value of the left edge of the fragment, and the contents of the counter 15 coordinates Y increases by one.

From the output of the delay element 33, the delayed signal End of the call enters the clock input of the first trigger and puts it in the zero state, since there is no high level signal at its information input at this time. The signal generated by the first trigger 30, the exchange, the duration of which is equal to one cycle of accessing the memory, ends. The signal from the second trigger output 30 is fed to

must be greater than the duration of one, but less than two cycles of accessing the memory so that the trigger 30 is guaranteed to be triggered by the End of exchange signal and so that it cannot trigger again, since the End of exchange signal appears asynchronously compared to the pulse of the first driver 23 Signal delay The end of the exchange on element 33 is necessary so that by this signal, even before the signal expires, the address has been successfully modified at the counters J5 and 16 of the Y coordinate and the X coordinate.

Since the Exchange signal arriving at the third input of the fourth element OR 24 has ended, the formation process

Signal start of the PDL cycle. On the falling edge of this signal, which enters the control input of the computer interface unit 32, the direct memory access of the computer starts in this block and the information from the serial outputs of the buffer registers of group 6 is transmitted through the input data bus computer memory

At the end of the cycle of direct access to

the memory of the computer at the seventh output of the block 32 of the conjugation appears a short signal. The end of the loop PDU, which is fed to the first control inputs of the buffer registers of group 6 and

the falling edge is moved by the PCF stored in this group on a ha of rows. Thus, on the successive outputs of the buffer registers of group 6, the following r, k-bit information points appear. The signal / end of the PDL cycle also receives the hd input of the second imaging unit 28 imp, and through the open second element 26 to the first input of the memory filling counter 27, increasing its content by one. On the back signal of the signal. End of the PDP1 t cycle, the shaper 28 generates an AI pulse, the duration of which is sufficient to prepare the computer support unit 32 for the new slm on the computer memory access. This i. bobbin with through the fourth element ИЫ) l not-1, drops to the controlling control of the internal control unit of the control unit 32 as a signal. to the PDL cycle, after which a new direct memory access to the computer is started and the next information transmission program is transmitted from successive outputs of the buffer registers g / p p 6 through the input bus of block 32 with the voltage in the computer memory- At the end of the next cycle, direct to ir; These computers at the seventh control unit 1 output unit of interconnection block 32 are outputted: the signal of the Konepins ia PDA and the transmission procedure of the iiFtbo SCCP is repeated for as long as the hedgehog doesn’t compete with it. counter 7 is silent; until it is counted. and all ilfigm. qi g which is recorded buffer 1st registers of group 6,

During the transfer of the h formation with h buffer, the register is group 6 s. .ai with t, a computer in the forward mode of data acquisition, until the exchange is generated. At the output of the first trigger 30, the memory blocks of group 7 -J, the shift registers of group 4 work in a similar way as in pei ve chrcion or formation, those. from group 7, the memory block is read by its lour-bits at the address of the counter 13 of the address or the counter 14 of the regeneration and the information is similar to the mode of the OTOUO storage on the screen of the block; 9 Vidgontrol, At the end of the cycle, the kilometer is about to access the computer memory signal. The end of the cycle PDP overflows the counter 27 of the memory and its contents becomes zero. Impuns lane; Sending from the output of the gateway 27 An instant epemge OR 34 triggers the first driver of the 23 pulses. The pulse from the output of this driver is fed to the information input of the first trigger 30 and the second input of the fourth element OR 24, delaying the falling edge of the signal. Starting the PDL cycle started by the pulse from the second

, the driver 28, At the nearest signal End of the call, arriving at the clock input of the first trigger 30, the signal produces a signal of 06 mt, which for the duration

The one-10th cycle of accessing the device’s memory terminates the normal stored-chi-chormation mode and during which the k слово th-th word of information j located at the address specified by the counters 16 and 17 of the X coordinate and the co-co-Y of the Y, is read from memory blocks of group 7 and through groups 5 of data computators on parallel inputs are written to the buffer

-, and other registers of group 6. At the root of this cycle, the contents of the counts 15 and 17 of the Y coordinate, the X coordinate and the fragment width of the / pot-.e addition, the exchange signal, post, are modified; And on the third input of the fourth element OR 24, it delays the appearance of the third edge of the signal. Starting the loop LDP1 1 until the end of the next cycle looks to the memory of the device. Next by. to the falling edge of the signal The start of the PDL cycle is entered into the next t cycles of direct access to the computer memory, and the sequence of the j file and computer memory contents and the buffer is transmitted again. RIH regkotrog group b, and the process of leredat-and information is similarly repeated

If the information on the fragment to be transmitted is determined by the information recorded in the fragment width register 9, then the height of this fragment depends on the programmable set number of the CRC-LOB direct access to the computer's F5, which must be a multiple of the number

Thus, the height of the fragment depends on the amount of information, tiepe-dyu in pz m 3Bi.i on the access direct j and the number of direct access transmitted cycles are determined by software,

After transferring the last portion of Shbeorg from group 6 of registers to memory, EVG produces the next cv:

where the second driver 28 through the fourth element OR 24 generates another signal. It starts the PDL cycle, but the computer interface unit 32 does not start more direct memory access cycles on the trailing edge of this signal.

After the transfer of the image fragment from the device memory to the computer memory is completed, the active level is programmatically removed at the first control output of the computer interface unit 32 and the device is completely transferred to the information storage mode.

The device is transferred into the mode of transferring a fragment of the image from the computer memory to its own memory when the active level is developed at the second control output of the computer interface unit 32 and when this unit is programmed to read information from the computer memory and output it to the output bus data block 32 direct access channel.

The active signal from the second control output of the computer interface unit 32 through the third element OR 22 is fed to the input of the second element AND 26. And opens it.

After the computer allows the interface unit 32 to operate in the direct access mode, a short Start signal is generated at its eighth control output, which enters the second input of the memory filling counter 27 and clears it. Simultaneously, the interface unit 32 generates the first cycle of the ave. 10

15

20

25

thirty

35

is per g bit. The process of sequential loading of these registers continues until they are completely filled with information from a computer, i.e. until the memory counter 27 is full. The overflow pulse from the output of this counter, similarly as in the previous mode of operation, generates an exchange signal at the first output of the first three hera 30, which also goes to the first input of the control unit 11. Since in this unit, in this mode, there is no active signal level from the first control output of the computer interface unit 32, the fifth And 46 element is closed and the Sixth And 47 element is open. Therefore, the signal exchange in control block 11 passes the open sixth element AND 47 and enters the input of the seventh element OR 54, from the output of which or from the third output of control block 1I this signal goes to the second control inputs of the memory blocks of group 7 and at the next access cycle It transfers these blocks to the recording-information mode. Therefore, the time of this memory access cycle k, m-bit layer from the parallel outputs of the buffer registers of group 6, is written into group 7 of memory blocks at the address generated by the counters 15 and 16 of the Y coordinate and the X coordinate. At the end of the cycle as before, the memory is modified by the contents of the counter 15 and 16 of the coordinates Y and X. At the end of the signal

access to memory, which in this data exchange begins again the cycles

The case starts programmatically. At the end of this cycle, the PDU information read from the computer memory is displayed on the output bus of the block 32 and the memory access and the process, as in the previous mode, continues until the weight of the image is transferred, the difference only

50

It goes to the serial inputs of the buffer 45 in that now the information is first of registers of group 6. The signal of the end of the cycle of the PLP from the seventh output of the interface block 32, like in the previous mode, shifts the information in the buffer registers of group 6, increases the content of the counter 27, and generates a signal. PDU, which, on the trailing edge, launches a new cycle of direct access to the computer memory. During this cycle, the next word of information is recorded on the sequential inputs of the buffer registers of group 6, and the contents of the latter are again shifted55

sequentially fills the buffer registers of group 6, and then in parallel is rewritten into memory blocks of group 7. After the fragment is transmitted, the active signal is programmatically removed at the second control output of computer interface unit 32, and the device returns to the information storage mode.

Thus, the proposed device, in comparison with the known functionality, is expanded by visual observation of information stored in the device memory.

five

0

five

0

five

is per g bit. The process of sequential loading of these registers continues until they are completely filled with information from a computer, i.e. until the memory counter 27 is full. The overflow pulse from the output of this counter, similarly as in the previous mode of operation, generates an exchange signal at the first output of the first trigger 30, which also enters the first input of the control unit 11. Since in this unit, in this mode, there is no active signal level from the first control output of the computer interface unit 32, the fifth And 46 element is closed and the Sixth And 47 element is open. Therefore, the signal exchange in control block 11 passes the open sixth element AND 47 and enters the input of the seventh element OR 54, from the output of which or from the third output of control block 1I this signal goes to the second control inputs of the memory blocks of group 7 and at the next access cycle memory transfers these blocks to write-information mode. Therefore, but the time of this memory access cycle k, the m-bit word from the parallel outputs of the buffer registers of group 6 is recorded in group 7 of memory blocks at the address generated by counters 15 and 16 of the Y coordinate and X coordinate. At the end of the memory access cycle similarly to the previous mode, the contents of the 15 and 16 coordinates of the Y and X coordinates are modified. As soon as the memory access is completed, the process continues, as in the previous mode, until the entire image fragment is transmitted, the difference is only

in the fact that now the information is first

sequentially fills the buffer registers of group 6, and then in parallel is rewritten into memory blocks of group 7. After the fragment is transmitted, the active signal is programmatically removed at the second control output of computer interface unit 32, and the device returns to the information storage mode.

Thus, the proposed device, in comparison with the known functionality, expands due to visual observation of information stored in the device memory, information exchange with a computer along rectangular image fragments, information exchange not only in the direction from the device memory into a computer memory. , but also in the opposite direction, reliable regeneration of the stored information in the device memory and device operation both in the autonomous mode and in the mode synchronous with the external video signal. In addition, in the proposed device, the speed requirement of the pa

m ti m times where ga used registers

rank of the group A. $

Claims (2)

1. A device for inputting information containing a video information sensor, a video amplifier, an analog-to-digital converter, a driver. video signal, video monitor block 5 group of buffer registers, group of memory blocks, first and second triggers, first and second pulse drivers, address counter, memory fill counter, first, second and third elements AND, and first element OR, video sensor output connected to the input of the video amplifier, the serial output of the buffer registers of the group is the serial output of the device, the first and the second inputs of the third element I are connected respectively to the initial output of the first trigger and the first He eats pulses, which is due to the fact that, in order to enhance functionality by providing two-way communication with a computer and by providing autonomous and synchronous with an external video signal, the modes of operation are group of shift registers, group of data switches, address switch, regeneration counter, counter of Y coordinate, counter of X coordinate, fragment width counter, X-chorcinate register, fragment width register, second to fifth OR elements, delay element, synchronization unit and control unit , in s control unit of the first through fifth ssogvetsg- venno connected to a direct output of the first trig - ge.ra, the third input of the fourth OR gate and to a first input of the switch upravp yuschim ,, address to the first inputs of the first AND gate and third 0 5,. 0 five 0 element OR v is the first control input of the device, with the direct output of the second trigger and with the control inputs of the data commutators of the group, with the fifth output of the synchronization unit and with the second control input of the address switch, with the fourth output of the synchronization unit and with the input of the first the delay element, the outputs of the control unit from the first to the sixth are connected respectively with the second control inputs of the group shift registers, with the second control inputs of the buffer registers of the group, with the second control inputs of the blocks n groups, with the counting input of the address counter, with the counting input. of the regeneration counter, with the counting inputs of the counters, X coordinate and fragment width, the first and second information outputs of the video amplifier are connected respectively to the information input of the analog-digital converter and the input of the synchronization unit, the first the output of which is connected to the clock input of the analog-to-digital converter and to the control inputs of the group shift registers, the second and third outputs of the synchronization unit are connected respectively to The information input of the video signal generator and with the first control inputs of the group memory blocks, the reset input of the address counter is connected to the sixth output of the synchronization unit and the clock input of the second trigger, the information input of the second trigger is the sixth control input of the device, the first, second and third the information inputs of the address switch are connected respectively to the outputs of the address counter, the regeneration and the coordinate of the X coordinate, the outputs of each bit of the aalo-digital conversion from the junction Connected respectively with the serial inputs of the group shift registers whose serial outputs are connected to the first information processor of the video signal generator, the output of which is connected to the input of the unit on the control panel, the parallel information output of the group shift registers is connected to the first information switch of the group data switch, the output of the address switch is connected to the address inputs of the groups group memory, parallel input of each group shift register is connected with the output of the group memory block and with the second information input of the data switch of the group, the output of which is connected to the parallel input of the buffer registers of the group whose parallel output is connected to the information input of the group memory, the second input of the third OR element is the second control input of the device, the first input of the first element OR is the third control input of the device and is connected to the control input of the format width register; the first input of the second element OR is the fourth control input of device and is connected to the control input of the register of X, the parallel-write input of the counter of the Y coordinate is the fifth control input of the device, the outputs of the first and second OR elements are connected respectively to the parallel-write inputs of the fragment-width counters and the X coordinate, the information inputs of the X-coordinate counters and the fragment width are connected respectively to the outputs of the registers of the X coordinate and fragment width, the output of the fragment width counter is connected to the second inputs of the first and second OR elements and with the input of the counter of the coordinate Y, the information input of the counter of the coordinate Y is connected to the information inputs of the registers of the coordinate X and the fragment width, with the information input of the buffer registers of the group and is the information input of the device, the first control inputs of the buffer 45 the group registers are connected to the first 40. The resident input is connected to the second input of the second element AND to the input of the second pulse shaper and is the seventh control input of the device, the output of the fourth element OR is the controlling output of the device, the first input of the fourth element OR is connected to the output of the second pulse driver, the second input of the fourth element OR is connected to the output of the third element AND, and to the information input of the first trigger, the clock input of which is connected to the output of the first delay element and vta- swarm input of first AND input is connected to fill the memory and the counter is reset eighth control input devices, output of the second AND element is connected to the counting input of the counter filling memory output per50 55 the parallel output of the word counter in line, the output register, the clock input of which is connected to the overflow output of the point counter in the word, to the counting input of the word counter in the line and to the clock input of the third trigger, the first, second and third information outputs of the output register are respectively second , the fifth and sixth outputs of the synchronization unit, the overflow output of the word counter in the line is connected to the counting input of the line counter in the frame, the output of which is connected to the input of the first decoder, the output of which is connected to the second CB address input of the second decoder, the output of the second decoder coupled to the data input of the output register. five 0 five 0 five The first element AND is connected to the second input of the fifth OR element, the output of which is connected to the input of the first pulse shaper, the first input of the fifth OR element is connected to the output of the memory filling counter, the second input of the second AND element is connected to the output of the third OR element. 2. The device according to p. Differs in that the synchronization unit comprises a sync pulse extraction unit from the full video signal, the input of which is the sync unit input, a third trigger, the reset input of which is connected to the first output of the sync pulse selection unit from the full video signal, the third decoder, the first and the second outputs of which are, respectively, the third and fourth outputs of the synchronization unit, the output of the clock generator is connected to the counting input of the point counter in the word and is the first output b Synchronization, the reset input of the point counter in the word of which is connected to the forward output of the third trigger, the parallel output of the counter of points in the word is connected to the input of the third decoder, the word counter in the line, the reset input of which is connected to the first output of the sync pulse from the full video signal, the counter rows in the frame, the reset input of which is connected to the second output of the sync pulse extraction unit from the full video signal, the first decoder, the second decoder, the first ad Resource input is connected to the parallel output of the word counter in the line, the output register, the clock input of which is connected to the overflow output of the point counter in the word, the counting input of the word counter in the line and the clock input of the third trigger, the first, second and third information outputs of the output register are respectively the second, the fifth and sixth outputs of the synchronization unit; the overflow output of the word counter in the line is connected to the counting input of the line counter in the frame, the output of which is connected to the input of the first decoder, the output of which is connected to the second CB address input of the second decoder, the output of the second decoder coupled to the data input of the output register. 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