JP3302685B2 - Semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to providing a structure of a memory cell of a semiconductor integrated circuit, in particular, an ultra-high-density integrated circuit (ULSI) at a 16M to 16 Gbit level. .

The present invention relates to a semiconductor device, in particular, a MIS (insulating gate) field effect semiconductor device having a microchannel type (hereinafter referred to as a μ-channel MISFET having a channel length of 0.03 to 1 μm or less, which is 1 μm or less) and connected in series thereto It is to propose a semiconductor device including a capacitor.

[Prior Art] Conventionally, as shown in FIG. 1, the structure of a MIS FET or a capacitor connected in series with the MIS FET is formed on one surface of a semiconductor substrate (1) on which a field insulator (2) is selectively provided. A drain or source (21), which is effectively a drain or source and constitutes a lower electrode of the capacitor, is provided relative to the gate insulator (2), the gate electrode (18) and the source or drain (14); A capacitor insulator (22) and a counter electrode (23) were provided.

Conventionally, MIS FETs have a channel formation region in the lateral direction parallel to the upper surface of the semiconductor substrate, and a pair of source, drain (14) and drain or source (21) must be formed symmetrically under both ends of the gate electrode on the semiconductor substrate. They were formed by forming the same plane. Furthermore, 1Tr / Cell (one MI
In this case, the gate electrode (18)
Is provided not only on the gate insulator (2) but also on the upper surface of the counter electrode (23) of the capacitor. This is the source or drain (14) under one end of the gate electrode (18).
Is self-aligned with one end of the drain or source (21) being the other end of the gate electrode. The other end (18 ") of the gate electrode is made larger than the channel region (6) by a poly II (polycrystalline silicon film (2) which is made to compensate for variations in mask alignment accuracy.
3) and (18)). However, even in such a case, it is impossible to reduce the channel length to 1 μm or less due to the restrictions on the photo-etching process. Cuts and the like occurred, making it impossible. The present invention actively utilizes this step in reverse.
A gate electrode of the MIS FET is provided, and the gate electrode is formed so as not to extend above an opposing electrode of the capacitor having a convex shape.

"Object of the present invention" The present invention is such that a current flows in a vertical direction in a channel forming region under the gate electrode, and the channel length is 0.03 to 0.03.
One MIS FET with extremely small size of 1μm
And the size of the 1Tr / Cell, in which capacitors are connected in series, are reduced to about 1μm □ to 10μm □.
It is an object of the present invention to provide an element structure for ULSI that can be made up to 16M to 16G bits.

The present invention provides an asymmetric MIS by forming the channel forming region in a vertical direction, that is, a vertical channel type, and forming a source and a drain in a horizontal direction so as to be easily connected to one electrode of a capacitor. It is in providing FET. That is, a convex single-crystal semiconductor region is provided on one main surface of a semiconductor substrate, and the upper portion thereof is connected to one source or drain of the MIS FET by LDD (a drain having a relatively low impurity concentration, ie, a light source).
Doped drain), the side of this convex region is a vertical channel forming region, and the bottom of the semiconductor substrate is a drain or source of LDD configuration.
These source or drain and the drain or source of improving the drain breakdown voltage in the impurity concentration of ^{3 × 10 16 ~5 × 10 18} cm -3 low concentrations, i.e. with the LDD, rectangle the corners of the protruding region Alternatively, a triangular gate electrode is provided.

The upper lateral portion of the gate electrode substantially coincides with the source or the drain, is coincident with the edge of the source or the drain, or is provided slightly larger on the source or the drain side, and is located below the second impurity region thereon. In addition, the gate electrode is prevented from having an offset structure, and a margin is provided for manufacturing.

In addition, a second impurity region is provided for the source or the drain,
In addition, the drain or the source is provided with a first impurity region having a high impurity concentration with a lateral surface in order to facilitate ohmic contact with the first impurity region and one electrode of the capacitor. Then, a stack-type capacitor (stacked capacitor) is provided by serially connecting a capacitor in which a conductor, an insulator, and a conductor are electrically stacked through the first region.

 An embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 In this embodiment, a 1Tr / Cell structure of the present invention and a manufacturing process thereof are shown in FIG.
Two FETs are provided as a pair using a convex region of a semiconductor substrate.

Semiconductor substrate such as silicon single crystal semiconductor (100), P type 1
I chose 0-500Ωcm. A convex region (35) was formed on the single crystal substrate using the first photomask.
For the fabrication, anisotropic etching of a silicon single crystal substrate may be formed using the photoresist (32) as a mask.
It is important that this corner has a very sharp vertical surface at 90 ° to the upper surface of the substrate. The height of this projection is 0.5 ~ 4μ
m, for example, 1.5 μm.

Silicon nitride that has a masking action against oxidizing gas (33)
Was formed to a thickness of about 0.1 μm. The film having a masking effect on the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon and silicon nitride. Thereafter, as shown in FIG. 2A, the silicon nitride was partially removed by a second photomask () to use the selective oxidation method, thereby forming FIG. 2A.

After doping the removed region with a P-type impurity for forming a channel cut, a field insulator (3) is
It was formed by being embedded to a thickness of 0.5 to 2 μm.

As shown in FIG. 2B, the silicon nitride film (33) is removed to form a film (2) for forming a gate insulating film on the semiconductor substrate (1) having the convex region (35). did. A semiconductor substrate (1) doped with As or phosphorus by ion implantation to a relatively low concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 from the vertical direction and to a depth of 3000 to 1 μm, for example 5000 °; N at the bottom of the surface and at the top of the convex area (35)
The drain or source (5), (5 ') and the source or drain (4) of the mold are configured as LDD (lightly doped drain).

Channel forming regions (6) and (6 ') are formed on the side surfaces of the convex region, and ion implantation (38) and (38') from the side or oblique direction for controlling the threshold voltage there.
Was doped with boron.

Since not only the substrate but also the insulating film (33) is damaged by these ion implantations, the whole is annealed to combine the semiconductor substrate (1) and the convex region (35) into a single crystal.

The silicon oxide film (2) is removed and another insulating film, for example, another silicon oxide, silicon nitride, tantalum oxide or a composite film thereof is formed to a thickness of 100 to 500 mm to form a gate insulating film (2).
It may be.

Next, as shown in FIG. 2 (C), a window for forming a source or a drain was formed in the gate insulating film (2) using a third photomask (). After sufficiently cleaning the surface of the insulating film, a low pressure gas phase method (LPCVD
A silicon semiconductor film (7) doped with an impurity of one conductivity type, for example, an N-type impurity (phosphorus) to a concentration of 1 to 10 × 10 ²⁰ cm ⁻³ by a gate electrode to a thickness of 0.5 to 2.5 μm. And other leads were formed. This impurity doping is not performed simultaneously with the film formation, but is performed by performing the following anisotropic etching to leave portions (8) and (8 ′) serving as gates, and after performing the conductive film (7). Doping may be performed by a diffusion method.

This conductive film (7) may be a metal or an intermetallic compound, instead of silicon doped with impurities. In addition, P ⁺ or N ⁺ type semiconductors and metals or metal compounds, especially
It may be a multilayer film of Mo, W or a silicide thereof (MoSi ₂ , WSi ₂ ).

When this coating (7) is made of a compound or a mixture of WSi ₂ , MoSi ₂ , silicon, tungsten and molybdenum,
These films may be formed by LPCVD, electron beam evaporation, or reactive sputtering to form 0.3 to 1.5 μm, particularly 0.5 to 0.7 μm.

 Thus, FIG. 2 (C) was obtained.

Next, as shown in FIG. 2 (D), a photoresist (for example,
OMR-83 (manufactured by Tokyo Ohka) (), followed by anisotropic etching. Regarding this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, instead of an isotropic etching method using a conventionally used solution. Specifically 2.45GHz
A reactive gas for etching, for example, nitrogen fluoride (NF ₃ ) or carbon fluoride (CF ₄ ) is chemically activated by microwaves using, and the degree of vacuum is further reduced to 0.1 to 0.001 torr.
A fluorine shower, which was turned into plasma in an atmosphere having a vacuum degree of 0.005 to 0.01 torr, was caused to flow vertically from the upper surface of the substrate, a bias was applied to the substrate, and an attempt was made to eliminate side etching as a low-temperature etching.

As a result, when the flat portion where the photoresist is not formed in the coating (7) is completely removed, the coatings (8) and (8 ') on the side portions which are the corners of the convex region (3).
Could be left as vertical rectangular or substantially triangular gate electrodes (18) and (18 ') around the sides. Using the lower end portion (46) of the gate electrode as a mask, a first impurity region having a high impurity concentration ((15), (1) in FIG.
(Corresponding to 5 ′)) was provided so that the ends (47) thereof were substantially aligned. Furthermore, the electrode contact (11) and its lead (12) of the first impurity region (15) of the MIS FET (19) could be left as an electrode lead of the N ⁺ type in this embodiment. Gate electrodes (18) and (18 ') are convex areas (35)
Does not exist over the upper surface of the film (7), and its width is not determined by photolithography, but can be determined by the thickness of the side surface of the film (7) and the degree of anisotropic etching.

Upper end (48) of this rectangular or triangular gate electrode
Is preferably approximately coincident with the end (4) of the source or drain, that is, located at the same degree or above, that is, approximately coincident. The width between (44) and (45) is extremely important as a margin in manufacturing.

The channel length of the MISFET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). As a margin for the height of the gate electrodes (18) and (18 '), the source and drain of the LDD (4)
Accordingly, the gate electrode is not offset even if the anisotropic etching is performed a little too much. The rectangular or substantially triangular gate electrodes (18) and (18 ′) have a width at the lower end of 0.05 to 1.5 μm, typically 0.2 to 1.0 μm, and further have channel forming regions (6) and (18). 6 '), this area is covered in the lateral direction, and its height is 0.2 to 2.5 µm, typically 0.3 to 0.8 µm.
In particular, this height is a function of the film thickness of the film (7), its etching time by plasma etching, and its intensity, but without using a sophisticated technique such as electron beam exposure, a channel length of 0.05 to 1.0 μm. A very short channel (hereinafter referred to as a microchannel) could be provided.

In FIG. 2 (D), rectangular or substantially triangular gate electrodes (18) and (18 ') have a lower end portion having a width of 0.1 to 1 [mu] m.
However, the layer is extended as a lead on the field insulator as required for design, and the width of the lead is provided as wide as 1 to 10 μm, and other layers provided on the same substrate are provided. It goes without saying that it may be connected to the electrode lead of the MIS FET or may be electrically connected to other capacitors, resistors, and the like.

Next, as shown in FIG. 2 (D), ohmic contact is made at the electrode with a higher concentration than the source or drain (4) and the drain or source (5), (5 ') by ion implantation. Therefore, arsenic, which is an N-type impurity, is implanted at an acceleration voltage of 30 to 150 KeV, and 1 × 10 ¹⁹ to 1 × 10 ¹⁹
At the impurity concentration of about 10 ²¹ cm ^-3 , the first impurity region (15),
(15 ') was formed on the bottom of the substrate, with its end (47) substantially matching the position of the lower end (46) of the rectangular or triangular gate electrodes (18), (18'). In addition, a second impurity region (14) is simultaneously formed on the N-type drain or source (4) above the convex region (35) to facilitate ohmic contact with another electrode.

Then, the first and second impurity regions (15),
(15 ') and (14) prevent the channel length from being varied by the re-diffusion due to the heat treatment after the ion implantation due to the presence of the LDD source or drain (4) and the drain or source (5), (5'). be able to. Particularly, the diffusion of the first impurity regions (15) and (15 ') in the lateral direction is as follows.
The width of the lower ends of the gate electrodes (18) and (18 ') can be provided in a self-aligned manner as a margin.

Further, the electrode leads (11) and (12) of the MIS FET (10) are connected to the first impurity region acting as the drain or source (15), and the other first impurity region (15 ') is connected to the other. May be brought into ohmic contact. Another MIS FET
The contact (1 ') with the first impurity region (15') of (10 ')
The lower electrode (21 ') of the capacitor (10') is connected via 3).

A dielectric (22 ') and an upper electrode (23') were provided thereon to form a 1Tr / Cell.

The dielectric (22 ') was a single layer or a multilayer of tantalum oxide, titanium oxide, barium titanate, and silicon oxide, and was formed by a sputtering method.

 Thus, 1Tr / Cell of the present invention was obtained.

Furthermore, after forming a lead in the direction perpendicular to these leads (19) and (12) with a polyimide-based insulator such as PIQ, the metal on the upper surface is selectively removed by photolithography to form a multilayer wiring. Can be done.

FIG. 2E is a vertical sectional view of the MIS FET (1) shown in FIG. 2D.
0), (10 ') and the capacitor (20') are symbolized and corresponded to the numbers.

Embodiment 2 FIG. 3 shows another embodiment to which the present invention is applied.

FIG. 3A shows two MIS FETs (1
0), (10 ′) and two capacitors are respectively connected in series, and two 1Tr / Cells are provided. That is, the channel-forming region (6),
(6 '), on which a source or drain (4) and a high-concentration second impurity region (14) are provided. A field insulator (3) is provided around the bottom of the semiconductor substrate (1) to form first impurity regions (15) and (15 ').
And drain or source (5), (5 '), gate electrodes (18), (18'), gate insulating film (2),
Two MIS FETs (10) and (10 ') were configured as (2'). The first region of N ⁺ to make this ohmic contact (15),
Connect to (15 ') (13), (13') and connect to capacitor (20),
(20 ') lower electrode (21), (21'), dielectric (22),
(22 '), and further, upper electrodes (23) and (23') are provided thereon, thereby forming capacitors (20) and (20 ').

In FIG. 3, (14) is a bit line, and (18),
(18 ') is a part of a memory system having a structure in which two 1Tr / Cells are paired with word lines. With such a structure, the convex region (35) is divided into two MIS FETs (10) and (10 ').
For common use, and dielectric (22), (22 ')
Has a feature of a stacked memory cell that can use a material having a high dielectric constant different from that of the gate insulating film, for example, tantalum oxide, titanium oxide, silicon nitride, barium titanate, or a multilayer film thereof. In this embodiment, the outer periphery of the gate electrodes (18) and (18 ') is insulated by the oxide interlayer insulator (17), but the thickness is 0.1 to 1.0 [mu] m. Impurity regions (15), (1
5 ') and the lower electrodes (21) of the capacitors (20) and (20'),
(21 ') is connected to selective growth of tungsten (13), (1)
An electrode (contact) according to 3 ′) was formed. For this reason,
The lower electrodes (21) and (21 ') were made of tungsten silicide.

As described above, when the MISFET of the present invention is used, a contact can be obtained while being connected to the first impurity region with a sufficient area. That is, the first impurity region (1
5), (15 ') can be made. The channel length could be made precisely as shown in Example 1 irrespective of the contact formation region and without increasing the size of the MIS FET as viewed from above the substrate.

An interlayer insulator such as polyimide is formed, and a third
May be formed.

The cell area was extremely small and could be formed at a high density. Example 1 was used for manufacturing steps not shown in this example.

Embodiment 3 FIG. 3B is a longitudinal sectional view of this embodiment.

As is apparent from the drawing, a single-crystal semiconductor (35) is provided on the surface of the semiconductor substrate in a convex shape on the surface of the semiconductor substrate, and a gate insulating film (2),
(2 ') is provided, and gate electrodes (18) and (18') are formed in a pair. The drain or source (5), (5 ') and the source or drain (4) of the LDD structure having a low impurity concentration are provided for precisely controlling the channel lengths (6), (6'). Using a part of the gate electrode such as silicon as a mask, the first impurity regions (15), (1)
5 ′) was provided by self-alignment, and a second high-impurity-concentration region (14) was also provided on the convex region by ion implantation at the same time. Thus, the μ-channel MIS FET (10), (1
0 ′) is provided in a paired structure.

Next, the contact openings (9) and (9 ') provided in the first impurity regions (15) and (15') are provided in the same manner as in the first embodiment. The side electrodes (20) and (20 ') are made of, for example,
It was formed to have a thickness of μm. On this upper surface, tantalum oxide films (22) and (22 ') were formed to a thickness of 100 to 500 mm by sputtering. Then, on this surface, the counter electrode (23),
(23) ') was provided by metal or semiconductor, and after this was photoetched, capacitors (20) and (20') were obtained.

Thus, the upper electrodes (23) and (23 ') of the capacitors (20) and (20') and the dielectrics (22) and (22 ') and the lower electrodes (21) and (21') are stacked. It could be made as a memory cell. In addition, the capacitor can be provided on the field insulating film (3) or over the convex region (35) and the gate electrodes (18), (18 '),
The cell area could be densified. By providing a multilayer wiring (24) as a word line on the interlayer insulating film (17) through a contact in the second impurity region (14) and using the gate electrodes (18) and (18 ') as bit lines, The formation of a pair of vertical channel type, source / drain horizontal MISFETs in a self-aligned manner was extremely effective for miniaturization, higher density and improved reliability.

In this embodiment, as in the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24), and the word line is the gate electrode (1).
8), (18 ') and a pair of 1Tr / cell memory systems.

The above-described embodiments 2 and 3 all aim to make a 1Tr / Cell DRAM (dynamic memory). However, in the process of the present invention, similarly, a μ-channel MISFET such as an amplifier or an inverter can be formed on the other part of the same substrate with the same shape. This has been very convenient for making memory systems or logic systems.

In addition, the lower electrode, the upper electrode, and the first region of the capacitor may all have a silicon family formed of the same main component as the substrate to improve reliability. In addition, since these are integrated N-channel MIS FETs, a plurality of convex regions are provided on the same substrate, and a part thereof is used as a P-channel MIS FET to form a complementary (complementary) integrated circuit. Is valid.

In the above three embodiments, the material forming the first region or the material forming the vertical rectangular or substantially triangular gate electrode (18) contains impurities having a P ⁺ or N ⁺ conductivity type. The description is based on a material having the same main component as that of the doped substrate, for example, silicon.

However, they may also be mixtures or compounds of silicon and Mo, W (MoSi ₂ , WSi ₂ ), and may be intrinsic, P ⁺ or
It goes without saying that the N ⁺ type semiconductor may have a multilayer structure, or may have a multilayer structure of a semiconductor such as silicon and Mo, W, platinum or a compound thereof.

In the present invention, the semiconductor substrate is mainly described with single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP or a polycrystalline, amorphous or semi-amorphous semiconductor.

Further, the channel forming region may be a buried channel type instead of the MIS FET using surface diffusion. Further, a method using a majority carrier may be used. These are based on a method of controlling the structure of the channel portion below the gate insulating film.

[Effects] As is clear from the above embodiments, the present invention is not a conventional structure in which a source and a drain having a pair of structures are separated from each other by a gate electrode and wired in the horizontal direction. The capacitor for connecting to it to form 1Tr / Cell is formed in a stacked type. Further, the ease of manufacture and the increase in the capacity of the capacitor could be achieved by reducing the cell area constituting one bit.

The threshold voltage of the channel forming region has a structure in which an impurity such as boron is doped in the upper part of the semiconductor obliquely or laterally, and the frequency response speed depends on its structural characteristics and the channel length of 0.1 to 1 μm. Is 1
It has a great feature that an extremely short channel (μ channel) MIS FET having up to 10 GHz can be implemented without using a technique such as electron beam exposure as an absolute requirement.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing a manufacturing process and a structure of the embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which 1Tr / Cell memories are provided in a pair. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Convex area 3 ... Field insulator 5,5 '... Drain or source 4 ... Source or drain 15,15' ... First impurity region 14 ... Second Impurity region 18, 18 ': Gate electrode 10, 10': Insulated gate field effect transistor (MIS FE
T) 20,20 '…… Capacitor …… Pattern processing by photomask

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 301X

Claims (1)

(57) [Claims] An insulating film on a side of the one-conductivity-type semiconductor substrate; an insulating film on a side surface of the one-sided semiconductor region and a bottom of the semiconductor substrate; A gate electrode having a rectangular or triangular shape at a corner formed; a first low-concentration impurity region at a bottom of the semiconductor substrate; and a second electrode at a bottom of the semiconductor substrate substantially coincident with a lower end of the gate electrode. A second high-concentration impurity region, a second upper-concentration impurity region having an upper end substantially coincident with an upper-end portion of the gate electrode, and a second upper-concentration impurity region above the convex region. A vertical channel-type insulated gate field effect transistor having a second high-concentration impurity region and a pair of the convex region and sharing the second low-concentration impurity region and the second high-concentration impurity region. Provided, A capacitor including a first electrode electrically connected to the first high-concentration impurity region, a tantalum oxide film on the first electrode, and a second electrode on the tantalum oxide film is provided; The vertical channel type insulated gate field effect transistor and the capacitor are electrically connected in series, and the first and second low-concentration impurity regions allow impurity ions to be injected from a direction perpendicular to the semiconductor substrate. By injection, a concentration of 3 × 10 ^{16 to} 5 × 10 ¹⁸ cm ^-3 and 30
Is formed to a depth of 0Nm～1myuemu, the first high concentration impurity region by implanting impurity ions to the gate electrode as a mask, 1 × 10 ¹⁹
It is shallower depth than and the a concentration of ~1 × 10 ²¹ cm ^-3 first low concentration impurity region, the second high concentration impurity ^{region, 1 × 10 19 ~1 × 10} 21 cm
^{-3 and} a depth lower than the second low-concentration impurity region, the first high-concentration impurity region is provided on the semiconductor substrate via the first low-concentration impurity region. And a second high-concentration impurity region is provided on the semiconductor substrate via the second low-concentration impurity region.