JPH0480958A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an element structure for a ULSI of 16M-16G bits by a method wherein a protrudent single crystal semiconductor is provided onto the primary face of a semiconductor substrate, the upper part of the protrudent semiconductor is made to serve as one of LLDs of a MISFET, the side of the protrudent region is made to serve as a vertical channel forming region, the base of the semiconductor substrate is made to serve as a drain or a source of LLD structure, and a rectangular or triangular gate electrode is provided to the corner of the protrudent region. CONSTITUTION:A protrudent region 35 is provided onto a semiconductor substrate, for instance a silicon single crystal semiconductor 100. N-type drains or sources 5 and 5' and a source or a drain 4 are provided to the surface of the semiconductor substrate 1 and the upper part of the protrudent region 35 as an LLD (lightly doped drain) structure. Channel forming regions 6 and 6' are provided to the side faces of the protrudent region 35 and doped with boron ions laterally or obliquely implanted. Coatings 8 and 8' provided to the side corners of the protrudent region 3 are left unremoved as almost triangular gate electrodes 18 and 18'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a memory cell structure for semiconductor integrated circuits, particularly ultra-high density integrated circuits (called ULSI) at the 16M to 16G bit level. Regarding.

The present invention relates to semiconductor devices, particularly MIS type (insulated gate type) field effect semiconductor devices having a microchannel type (hereinafter referred to as μ channel λ (Is FET) because the channel length is 1 μm or less, 0.03 to 1 μm), and The present invention proposes a semiconductor device comprising capacitors connected in series.

``Prior Art'' Conventionally, the structure of a MisFET or a capacitor connected in series thereto is as shown in FIG. A drain or source (21) that is effectively a drain or source and constitutes a lower electrode of the capacitor is provided opposite to the gate insulator (2), the gate electrode (18), and the source or drain (14); A capacitor insulator (22) and a counter electrode (23) were provided.

Conventionally, MIS FETs have a channel formation region in the lateral direction parallel to the upper surface of the semiconductor substrate, and a pair of source, drain (14) and drain or source (21) are always placed symmetrically under both ends of the gate electrode on the semiconductor substrate. They were formed on the same plane. Furthermore, ITr/C which is the object of the present invention
In the case of e1l (one MIS FET and one capacitor are connected in series to form a memory that constitutes one bit), this gate electrode (18) is placed not only on the gate insulator (2) but also on the capacitor. It was provided over the upper surface of the counter electrode (23). This is provided with self-alignment, with one end of the source or drain (14) placed below one end of the gate electrode (18), and one end of the drain or source (21) placed above the other end of the gate electrode. . The other end (18°) of the gate electrode is coated with a polycrystalline silicon film (23), (18) which is made larger than the channel region (6) to compensate for variations in mask alignment accuracy.
). However, even in such a case, it is impossible to reduce the channel length to 1 μm or less due to limitations in the photoetching process, and in particular, due to the unevenness at the step portion (18), it is impossible to shorten the channel length due to the pattern step. This was not possible due to cuts etc. The present invention actively utilizes this difference in MIS.
The present invention is characterized in that a gate electrode of the FET is provided, and the gate electrode is formed without extending above the opposing electrode of the capacitor forming a convex shape.

"Objective of the present invention" The present invention provides a channel forming region under the gate electrode in which a current flows in the vertical direction, and the channel length is 0.03.
In addition to extremely small size of ~1μm, one MIS
ITr with a FET and a capacitor connected in series/
The purpose of this invention is to provide an element structure for ULSI that can be made up to 16M to 16G bits by reducing the size of Ce1l to about 1 μm to 10 μm.

``Structure of the Invention'' The present invention has an asymmetric structure in which the channel forming region is formed in the vertical direction, that is, in a vertical channel type, and the source and drain are formed in the horizontal direction to facilitate connection with one electrode of the capacitor. The purpose of this company is to provide MIS FETs. That is, a convex single-crystal semiconductor region is provided on the whole surface of the semiconductor substrate, and the upper part thereof is configured as λ (one source or drain of the IS FET is configured as an LDD (a drain with a relatively low impurity concentration, that is, a light doped drain). Seshime,
Furthermore, the sides of this convex region are made into vertical channel forming regions, and the bottom of the semiconductor substrate is made into a drain or source having an LDD configuration, and these sources have an impurity concentration of 3×10 16 to 5×
The concentration is as low as 10''' cm-3 to improve the drain breakdown voltage, that is, it is an LDD, and a rectangular or triangular gate electrode is provided at the corner of the convex region.

The upper lateral part of the gate electrode roughly coincides with the source or drain, coincides with the end of the source or drain, or is provided slightly larger on the source or drain side, and is located below the second impurity region thereon. This prevents the gate electrode from having an offset structure and provides a margin for manufacturing.

In addition, the source or drain has a second impurity region, and the drain or source has a side surface to facilitate ohmic contact between the first impurity region with a high impurity concentration and one electrode of the capacitor. It is set up. The present invention is characterized in that a stacked type (stacked type capacitor) is provided by connecting capacitors in which a conductor, an insulator, and a conductor are electrically stacked in series via the first region.

Examples of the present invention will be described below according to the drawings.

``Example 1'' In this example, the ITr/Cell structure of the present invention and its manufacturing process are shown in FIG. They are provided as a pair.

A semiconductor substrate, for example a silicon single crystal semiconductor (100).

P-type lO~500Ωcm was selected. A convex region (35
) was formed. For its manufacture, a silicon single crystal substrate may be anisotropically etched using a photoresist (32) as a mask. This corner part is 90° to the top surface of the board.
It is important to have an extremely sharp vertical surface. The height of this convex portion was set to 0.5 to 4 μm, for example, 1.5 μm.

Silicon nitride that has a masking effect against oxidizing gases (33)
was formed to a thickness of about 0.1 μm. The film having a masking effect against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride. Thereafter, as shown in FIG. 2(A), in order to use a selective oxidation method, a portion of the silicon nitride was removed using a second photomask (■) to form the structure shown in FIG. 2(A).

Then, P for forming a channel cut in this removed area.
After doping type impurities, the field insulator (3) is
．． It was embedded and formed to a thickness of 5 to 2 μm.

As shown in FIG. 2(B), this silicon nitride film (33) is removed and a film (2) for forming a gate insulating film is formed on the semiconductor substrate (1) having the convex region (35). did.

It has a relatively low concentration of 3X10" to 5X10" cm-3 in the vertical direction, and has a density of 3000 to 1. Dope As or phosphorus to a depth of 5,000 um, for example, by ion implantation, and form an N-type drain or source (5) at the bottom of the surface of the semiconductor substrate (1) and at the top of the convex region (35). (5') and source or drain (4')
) is configured as an LDD (Light Doped Drain).

A channel forming region (6), (6°) is formed on the side surface of the convex region, and ions are implanted laterally or diagonally to control the threshold voltage there (38).

(38') was doped with boron.

By implanting these ions, not only the substrate but also the insulating film (
33) was also damaged, so they were all annealed to form a single crystal of the semiconductor substrate (1) and the convex region (35).

This silicon oxide film (2) is removed and another insulating film, such as another silicon oxide, silicon nitride, tantalum oxide, or a composite film of these, is formed to a thickness of 100 to 500 nm to form a gate insulating film (
2) may also be used.

Next, as shown in FIG. 2(C), this gate insulating film (2)
A window for use as a source or drain was formed using a third photomask (■). After sufficiently cleaning the surface of the insulating film, a low pressure vapor phase method (LPCVD method) is applied on the substrate.
impurities of one conductivity type, e.g. N-type impurities (phosphorus)
A silicon semiconductor film (7) doped with a concentration of 1 to 10.times.10.sup.20 cm.sup.-3 was formed to a thickness of 0.5 to 2.5 .mu.m to constitute a gate electrode and other boards. These impurity dots are not removed at the same time as the film is formed, but are etched in the next anisotropic etching to form gates (8) and (8).
) may be doped by a diffusion method after the step of leaving the conductive film (7).

This conductive film (7) is not silicon doped with impurities, but may also be a metal or an intermetallic compound. Furthermore, P+ or N+ type semiconductors and metals or metal compounds, especially Mo, W or their silicides (MoSi2゜WSi
2) may be a multilayer film.

This coating (7) was applied to WSi2. When using a compound or mixture of Mos+ 2, etc., silicon, tungsten, and molybdenum, the coating is formed by LPGVD, electron beam evaporation, or reactive sputtering to a thickness of 0.3 to 1.5 μm, particularly 0.5 to 0.5 μm. It is sufficient to form the layer with a thickness of 7 μm.

Thus, Figure 2(C) was obtained.

Next, as shown in FIG. 2(D), apply a photoresist (for example, O
MR-83 (manufactured by Tokyo Ohka) (■) was selectively coated, and then anisotropic etching was performed. For this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, rather than the conventional solution-based isotropic etching method. Specifically 2.45
A reactive gas for etching, such as nitrogen fluoride (NF3), carbon fluoride (CF
, ) is chemically activated, and the degree of vacuum is further reduced to 0.1~
0.001torr especially 0.005~0.01torr
In an atmosphere with a vacuum level of 100%, a fluorine shower turned into plasma was flowed vertically from the top surface of the substrate, and a bias was applied to the substrate in an effort to completely eliminate side etching by performing low-temperature etching.

As a result, when the planar part of the film (7) on which no photoresist is formed is completely removed, the convex region (3
) coating (8) on the side surface, which is the corner part.

(8') could be left as vertical rectangular or approximately triangular gate electrodes (18), (18') around the sides. Using the lower end (46) of this gate electrode as a mask, the first impurity region with a high impurity concentration (see FIG.
D) (corresponding to (15), (15”)) at its end (4
7) were provided to roughly match. Furthermore, MIS FET (
The electrode contact (11) and its lead (12) of the first impurity region (15) of 19) are N+ in this embodiment.
It was possible to leave it as an electrode lead in the mold. Gate electrode (18).

(18") does not exist over the upper surface of the convex region (35), and its width is not determined by photolithography, but is determined by the thickness of the side surface of the coating (7) and the degree of anisotropic etching. It can be determined by

The upper end (48) of this rectangular or triangular gate electrode
It is preferable that the edge (4) of the source or drain be located approximately at the same level or above the end (4) of the source or drain. The width between (44) and (45) is extremely important as a margin in manufacturing.

The channel length of the MIS FET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). This gate electrode (18).

(18°) as a margin for the height of the LDD source,
It has a drain (4), which has the feature that even if the anisotropic etching is performed a little too much, the gate electrode will not be in an offset state. This rectangular or almost triangular gate electrode (18), (18'') has a width of 0.05 to 1.5 μm at its lower end, typically 0.2 to 1.5 μm.
0 μm and further a channel forming region (6).

(6°) in the lateral direction and reduce its height to 0.
The thickness is 2 to 2.5 μm, typically 0.3 to 0.8 μm. In particular, this height is a function of the film thickness of the coating (7) and the etching time and intensity of plasma etching, but it can be etched as a channel length of 0.05 to 0.05 without using advanced techniques such as electron beam exposure. It was possible to provide a very short channel (hereinafter referred to as a microchannel) of 1.0 μm.

In FIG. 2(D), the rectangular or almost triangular gate electrode (18) (18°) has a width of 0.1 at the lower end.
Although the layer is as thin as ~1 μm, the layer can be extended as a lead on the field insulator according to design needs, and the lead width can be made as wide as 1 to 10 μm, and it can be placed on the same substrate. It goes without saying that it may be electrically connected to the electrode leads of other MIS FETs, or to other capacitors, resistors, etc.

Next, as shown in FIG. 2(D), the source or drain (4) and the drain or source (5), (5') are made at a higher concentration than the electrodes by ion implantation, and ohm contact is made with the electrode. Therefore, arsenic, which is an N-type impurity, is implanted at an accelerating voltage of 30 to 150 KeV, and
The first impurity region (15), (15°) is formed at its end (4
7) with a rectangular or triangular gate electrode (18), (
18') in approximately the same position as the lower end (46) of the
It was formed on the bottom of the substrate. In addition, a second impurity region (14) was simultaneously formed above the N-type drain or source (4) above the convex region (35) to facilitate ohmic contact with other electrodes.

Then, these first and second impurity regions (15).

(15°) and (14) prevent variations in channel length due to re-diffusion due to heat treatment after ion implantation due to the presence of the source or drain (4) and the drain or source (5) and (5') for LDD. Something will happen. In particular, the lateral diffusion of the first impurity regions (15), (15°) is caused by the gate electrodes (18), (18').
The width of the lower end of can be provided as a self-alignment margin.

In addition, the electrode lead (11) of the MIS FET (10),
(12) and a first impurity region acting as a drain or source (15) can be connected, and another first impurity region (15') and another electrode lead can be brought into ohmic contact.

Further, the first impurity region (15°) of another MIS FET (10') is connected to the lower electrode (21') of the capacitor (10°) via a contact (13).

A dielectric (22°) and an upper electrode (23°) were provided on this to form ITr/Ce11.

The dielectric (22°) was a single layer or multilayer film of tantalum oxide, titanium oxide, barium titanate, and silicon oxide, and was formed by sputtering.

In this way, ITr/Cel of the present invention was obtained.

Furthermore, after forming interlayer insulators for leads in the direction perpendicular to these leads (19) and (12) using polyimide insulators such as PIQ, the metal on the top surface is selectively removed by photolithography to form multilayer wiring. can be done.

Figure 2 (E) is a vertical cross-sectional view of MrS FE in Figure 2 (D).
T(10), (10°) and capacitor (20°)
are written in symbols with corresponding numbers.

"Example 2" FIG. 3 shows another embodiment to which the present invention is applied.

FIG. 3(A) shows two MIS FETs using Example 1.
(10), (10") and two capacitors are connected in series, and two ITr/Cell pairs are provided. That is, the convex region (35) has a channel forming region. (6), (6'), and has a source or drain (4) on top thereof, and a highly concentrated second impurity region (14).A field is provided at the bottom peripheral part of the semiconductor substrate (1). An insulator (3) is provided, and a first impurity region (15) (15°) and a drain or source (5) (5') and a gate electrode (18) are formed outside of the first impurity region (15) (15°).
, (18'), gate insulating film (2), (2')
Two MIS FETs (10), (10°) were configured as follows. The first region of N+ (
15), (15') 2-connection (13), (13'
) t, lower electrode (21) of (20°), dielectric (22), (2
2°), and further above that the upper electrode (23), (23'
), thereby providing capacitors (20), (20'
).

In FIG. 3, (14) is a bit line, (18)
.

This is part of a memory system in which a word line (18') is used as a pair of ITr/Ce11. With such a structure, the convex region (35) is divided into two MIS F
The dielectric material (22), (22'') can be made of a material with a high dielectric constant different from the gate insulating film, such as tantalum oxide, titanium oxide, or silicon nitride. , barium titanate, a multilayer film of these, etc., have the characteristics of a stacked memory cell.In this embodiment, the gate electrode (1
8), the outer periphery of (18°) is insulated by the oxide interlayer insulator (17), the thickness of which is 0.1~
1.0 μm, the first impurity region (15), (1
5°) and the lower electrodes (21), (21°) of the capacitors (20), (20') were connected by selectively growing tungsten (13), (13'') to form electrodes (contacts). For this reason, the lower electrode (21), (21
) was tungsten silicide.

When using the MIS FET of the present invention as described above, the first
A contact can be obtained by connecting to the impurity region with a sufficient area margin. In other words, the first impurity region (
15), just make (15°). The channel length could be made precisely as shown in Example 1, regardless of this contact formation region and without increasing the size of the MisFET as seen from the substrate.

An interlayer insulator such as polyimide may be formed, and the third conductor wiring (9) may be formed on the upper surface thereof.

In addition, the area of the cells could be extremely small and the cells could be formed with high density. For manufacturing steps not shown in this example, Example 1 was used.

Embodiment 3j This embodiment is shown in longitudinal section in FIG. 3(B).

As is clear from the drawing, a single crystal semiconductor (35) is provided on the surface of the semiconductor substrate in a convex shape, and a gate insulating film (2) is formed around the side thereof and at the corner of the bottom of the substrate.
(2') and a gate electrode (18).

(18°) are formed as a pair. Drain or source (5) of LDD structure with low impurity concentration, (5°
).

The source or drain (4) is connected to the channel length (6), (
Using a part of this gate electrode made of silicon as a mask, a highly concentrated first impurity region (15) (15°) is provided as a self-line, and a convex At the same time, a second high impurity concentration region (14) was provided above the shaped region by ion implantation.

Thus μ channel eight (Is FET (10), (1
0') were provided in a structure forming two pairs.

Next, since the contact openings (9), (9°) provided in this first impurity region (15), (15°) are provided in the same manner as in Example 1, this allows The side electrodes (20) (20°) were provided, for example, by forming doped silicon to a thickness of 0.1 to 1 μm. On this upper surface, a tantalum oxide film (22) is formed by sputtering.
(22°) was formed to a thickness of 100 to 500 people. Thereafter, counter electrodes (23), (23)') were provided on this surface using metal or semiconductor, and after photoetching, capacitors (20), (20°) were formed.

Thus, the upper electrode (23), (23°) of the capacitor (20), (20') and the dielectric (22),
(22') and lower electrode (21), (21°)
could be made as a stacked memory cell. In addition, this capacitor is connected to the field insulating film (3) or the convex region (35) and the gate electrode (18), (1
8°), and it was possible to increase the density of the cell area.

By providing a multilayer wiring (24) as a word line on the interlayer insulating film (17) via a contact to the second impurity region (14), and using the gate electrodes (18), (18'') as a bit line, Forming pairs of vertical channel type MIS FETs and horizontal source/drain type MIS FETs in a self-aligned manner was extremely effective in reducing size, increasing density, and improving reliability.

In this embodiment as well, similar to the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24) and the word line is the gate electrode (18).
), (18'') could be configured as part of the ITr/cell memory system.

The above embodiments 2 and 3 are all ITr/Ce1l DRA.
The purpose is to create M (dynamic memory).

However, in all of the processes of the present invention, μ-channel MIS FETs such as amplifiers or inverters can be formed in other parts of the same substrate with the same shape. This makes it extremely convenient for creating memory systems or logic systems.

Further, the lower electrode, the upper electrode, and the first region of the capacitor may all be formed of a silicon family made of the same main component as the substrate to improve reliability. Also, these are N
Since it is an integrated channel Mis FET,
It has multiple convex regions on the same substrate, some of which are P
It is effective to use a complementary integrated circuit as the channel MIS FET.

In the above three embodiments, the material constituting the first region and the vertical rectangular or approximately triangular gate electrode (1
The material constituting 8) is mainly a material having the same main component as the substrate doped with an impurity having a conductivity type of P'' or N''W, such as silicon.

However, they may be mixtures or compounds of silicon, Mo, and W (MoSi2, WSi2), and may also be made of a multilayer structure of intrinsic, P+ type, or N'' type semiconductors, or may be made of semiconductors such as silicon and Mo, It goes without saying that it may have a multilayer structure with W, platinum, or a compound thereof.

In the present invention, the semiconductor substrate is mainly made of single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

In addition, the channel formation region is a MISFET that uses surface diffusion.
Instead, it may be a recessed channel type.

Alternatively, a method using majority carriers may be used.

These are based on the method of controlling the structure of the channel section under the gate insulation crotch.

[Effect J] As is clear from the above embodiments, the present invention does not have a conventional structure in which the source and drain are separated from each other by a gate electrode and are wired in the horizontal direction, but instead has a structure in which the source or drain is connected to the outside. A capacitor connected thereto to form an ITr/Cell is formed in a stacked type. Furthermore, ease of manufacture and increase in capacitance of the capacitor can be achieved by reducing the cell area constituting one bit.

The threshold voltage of the channel forming region has a structure in which impurities such as boron are doped into the upper part of the semiconductor diagonally or laterally, and the frequency is determined by its structural characteristics and the channel length of 0.1 to 1 μm. Response speed is 1
- Very short channel (μ channel) MI with 10 GHz
A major feature is that the S FET can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of the drawing]

FIG. 1 shows a conventionally known MIS FET. FIG. 2 is a longitudinal sectional view showing the manufacturing process and structure of an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of another embodiment of the present invention in which a pair of ITr/Cel memories are provided. 1... Convex region...Field insulator...Drain or source...Source or drain...First impurity region...Second impurity region...Gate electrode...Insulated gate field effect transistor (MIS FET)・Capacitor...Patterning process using photomask Figure 2

Claims (1)

[Claims] 1. A convex region on a semiconductor substrate of one conductivity type, an insulating film that covers the side surfaces and bottom surface of the region, and an insulating film that does not extend above the region and connects the region and the bottom surface of the substrate. a rectangular or triangular gate electrode on an insulating film at a corner portion, a low concentration drain or source provided at the bottom of the semiconductor substrate, and a low concentration drain or source provided at the bottom of the semiconductor substrate; A first impurity region with a higher concentration than the drain or source provided at the bottom of the interior and an end of the lower concentration source or drain provided at the top of the convex first region are connected to the gate electrode. a vertical channel insulated gate field effect transistor having a second impurity region provided approximately in line with the upper end portion and provided above the source or drain; and a second impurity region connected to the first impurity region. A capacitor including a first electrode, a dielectric on the electrode, and a second electrode on the dielectric is provided, and the vertical channel insulated gate field effect transistor and the capacitor are electrically connected in series. A semiconductor device characterized by: 2. A corner consisting of a convex region on a semiconductor substrate of one conductivity type, an insulating film covering the side and bottom surfaces of the region, and the region and the bottom surface of the semiconductor substrate without extending above the region. A rectangular or triangular gate electrode is formed on the insulating film of the
a lightly doped drain or source provided at the bottom of the semiconductor substrate; and a first impurity region more highly doped than the drain or source provided at the bottom of the substrate and approximately coincident with the lower end of the gate electrode. , a low concentration source or drain provided above the convex first region is provided to approximately coincide with the upper end of the gate electrode, and a second impurity region provided above the source or drain; Vertical channel insulated gate field effect transistors having a pair of vertical channel insulated gate field effect transistors are provided in the convex region in pairs, and are connected to each of the first impurity regions of the pair, and are connected to each of the first pair of the capacitors. an electrode, a dielectric on the first electrode, and a second electrode on the dielectric, and a bit line is configured in the second region provided in the convex region, and A semiconductor device characterized in that each gate electrode of the pair of vertical channel type insulated gate field effect transistors is provided to constitute a word line.