JPH0480968A - Insulated-gate field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To provide the gate electrode of a MISFFT taking advantage of a step, where the gate electrode is formed so as not to extend above the counter electrode of a capacitor formed protrudent by a method wherein a protrudent single crystal semiconductor region is provided onto the primary surface of a semiconductor substrate. CONSTITUTION:Vertical rectangular or triangular gate electrodes 18 and 18' are provided adjoining to a protrudent region to be enhanced in mechanical strength, and a source 4 and drains 5 and 5' adjoining to channel forming regions 6 and 6' are formed into an LDD structure. The gate electrodes 18 and 18' are electrically isolated through an insulating film 17 and can be dynamically reinforced by leaning them against the protrudent region. The source or the drain 4 and the drains or the sources 5 and 5' are separated from each other by the channel forming regions 6 and 6', and the gate electrodes 18 and 18' are formed on the side faces of gate insulating films 2 located on the side faces of the channel forming regions 6 and 6', whereby a vertical micro channel type MISFET precisely controlled in channel length and small in occupying area on a substrate can be formed.

Description

Detailed Description of the Invention "Field of Industrial Application" The present invention is directed to semiconductor integrated circuits, particularly insulated gate field effect semiconductor devices for ultra-high density integrated circuits (called ULSI) at the 16M to 16G bit level. Regarding providing.

The present invention relates to a semiconductor device, particularly a MIS type (insulated gate type) field effect semiconductor device having a microchannel type (hereinafter referred to as a μ channel MIS FET because the channel length is 1 μm or less, 0.03 to 1 μm), and a capacitor therefor. The purpose of the present invention is to propose a semiconductor device that connects the two.

The present invention provides a vertical channel type MIS in which a convex region is provided on the surface of a semiconductor substrate by anisotropic etching, and a channel is formed on the side surface of this single crystal convex region.
``Prior art'' related to FET Conventionally, the structure of MIS PET or a capacitor connected in series with it is as shown in FIG. A drain or source (21) that is effectively a drain or source and constitutes a lower electrode of the capacitor is provided opposite to the gate insulator (2), the gate electrode (18), and the source or drain (14). Furthermore, a capacitor insulator (22) and a counter electrode (23) were provided.

Conventionally, MIS FETs have a channel formation region in the lateral direction parallel to the upper surface of the semiconductor substrate, and a pair of source, drain (14) and drain or source (21) are always placed symmetrically under both ends of the gate electrode on the semiconductor substrate. They were formed on the same plane. Furthermore, ITr/Ce1l (one M
In the case of a memory that configures one bit by connecting an IS FET and one capacitor in series, this gate electrode (
18) was provided not only on the gate insulator (2) but also over the upper surface of the counter electrode (23) of the capacitor.

This places one end of the source or train (14) on one end of the gate electrode (18) and one end of the drain or source (21).
One end is provided with self-alignment with the other end apparently above the gate electrode. and the other end of the gate electrode (18"
') is a polycrystalline silicon film made larger than the channel region (6) to compensate for variations in mask alignment accuracy (a process in which a polycrystalline silicon film is used for (23) and (18)). However, even in such a case, it is impossible to reduce the channel length to 1μ or less due to limitations in the photoetching process, and in particular, it is impossible to shorten the channel length due to the unevenness of the step part in (step 8). This was not possible due to breakage, etc. The present invention is characterized in that the gate electrode of the MIS FET is provided by actively utilizing this level difference, and the gate electrode is formed without extending above the opposing electrode of the capacitor forming the convex shape. do.

``Object of the present invention'' In the present invention, a current flows in the channel formation region under the gate electrode in the vertical direction, and the channel length is 0.03.
In addition to extremely small size of ~1μm, one MIS
By reducing the size of the FET to about 1μm to 10μm, it is possible to make up to 16M to 16G bits.
The purpose of this invention is to provide an element structure for LSI. Furthermore, the MIS FET is combined to provide an inverter structure or a memory cell structure connected to other elements such as capacitors.

``Structure of the Invention J'' The present invention makes the channel forming region vertical, that is, a vertical channel type, and the source and drain are formed in the horizontal direction in order to facilitate electrode formation in the subsequent process. In other words, a convex single-crystalline semiconductor region is provided on one main surface of a semiconductor substrate, and the upper part of the single-crystal semiconductor region is used to connect one source or drain of the MI 5FET to an LDD (drain with relatively low impurity concentration). Furthermore, the sides of this convex region are formed as vertical channel formation regions, and the bottom of the semiconductor substrate is formed as a train or source of an LDD configuration, and these sources or drains and the trains or sources are formed with impurity Concentration 3XIO" ~ 5X 10
The concentration is as low as "cm-3" to improve the drain breakdown voltage, that is, it is an LDD, and a rectangular or triangular gate electrode is provided at the corner of the convex region.

The upper lateral part of the gate electrode roughly coincides with the source or drain, coincides with the end of the source or drain, or is provided slightly larger on the source or drain side, and is located below the second impurity region thereon. This prevents the gate electrode from having an offset structure and provides a margin for manufacturing. ' Also, the source or train and the drain or source are used to facilitate ohmic contact between the second impurity region and the first impurity region with high impurity concentration with external electrodes.
It is provided with a horizontal surface.

And electrically conductor, insulator,
A stacked type (
It is characterized by the provision of a stacked capacitor.

Therefore, the semiconductor device of the present invention achieves high density for configuring a ULSI by proactively providing the area in the height direction instead of reducing the area occupied by the conventional horizontal MIS FET substrate by scaling. The purpose is to

Examples of the present invention will be described below according to the drawings.

``Example 1'' In this example, the manufacturing process is shown in FIG. 2, and two vertical channel type N-channel MIS FETs are provided as a pair using a convex region of a semiconductor substrate. .

A semiconductor substrate, for example a silicon single crystal semiconductor (100).

A P type of 10 to 500 Ωcm was selected. A convex region (35
) was formed. For its manufacture, a silicon single crystal substrate may be anisotropically etched using a photoresist (32) as a mask. This corner part is 90° to the top surface of the board.
It is important to have an extremely sharp vertical surface. The height of this convex portion was set to 0.5 to 4 μm, for example, 1.5 μm.

Silicon nitride that has a masking effect against oxidizing gases (33)
was formed to a thickness of about 0.1 μm. The film having a masking effect against the oxidizing gas may be a multilayer film of silicon oxide, polycrystalline silicon, and silicon nitride. Thereafter, as shown in FIG. 2(A), in order to use a selective oxidation method, a portion of the silicon nitride was removed using a second photomask (■) to form the structure shown in FIG. 2(A).

Then, P for forming a channel cut in this removed area.
After doping type impurities, the field insulator (3) is
．． It was embedded and formed to a thickness of 5 to 2 μm.

As shown in FIG. 2(B), this silicon nitride film (33) is removed and a film (2) for forming a gate insulating film is formed on the semiconductor substrate (1) having the convex region (35). did.

The bottom of the surface of the semiconductor substrate (1) is doped with As or phosphorus at a relatively low concentration of 3×1016 to 5×1018 cm from the vertical direction and to a depth of 3000λ to 1 μm, for example, 5000 cm, by ion implantation. and an N-type drain or source (
5), (5') and the source or drain (4) are configured as an LDD (lightly doped drain).

A channel forming region (6), (6°) is formed on the side surface of the convex region, and ions are implanted laterally or diagonally to control the threshold voltage there (38).

(38') was doped with boron.

By implanting these ions, not only the substrate but also the insulating film (
33) was also damaged, so they were all annealed to form a single crystal of the semiconductor substrate (1) and the convex region (35).

This silicon oxide film (2) is removed and another insulating film, such as another silicon oxide, silicon nitride, tantalum oxide, or a composite film of these, is formed to a thickness of 100 to 500 nm to form a gate insulating film (
2) may also be used.

Next, as shown in FIG. 2(C), this gate insulating film (2)
A window for use as a source or drain was formed using a third photomask (■). After the surface of the insulating film was sufficiently cleaned, the substrate was doped with impurities of one conductivity type, such as N-type impurities (phosphorous), to a concentration of 10×10”cF3 by low pressure vapor phase PCVD. A silicon semiconductor film (7) was formed to a thickness of 0.5 to 2.5 μm to form a gate electrode and other lids.This impurity dot was not removed at the same time as the film was formed, but during the subsequent anisotropic etching. After the step of leaving the portions (8), (8'') that will become gates, and the coating (7), doping may be performed by a diffusion method.

This coating (7) is not impurity or doped silicon;
It may be a metal or an intermetallic compound.

Furthermore, P' or N' type semiconductors and metals or metal compounds, especially Mo, W or their silicides Q (oSi29wsi
2) may be a multilayer film.

When this coating (7) is made of a compound or mixture of WS I 21λ (oSi2, etc., silicon, tungsten, molybdenum, etc.), the coating is formed by LPCvD, electron beam evaporation, or reactive sputtering to a concentration of 0.3 to 1 A thickness of 0.5 μm, especially 0.5 to 0.7 μm is good.

Thus, Figure 2(C) was obtained.

Next, as shown in FIG. 2(D), apply a photoresist (for example, O
MR-83 (manufactured by Tokyo Ohka) (■) was selectively coated, and then anisotropic etching was performed. For this etching, it is important to use an anisotropic etching method with very little or no side etching and taper etching, rather than the conventional solution-based isotropic etching method. Specifically 2.45
Reactive gases for etching, such as nitrogen fluoride (NF3), carbon fluoride (CF
4) is chemically activated, and the degree of vacuum is further reduced to 0.1~
A fluorine shower made into plasma in a vacuum atmosphere of 0.00 torr, especially 0.005 to 0.01 torr, is flowed vertically from the top surface of the substrate, and a bias is applied to the substrate, resulting in low-temperature etching that eliminates side etching. I tried.

As a result, when the flat part of the coating (7) where no photoresist is formed is completely removed, the convex area (3) is completely removed.
) coating (8) on the side surface, which is the corner part.

(8') is left as vertical rectangular or approximately triangular gate electrodes (18), (18') around the sides. Furthermore, the first impurity region (corresponding to (15) in FIG. 2(D)) for the train or source (contact) (11) and its lead (12) are N in this embodiment.
It was possible to leave it as an electrode lead in the ゛ type.

The gate electrodes (18), (18') have convex regions (3
The width of the film (5), which extends over the upper surface of the film (7), is not determined by photolithography, but can be determined by the thickness of the side surface of the film (7) and the degree of anisotropic etching.

The upper end (48) of this rectangular or triangular gate electrode
is approximately aligned with the end (44) of the source or train, that is, located at the same level or above, and is located away from the end (45) of the second impurity region (14) to be formed in a subsequent process. That's preferable. The width between (44) and (45) is extremely important as a margin in manufacturing.

The channel length of the Mis FET can be determined by the difference in height between the end (44) of the source or drain (4) and the convex region (35). This gate electrode (18).

(18') has the source and drain (4) of the LDD as a margin for the height, and has the feature that even if the anisotropic etching is performed a little too much, the gate electrode will not become offset. This rectangular or almost triangular gate electrode (18), (18°) has a width of 0.000 mm at its lower end.
05 to 1.5 μm, typically 0.2 to 1.0 μm, and further covering this region in the lateral direction of the channel forming region (6), (6°) to increase its height by 0.2 μm. ~2.5μm
Typically, the thickness is 0.3 to 0.8 μm. In particular, this height is a function of the film thickness of the coating (7) and its etching time and intensity by plasma etching, or the channel length is 0.05 to 1. It was possible to provide a very short channel (hereinafter referred to as a microchannel) of .0 μm.

In FIG. 2(D), the rectangular or approximately triangular gate electrodes (18), (18') have a width of 0.00000000000000000000000000000000000000000000,000.
The layer can be as thin as 1 to 1 μm, and can be extended as a lead over the field insulator as required by the design.
The width of the lead may be as wide as 1 to 10 μm, and it may be connected to the electrode lead of another λ(Is FET) provided on the same substrate, or may be electrically connected to other capacitors, resistors, etc. Needless to say.

Next, as shown in FIG. 2(D), the source or drain (4) and the drain or source (5) are formed at a higher concentration than the (5°) by ion implantation, and ohmic contact is made with the electrodes. Therefore, arsenic, which is an N-type impurity, is implanted at an accelerating voltage of 30 to 150 KeV, and l
The end portions (47) of the first impurity regions (15), (15') are formed into a rectangular or triangular gate electrode (
18), (18°) was formed on the bottom of the substrate approximately in alignment with the position of the lower end (46). In addition, a convex region (
35) A second impurity region (14) was also formed on the top of the upper N-type train or source (4) to facilitate ohmic contact with other electrodes.

Then, these first and second impurity regions (15).

(15°) and (14) prevent variations in channel length due to re-diffusion due to heat treatment after ion implantation due to the presence of the source or train (4) and drain or source (5) for LDD (5°). I can do it. In particular, the lateral diffusion of the first impurity regions (15), (15°) should be made in a self-aligned manner as a margin, which is the width of the lower end of the gate electrodes (18), (18''). I can do it.

Further, the electrode leads (11) and (12) are connected to a first impurity region acting as a drain or source (15), and another first impurity region (15') and another electrode lead (19) are connected. ) to make ohmic contact with the electrode (1
3) Below, there are higher concentration impurity regions (15), (1
5'), and these have a drain or source (14
) contacts are formed.

Thus, it is a vertical channel type, and the source and drain are LD.
While having a D structure, the upper part of the convex region and the lateral surface of the bottom surface of the substrate were used for contact with the outside, and a vertical channel type MIS FET of so-called vertical and horizontal type was able to be obtained. Therefore, the electrode (contact) for the source and train
The channel length is 0.1 to 1.
It is as small as μm, and its length can be precisely controlled by using an LDD structure.

As is clear from the above embodiments, the present invention provides a vertical rectangular or substantially triangular gate electrode (18).

(18°) is adjacent to the convex region to increase mechanical strength, while the source (4), drain (5), (5°) adjacent to the channel forming region (6), (6') is LDD. We were able to obtain a vertical channel type MIS FET.

Furthermore, since the gate electrodes (18) and (18') are thick, they are geometrically weak.
In addition, since the unevenness of the inherent drawback of ULS I tends to become severe, it is electrically isolated by an insulating film (17), and mechanically reinforced by leaning on the convex region. It is characterized by being able to do things.

As is clear in FIG. 2(D), source or drain (4), drain or source (5), (5'
) are separated at the channel forming region (6), (6°), and gate electrodes (18), (18°) are formed on the side surfaces of the gate insulating film (2) on the side surfaces of this channel forming region. It is possible to fabricate a vertical and horizontal microchannel (μ channel) type MIS FET that has a channel length that is controlled precisely and that reduces the total area of the entire substrate of the transistor.

Furthermore, after forming interlayer insulators for leads in the direction perpendicular to these leads (19) and (12) using polyimide insulators such as PIQ, the metal on the top surface is selectively removed by photolithography to form multilayer wiring. can be done.

Figure 2 (E) is a vertical cross-sectional view of Mis PE in Figure 2 (D).
T(10) and (10') correspond to their numbers and are symbolized λ (OSFET).

In the embodiment of the present invention, the conductivity type is that the substrate is P- type, the channel region (12) is P type, and the source or drain (4).

The drain or source (5), (5°) is an N-type low concentration region, and (14), (15), (15”°
) was set as an N'' type high concentration region. Also, the gate electrode (1
8), (18°°) is the so-called two μλ (IS F
It is ET.

In addition, a P-type, first MIS FET is provided in the channel formation region.
(10), second λ(Is FET (10°)
It is also possible to use an inverter structure in which the output is taken out from (14) using as a driver. At that time, the load (10) is a depletion type MIS FET, and the driver (10) is a depletion type MIS FET.
°) may be an enhancement type.

In Figure 1, two MIS FETs are formed on a substrate, but other Mis FETs are provided on the same substrate in other parts separated by field insulators to form multiple MIS FETs.
The present invention can be further promoted by making the FET into a so-called LSI or VLSI.

“Example 2j FIG. 3(A) shows another embodiment to which the present invention is applied.

FIG. 3(A) shows two Mis FETs using Example 1.
(10), (10') and two capacitors are respectively connected in series, and two ITr/Ce11 pairs are provided. That is, the convex region (35) has channel forming regions (6), (6''), and above it has a source or train (4) and a high concentration second impurity region (14). Further, a field insulator (3) is provided at the periphery of the bottom of the semiconductor substrate (1), and a first impurity region (15), (15°) and a drain or source (5), ( 5°), gate electrode (18)
, (18°), two MIS FETs (10), (10”) were placed horizontally as gate insulation W (2), (2”). The first region of N (15
), (15') connected (13), (13°) to the lower electrode (21) of the capacitor (20 (20"), (
2F), dielectrics (22), (22'), and upper electrodes (23), (23') were provided thereon to form capacitors (20), (20°).

In FIG. 3(A), (14) is a bit line, and (
18), ITr/Ce with (18') as the word line
This is part of a memory system that has a structure in which two 1Ls are paired. With a strong structure, the convex region (35) can be made common to the two M I 5FETs (10), (10'), and the male electric body (22), (22'
) has the characteristics of a stacked memory cell that can use a material with a high electrical constant different from the gate insulating film, such as tantalum oxide, titanium oxide, silicon nitride, barium titanate, or a multilayer film of these. In this embodiment, the outer periphery of the gate electrodes (18), (18') is insulated by an oxide interlayer insulator (7), the thickness of which is 0.1 to 1.0 μm. , first impurity region (15).

(15°) and capacitor (20), lower electrode (21) at (20°).

(2]) is connected to selective growth of tungsten (13).

(13) An electrode (contact) was formed. For this reason, the lower electrodes (21), (21°) were made of tungsten silicide.

Like this (when using the MIS FET of the present invention, the first
A contact can be obtained by connecting to the impurity region with a sufficient area margin. In other words, the first impurity region (
15), it is good to make (15'). Irrespective of this contact forming region, the channel length could be made precisely as shown in Example 1 without increasing the size of the MIS FET as seen from the substrate.

An interlayer insulator such as polyimide may be formed, and the third conductor wiring (9) may be formed on the upper surface thereof.

In addition, the area of the cells could be extremely small and the cells could be formed with high density. For manufacturing steps not shown in this example, Example 1 was used.

Embodiment 3j This embodiment is shown in longitudinal section in FIG. 3(B).

As is clear from the drawing, a single crystal semiconductor (35) is provided on the surface of the semiconductor substrate in a convex shape, and a gate insulating film (2) is formed around the side thereof and at the corner of the bottom of the substrate.
(2°) and a gate electrode (18).

(18') are formed as a pair. Drain or source of LDD structure with low impurity concentration (5), (5'
).

The source or drain (4) is connected to the channel length (6), (
6°) is provided for precise control. Using a part of this gate electrode such as silicon as a mask, high-concentration first impurity regions (15), (15') are provided in a self-lined manner, and a second high-concentration impurity region is also simultaneously applied to the upper part of the convex region. A region (14) was provided by -r neon implantation.

In this way, the IIS FET (10), (1
0'') were provided in a structure forming two pairs.

Next, since the contact openings (9) and (9') provided in the first impurity regions (15) and (15'') are provided in the same manner as in Example 1, this allows The side electrodes (20), (20'') were provided, for example, by forming doped silicon to a thickness of 0.1 to 1 μm.

On this upper surface, a tantalum oxide film (22) is formed by sputtering.
(22°) was formed to a thickness of 100 to 500 people. Thereafter, counter electrodes (23), (23)') were provided on this surface using metal or semiconductor, and after photoetching, capacitors (20), (20°) were formed.

Thus, the upper electrodes (23), (23') of the capacitors (20), (20') and the dielectric (22),
(22°) and lower electrodes (21), (21')
could be made as a stacked memory cell. In addition, this capacitor is connected to the field insulating film (3) or the convex region (35) and the gate electrode (18), (1
8"), and it was possible to increase the density of the cell area.

By providing a multilayer wiring (24) as a word line on the interlayer insulating film (17) via a contact to the second impurity region (14), and using the gate electrodes (18) and (18') as a bit line, Forming vertical channel type, source, and train horizontally arranged MIS FETs in pairs in a self-aligned manner was extremely effective in reducing size, increasing density, and improving reliability.

In this embodiment as well, similar to the second embodiment, a high dielectric constant material such as tantalum oxide can be used as the dielectric material, and the bit line is the region (24) and the word line is the gate electrode (18).
), (18°) could be configured as part of the ITr/'cell memory system.

The above embodiments 2 and 3 are all ITr/Ce1l DRA.
The purpose is to create M (tyramic memory).

However, in all of the processes of the present invention, μ-channel λ (Is FETs) such as amplifiers or inverters can be formed in other parts of the same substrate with the same shape. This was extremely convenient for creating a system.

Further, the lower electrode, the upper electrode, and the first region of the capacitor may all be formed of a silicon family made of the same main component as the substrate to improve reliability. Also, these are N
Since it is an integrated channel MIS FET,
It has multiple convex regions on the same substrate, some of which are P
It is effective to use a complementary integrated circuit as the channel MIS FET.

In the present invention, an electrically floating electrode may be provided in the gate insulating film to constitute a floating gate type nonvolatile memory.

In the above three embodiments, the material constituting the first region and the vertical rectangular or approximately triangular gate electrode (1
The material constituting 8) is mainly a material having the same main component as the substrate doped with impurities having P+ or N' conductivity type, such as silicon.

However, they may be mixtures or compounds of silicon, Mo, and W (8fosi2.WSi2), and may also be formed into a multilayer structure of intrinsic, P type or N+ type semiconductors, or may be made of semiconductors such as silicon and λ1o. It goes without saying that it may have a multilayer structure with biplatinum, biplatinum, or a compound thereof.

In the present invention, the semiconductor substrate is mainly made of single crystal silicon. However, it goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

In addition, the channel forming region is formed using MISPPT using surface diffusion.
Instead, it may be a recessed channel type.

Alternatively, a method using majority carriers may be used.

These are based on the method of controlling the structure of the channel section under the gate insulation crotch.

``Effects'' As is clear from the above embodiments, the present invention does not have a conventional structure in which the source and drain are separated from each other by gate electrodes and are wired laterally, but rather the source or drain is connected to the outside. It is easy to peel off, the upper surface has the same flat surface as the substrate, and the channel is vertically shaped to form a microchannel. Even such microchannels have the characteristic that the channel length can be precisely controlled by forming a source and drain as an LDD in them and controlling the concentration of ion implantation. In addition, the gate electrode has a structure in which it is mechanically reinforced by leaning over the side of the convex first region in an effort to achieve high reliability. The threshold voltage of the channel forming region has a structure in which impurities such as boron are doped into the upper part of the semiconductor diagonally or laterally, and the frequency is determined by its structural characteristics and the channel length of 0.1 to 1 μm. The present invention has a major feature in that an ultrashort channel (μ channel) MIS FET with a response speed of 1 to 10 GHz can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of the drawing]

FIG. 1 shows a vertical cross-sectional view of a conventionally known λ(Is FET. FIG. 2 is a vertical cross-sectional view showing the manufacturing process and structure of an embodiment of the present invention. FIG. 3 shows an ITr/Is FET. It is a vertical cross-sectional view of another embodiment of the present invention in which a pair of Ce1l memories are provided. 1... Semiconductor substrate 2... Convex region 3... Field insulation 5.5゛4 ・ ・ ・ 15.15 ・ 14 ・ ・ 18.18 ・ 10.10 ・ 20, 20 ・■～■・ ・Drain or source・Source or drain・First impurity region・Second Impurity region, gate electrode, insulated gate field effect transistor (MIS FET)... capacitor... Turning treatment using a photomask! Figure 2 Figure 2

Claims (1)

[Claims] 1. A corner portion consisting of a convex region on a semiconductor substrate of one conductivity type, an insulating film covering the side and bottom surfaces of the region, and the region and the bottom surface of the substrate without extending above the region. a rectangular or triangular gate electrode on an insulating film; a low concentration drain or source provided on the bottom of the semiconductor substrate; a first impurity region with a higher concentration than the drain or source; a low concentration source or drain provided above the convex region; and a second impurity region provided above the source or drain. and has an end of the source or drain in the lateral direction of the upper end of the gate electrode, and a side surface of the convex region provided under the gate insulator below the gate electrode. a channel forming region that allows current to flow in the vertical direction;
An insulated gate field effect semiconductor device having a vertical channel structure including a drain or a source provided at the bottom of the semiconductor substrate below the gate electrode.