JPS60150643A - Complementary semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a semiconductor device of enhanced integration that is completely free of latchup by a method wherein an elements-isolating insulator is buried inside a groove and high-density impurity regions are formed in contact with each other in the vicinity of the bottoms of neighboring grooves. CONSTITUTION:An impurity of the second conductivity type is introduced selectively into a portion 33 of a semiconductor substrate 31 of the first conductivity type. Anisotropic etching is performed to selectively affect the substrate 31 for the formation of grooves 35. Next, an impurity of the first or second conductivity type is introduced into the bottoms of the grooves 35. The impurity is diffused by thermal treatment for the formation of element-forming regions of the first and second conductivity types and of high-density impurity regions 39 of the first or second conductivity type that are in contact with each other in the vicinity of the bottoms of neighboring grooves 35. Further, an insulating material 41 is buried inside the grooves 35 for the isolation of elements for the formation of a MOS element with a chennel of the second conductivity type in the element region of the first conductivity type and a MOS element with a channel of the first conductivity type in the element region of the second conductivity type.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary semiconductor device and a method for manufacturing the same, and particularly to an element isolation technique for a complementary semiconductor device.

[Technical background of the invention and its problems]

Conventionally, as an element isolation method for semiconductor devices, a selective oxidation method (Loeo
s method) is the most commonly used. When elements of a complementary MO8 (0MO8) semiconductor device are separated using this method, the result is as shown in FIG. In the figure, 1 is, for example, an n-type silicon substrate, and the surface of this substrate is p8! ! Well area 2
is provided selectively. A field oxide film 3 is formed using a selective oxidation method using a silicon nitride film as a mask on the surface between the substrate and the well region 2 other than the well region 2. ...
There is water forming. A dirt electrode 51 is formed on the substrate other than the well region 2 via a dirt oxide film 41, and a gate electrode 6! is formed on the JH surface of the substrate. By ion implantation using the mask as a mask, + type source and drain regions 6 and 7 are formed, thereby forming a p-channel MO transistor (8). There is a gate oxide film 4 on the well region 2!
An electrode 5z is formed through the well region 2, and n+ type source and drain regions 8 and 9 are formed on the surface of the well region 2 by ion implantation using the gate electrode 52 as a mask. Sister ice consists.

However, in 0MO8, in order to prevent latch-ag, it is necessary to place a gold film at a certain distance or more between the n+ type impurity region and the p+ type impurity region.
When using the method (OS method), the width of the field oxide film 3 used to separate the well regions 2 is usually 6 μm or more.

This poses a major obstacle to higher integration of elements.

Therefore, element isolation techniques as shown in FIGS. 2(,) to (c) have been proposed. First, for example, an n-type silicon substrate 1
For example, boron is ion-implanted to form a well region selectively in a part of the substrate 1 to form a boron ion-implanted layer 12, and then a part of the substrate 1 is selectively etched by anisotropic etching. Deep groove13. ... is formed (as shown in FIG. 2). Next, heat treatment is performed to diffuse the boron in the ion-implanted layer No. 2 to form a p-type well region J4.
form. Next, for example, CVD 11! After depositing the chemical film, the entire surface is etched back to form the groove 3.・
...CVD oxide film only inside 15. . . . is buried to perform element isolation (as shown in FIG. 3(b)). Next, according to a normal process, a dirt electrode 17. form,
Dart electrode 17. hp+ by ion implantation using as a mask
Type source and drain regions 18 and 19 are formed. Also,
A dirt electrode 17g is formed on the well region 14 via the dirt oxide film 76, and pn+W7- source and drain regions 20.2 are formed by ion implantation using the gate electrode 172 as a mask.
form 1.

Note that -CVD oxide film 25. m1s instead of...

. . . For example, multi-element isolation may be performed by embedding a polycrystalline silicon film through a thermally evaporated film.

In the CMO8 semiconductor device shown in FIG. 2(c), there is a deep groove J3.
CVD oxide film 15 buried in w... . . . effectively increases the distance between the n-type impurity region and the p-type impurity region, so that the resistance to tchia and f performance can be reliably improved, and the CVD oxide film 15. ... can be made approximately 1 μm wide, which is advantageous for higher integration of elements.

However, the resistance between the n+ type impurity region and the p+ type impurity region is large, and it is not possible to completely latch the transistor 7';1-. It is possible to use the above-mentioned Nihaevitaxial wafer I to reduce the resistance and form a buried layer with high concentration so that the insulator in the trench reaches this buried layer, or to increase the impurity concentration in the well region. Conceivable. However, with the former method, it is difficult to form a buried layer of high concentration with good controllability, and since the epitaxial wafer is expensive, there are also problems in terms of cost. On the other hand, in the latter method, if the concentration in the well region is too high, it will affect the device characteristics on the substrate surface, so counter ion implantation of opposite conductivity type ions is required to lower the concentration near the surface. There are many problems such as complicated processes, decreased controllability, and increased costs.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is completely latch-up-free, without using an ubiquitous substrate, while keeping the concentration of the substrate and well region at the normal concentration. The present invention aims to provide a complementary semiconductor device with improved performance and a method for manufacturing the same.

[Summary of the invention]

The complementary semiconductor device of the invention of No. 1 of the present application has an insulator for element isolation (for example, an oxide film or a polycrystalline silicon film with an oxide film interposed therebetween) buried inside a groove formed in a semiconductor substrate of 1g1 conductivity type. and first or second conductivity type crystal a impurity regions formed in contact with each other near the bottoms of adjacent trenches, and first and twenty-fourth crystal impurity regions formed separately by the insulator.
an MO8 element of a second conductivity type channel formed in the element region of the first conductivity type, and an MO8 element of a second conductivity type channel formed in the element region of the first conductivity type. The device is characterized by comprising a device.

According to such a complementary semiconductor device, even if a parasitic silicon risk is formed, the current amplification factor can be reduced by the high concentration impurity region (buried low resistance layer), so latch-up can be completely prevented. .

Further, the method for manufacturing a complementary semiconductor device according to the second invention of the present application includes a step of selectively introducing an impurity of a 24th conductivity type into a part of a semiconductor substrate of a first conductivity type, and an anisotropic etching. A step of selectively etching a part of the substrate to form a groove, a step of introducing an impurity of a first or second conductivity type into the bottom of the groove, and a step of diffusing a cine fine substance by heat treatment to form a first conductivity type impurity. and second
High-concentration impurity impurities of the first or 24th conductivity type that form element regions of the conductivity type and are separated from each other near the bottoms of adjacent grooves.
a step of forming a conductive region, a step of embedding an insulator for element isolation in the trench, and a step of embedding an MO8 element of the second conductivity type channel in the element region made of the first conductivity; The present invention is characterized by comprising a step of forming MO8 graded metals of the first conductivity type channels in the element region.

According to such a method, a highly-concentrated impurity region can be formed with extremely good controllability, and at low cost.
A complementary semiconductor device according to the invention can be manufactured.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 3(a) to 3(f).

First, a thermal oxide film 32 having a thickness of 500^ is formed on the surface of the p-type silicon substrate 3. Next, using a photoresist pattern (not shown) as a mask, ions of glue for forming an n-well are selectively implanted into a part of the substrate 3 to form a phosphorus ion-implanted layer 33. Subsequently, after removing the photoresist cutter, a CVD oxide film 34 with a thickness of 1 μm is formed on the entire surface.
Deposit. Subsequently, after selectively etching a portion of the CVD oxide film 34 and thermal oxide film 32 using a photoresist pattern (not shown) as a mask, the photoresist pattern is removed (2) (as shown in FIG. 3).

Next, using the grooves and turns of the CVD oxide film 34 as a mask, the substrate 3 is etched by anisotropic etching to form grooves 35 with a depth of 5 μm. ... formed at intervals of t5 μm. Next, thermal oxidation was performed at 1000°C and the temperature was 35. A thermal oxide film 36 having a thickness of about 1000° C. is formed on the inner surface of the semiconductor device (as shown in FIG. 3(b)).

Next, poron is ion-implanted at a dose of 3 x 10"a++-2 to form a poron ion-implanted layer 37 at the bottom of the groove 35 (as shown in FIG. 3C).
.

Next, CVD oxide film 34. . . . thermal oxide film 32 and grooves 35 on the surface of the substrate 31. After etching the thermal oxide film 36 on the inner surface, a well drive-in for forming an n-well is performed for 5 hours at a high temperature of 1200° C., for example.
An n-well region 38 with a depth of 3 μm is formed. At the same time, groove 35. . . . The bottom part is the Ron ion implantation layer 37.・・・
The boron of * is also diffused to form a p+ type impurity region (buried low resistance layer) 39. This p+ type impurity region 39 is connected to the adjacent trench 36. ...The p+ type impurity regions at the bottom are in contact with each other to form a continuous structure. Next, the thermal oxidation groove 35. ...Film thickness of approximately 5 on the surface of the substrate 3 including the inner surface
A thermal oxide film 40 of 00X is formed (as shown in FIG. 4(d)).

Next, after depositing a polycrystalline silicon film over the entire surface, the surface is planarized and grooves 35. ...Polycrystalline silicon film 41 only inside. . . . is buried to perform element isolation (as shown in the figure (-)).

Then, using a well-known technique, dirt electrodes 431+432 are formed on the substrate 3 other than the n-type well region 38 and on the n-type well head region 38 via dirt oxide films 42+ and 422, respectively.
form. Subsequently, using the dirt electrode 431 as a mask, ions of, for example, arsenic are selectively implanted into the substrate 3 other than the well region 38, thereby forming n+ type source and drain regions 44 and 45. Next, the dart electrode 43
By selectively ion-implanting, for example, pyrons, into the well region 38 using No. 2 as a mask, p-type north and drain regions 46 and 47 are formed. Subsequently, after depositing an interlayer insulating film 48 on the entire surface, contact holes 49. . . . After opening a hole and depositing an A7 film on the entire surface, patterning is performed to form wiring 50. ... to produce 0MO8 (
Figure (f) shown).

According to 0MO8 shown in FIG. 3(f), the groove 35
,...Since the p+ type impurity region 39 is continuously formed at the bottom, even if a PNPN or NPNP thyristor is formed, the current amplification factor β decreases because the p+ type impurity region 39 has a low resistance. This completely prevents latch-up.

Further, according to the method of the present invention, latch-up can be prevented without using an epitaxial wafer or increasing the concentration of the well region, which is advantageous in terms of cost.
In addition, the p-type impurity region (buried low resistance layer) 39 is in the groove 3.
5. ... can be controlled simply by the depth of the impurities, the amount of impurities, and the heat treatment time, and the controllability is extremely good, so that the device characteristics do not deteriorate.

Note that in the above embodiment, the groove 35. The depth of ... is 5 μm1
Groove 35. Although the interval between the grooves 35. The interval between... is groove 35. It suffices if the depth is less than twice the depth of...

Further, in the step of FIG. 3(c), the groove 35. When boron ions are implanted into the bottom of the groove 35. A thermal oxide film 36 is formed on the inner surface of the groove 35. . . . An oxide film or a silicon nitride film is formed on the inner sidewall, and the groove 35. ...It is desirable to make it difficult for impurities to be introduced into areas other than the bottom.

Further, in the above embodiment, the groove 35. Although the polycrystalline silicon film 4 is buried inside the thermal oxide film 40, the present invention is not limited to this, and for example, a CVD oxidized film may be buried.

Furthermore, in the above embodiment, the buried low resistance layer is formed of a pm high concentration impurity region, but it is formed of a nm high concentration impurity region.

A similar effect can be obtained by forming a high concentration impurity region.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a complementary semiconductor device with a high degree of integration and completely latch-up-free, and a method for manufacturing such a complementary semiconductor device with good controllability and at low cost. It is.

[Brief explanation of drawings]

Figure 1 shows 0MO3 produced using the conventional selective oxidation method.
2(a) to 2(C) are sectional views showing a method of manufacturing 0MO8 using other conventional element isolation techniques, and FIGS. 3(a) to 3(f) are cross-sectional views showing an example of the present invention. It is a sectional view showing a manufacturing method of 0MO8 in. 3...p-type silicon substrate, 32, 36, 40...
Thermal oxide film, 33... Phosphorus ion implantation layer, 34...C
VD oxide film, 35... Groove, 37... Boron ion implantation layer, 38... N type well region, 39... P+ type draft region, 4... Polycrystalline silicon film, 42. +42ri...dirt oxide film, 431+432'''dart electrode,
44, 45... n0m source, drain region, 46
．． 47...p type 10 north, drain region, 48...
Interlayer insulating film, 49... contact hole, 50...
Scarlet. Figure 2 Figure 3 (a) Figure 3 (C) Figure 3 (e)

Claims (4)

[Claims] (1) An insulator for element isolation buried inside a groove formed in a semiconductor substrate of a first conductivity type, and an insulator of a first conductivity type or a second conductivity type formed in contact with each other near the bottom of an adjacent groove. A high concentration impurity region, first and second conductivity type element regions formed separately by the insulator, and a 24th conductivity type channel MO8 element formed in the first conductivity type element region. and an MO8 element of a first conductivity type channel formed in the element region of the second conductivity type. (2) The complementary semiconductor device according to claim 1, wherein the interval between adjacent grooves is not more than twice the depth of the grooves. (3) A step of selectively introducing a second conductivity type impurity into a part of the first conductivity type semiconductor substrate, and selectively etching a part of the substrate by anisotropic etching to form a groove. a step of introducing an impurity of the first or second conductivity type into the bottom of the groove, and a step of diffusing the cine dull material by heat treatment to form element regions of the first and second conductivity types, and forming adjacent regions. a step of forming high concentration impurity regions of a first or second conductivity type that contact each other near the bottom of the trench, a step of burying an insulator for element isolation inside the trench, and a step of burying an element region of the first conductivity type. A method for manufacturing a complementary semiconductor device, comprising: forming an MO8 element of a second conductivity type channel, and forming an MO8 element of a first conductivity type channel in the element region of the second conductivity type. (4) An oxide film or a nitride film is formed on at least the side walls of the trench when introducing the first or 24th type impurity into the bottom of the trench. A method for manufacturing a complementary semiconductor device.