JP2000174267A - Mis semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To limit the formation region for an LDD(lightly doped drain) structure and prevent an increase in the space factor of a semiconductor substrate. SOLUTION: In this MIS(metal insulator semiconductor) semiconductor device, an N-type drain region 3 and a source area 4 are formed selectively in a P-type well region 2, and the N-type drain region 3 is provided with a high impurity concentration region (N+ area) 3A with an impurity concentration of 1×1019-1×1020/cm3 and a low impurity concentration region (N- area) 3B with an impurity concentration of 1×1017-1×1018/cm3 which is formed adjacent to the periphery of the region 3A and is smaller in depth than the region 3A. The N-type source region 4 is provided with only a high impurity concentration region (N+ area) with an impurity concentration of 1×1019-1×1020/cm3 which is formed on both sides of the N-type drain region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
More particularly, the present invention relates to an LDD (Lightly Doped Drai).
n) A MIS type semiconductor device having a structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art LSIs (large-scale integrated circuits) such as memories and processors known as representatives of semiconductor devices are:
MOS (Metal Oxide), which is mostly excellent in terms of integration
Semiconductor) type transistors. Such MOS-type LSIs are widely applied to various storage devices such as information devices because cost reduction can be achieved by high integration.

The individual MOs constituting a MOS LSI
In the S-type transistor, one of the important factors is to improve the transistor performance by reducing the gate length. By the way, when the gate length of the MOS transistor is reduced, the drain electric field at the end of the channel increases during operation, so that a portion of the carrier passing through the channel is trapped in the gate insulating film by the electric field. The phenomenon occurs. When carriers are trapped in the gate insulating film, the threshold value of the MOS transistor fluctuates, which causes a malfunction such as a malfunction.

In order to prevent such a hot electron phenomenon from occurring, an LDD structure has conventionally been employed in a MOS transistor. In this LDD structure, a low impurity concentration region is provided adjacent to a side of a high impurity concentration region constituting a drain region opposite to a source region, so as to reduce a drain electric field at a channel end. is there. For example, Japanese Patent Application Laid-Open No. 4-346476 discloses a method of manufacturing a semiconductor device in which a gate is miniaturized in a MOS transistor having an LDD structure. Hereinafter, with reference to FIGS. 13A to 13C and FIGS. 14D to 14F, a method of manufacturing the same semiconductor device will be described in the order of steps.

[0005] First, as shown in FIG.
An oxide film 52 having a thickness of 200 to 400 nm is formed on a P-type silicon substrate 51 by a (Chemical Vapor Deposition) method.
Is formed, an opening 53 of about 0.6 μm is formed in the oxide film 52 by lithography. Next, a nitride film 54 having a thickness of 200 to 300 nm is formed by a CVD method. Next, as shown in FIG. 13B, the nitride film 54 is etched back to form a sidewall 55, and the interval between the sidewalls 55 is formed to be 0.15 to 0.2 μm. At the same time, the silicon substrate 51 in the opening 53
After the surface of the silicon substrate 51 is etched by 100 to 150 nm, a gate oxide film 56 is formed on the exposed surface of the silicon substrate 51.

[0006] Next, as shown in FIG.
A polycrystalline silicon having a thickness of 300 to 400 nm is formed by a method, and phosphorus is added to the polycrystalline silicon in an amount of 1 × 10 ²⁰ to
After doping to an impurity concentration of 1 × 10 ²¹ / cm ³ to lower the resistance, the polysilicon is etched back to form a gate electrode 57 having a gate length of 0.2 to 0.3 μm. Next, as shown in FIG. 14D, after removing the oxide film 52, arsenic is deposited at 2 × 10 ^{15 to} 5 × 10 ¹⁵ / cm 3 as shown by an arrow 58A to form a high-concentration N-type layer. Ion implantation is performed at a dose of ² . Next, as shown in FIG. 14E, after removing the sidewalls 55 of the nitride film, phosphorous is added in a concentration of 1 × 10 ^{13 to} 3 × 10 3 as shown by an arrow 59A to form a low-concentration N-type layer. Ion implantation is performed at a dose of ¹³ / cm ² .

[0007] Next, as shown in FIG.
By performing a heat treatment at 0 ° C. for 20 to 40 minutes, the impurities implanted as described above are activated to form the high-concentration N-type layer 58 and the low-concentration N-type layer 59. As described above, the LD region having the N-type drain region 60 and the source region 61 including the high-concentration N-type layer 58 and the low-concentration N-type
A MOS transistor having a D structure is completed. According to such a MOS transistor, the gate length is determined by the distance between the sidewalls 55, so that a fine gate can be formed.

[0008]

By the way, in the conventional method of manufacturing a semiconductor device described in the above-mentioned publication, the LDD structure is formed not only in the drain region but also in the source region. There is a problem that it increases. That is, in the step of FIG.
In order to form the structure, phosphorus is ion-implanted using the gate electrode 57 as a mask as shown by an arrow 59A. At this time, phosphorus is ion-implanted not only at the planned drain region formation position but also at the source region formation planned position. Therefore, in the step of FIG. 14F, the low-concentration N-type layer 59 is formed at a position other than the position where the drain region is originally required. Therefore, the area occupied by the semiconductor substrate increases by the width of the low-concentration N-type layer 59 in the source region 61, and the utilization rate of the semiconductor substrate decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is intended to limit an area for forming an LDD structure to prevent an increase in the area occupied by a semiconductor substrate.
An object is to provide an S-type semiconductor device and a method for manufacturing the same.

[0010]

In order to solve the above-mentioned problems, the present invention is directed to a semiconductor device according to a first aspect of the present invention, wherein a first second conductivity type semiconductor region and a second second conductivity type semiconductor region are selectively provided in a first conductivity type semiconductor region. A two-conductivity-type semiconductor region is formed, and an insulation gate is formed between the first and second second-conductivity-type semiconductor regions.
An S-type semiconductor device, wherein the first second conductivity type semiconductor region is formed adjacent to a high impurity concentration region and around the high impurity concentration region, and has a low impurity concentration shallower than the high impurity concentration region. And the second second-conductivity-type semiconductor region comprises only high-impurity-concentration regions formed on both sides of the first second-conductivity-type semiconductor region. It is characterized by comprising an endless annular conductive layer formed through a film.

[0011] The invention according to claim 2 provides the M according to claim 1.
According to the IS type semiconductor device, a first sidewall insulating film is formed on an inner side surface of the conductive layer of the insulating gate so as to cover the low impurity concentration region of the first second conductive type semiconductor region. On the other hand, a second sidewall insulating film is formed on an outer side surface of the conductive layer so as to cover an end of the second second conductivity type semiconductor region.

According to a third aspect of the present invention, there is provided the MIS type semiconductor device according to the first or second aspect, wherein the conductive layer is made of polycrystalline silicon.

According to a fourth aspect of the present invention, there is provided the MIS type semiconductor device according to the second or third aspect, wherein the first sidewall insulating film is made of a silicon nitride film.

[0014] The invention described in claim 5 is the invention according to claim 2,
The MIS semiconductor device according to item 3 or 4, wherein the second sidewall insulating film is formed of a silicon oxide film.

According to a sixth aspect of the invention, there is provided the MIS type semiconductor device according to any one of the first to fifth aspects, wherein the first second conductivity type semiconductor region is a drain region. .

According to a seventh aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the first second conductivity type semiconductor region and the second second conductivity type semiconductor region are selectively provided in the first conductivity type semiconductor region.
Is formed, and the first and second semiconductor regions are formed.
A method of manufacturing an MIS type semiconductor device in which an insulating gate is formed between second conductive type semiconductor regions.
After forming a conductive layer on the conductive type semiconductor region via a gate insulating film, the conductive layer is endlessly patterned to form an opening at a position where the first second conductive type semiconductor region is to be formed. Forming a portion, and introducing a second conductivity type impurity into the first conductivity type semiconductor region from the opening to form a low impurity concentration region forming a part of the first second conductivity type semiconductor region. Forming a first sidewall insulating film on the inner side surface of the conductive layer so as to cover the low impurity concentration region; and forming an outer side surface of the conductive layer. Forming a second sidewall insulating film on the first and second sidewall insulating films, and the first and second sidewall insulating films,
And using the conductive layer as a mask, introducing a second conductive type impurity into the first conductive type semiconductor region, and forming the first second conductive type semiconductor region deeper in the low impurity concentration region than the low impurity concentration region. And a high impurity concentration region forming the second second conductivity type semiconductor region on both sides of the first second conductivity type semiconductor region at the same time as forming the high impurity concentration region forming a part of the first impurity region. And forming a concentration region.

According to the present invention, the first and second conductive type semiconductor regions and the second and second conductive type semiconductor regions are selectively provided in the first conductive type semiconductor region.
Is formed, and the first and second semiconductor regions are formed.
A method of manufacturing an MIS type semiconductor device in which an insulating gate is formed between second conductive type semiconductor regions.
After forming a conductive layer on a conductive type semiconductor region via a gate insulating film, the conductive layer is selectively removed to form the first and second conductive layers.
An opening forming step of forming an opening at a position where the conductive semiconductor region is to be formed; and introducing the second conductive impurity into the first conductive semiconductor region from the opening to form the first second conductive impurity.
Forming a low-impurity-concentration region that forms a part of the conductive-type semiconductor region; and patterning the conductive layer into an endless ring, and then covering the low-impurity-concentration region on the inner side surface of the conductive layer. Forming a first sidewall insulating film in the first step, and introducing a second conductive type impurity into the first conductive type semiconductor region using the first sidewall insulating film and the conductive layer as a mask. Forming a high impurity concentration region forming a part of the first second conductivity type semiconductor region deeper than the low impurity concentration region in the low impurity concentration region, and simultaneously forming the first second conductivity type semiconductor. Forming a high impurity concentration region forming the second second conductivity type semiconductor region on both sides of the region; and forming the second impurity concentration region on the outer side surface of the conductive layer.
Forming a second sidewall insulating film so as to cover the end of the second conductivity type semiconductor region.

According to a ninth aspect of the present invention, there is provided a method for manufacturing a MIS type semiconductor device according to the seventh or eighth aspect, wherein the low impurity concentration region and the high impurity concentration region are formed after the high impurity concentration region forming step. And a heat treatment step of performing a heat treatment for activating.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a MIS type semiconductor device according to the seventh, eighth or ninth aspect, wherein polycrystalline silicon is used as the conductive layer.

The invention according to claim 11 is the same as the claim 7.
The method according to any one of Items 1 to 10, wherein a silicon nitride film is used as the first sidewall insulating film.

The invention according to claim 12 is the same as the claim 7.
According to the method of manufacturing a MIS type semiconductor device according to any one of the first to eleventh aspects, a silicon oxide film is used as the second sidewall insulating film.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. First Embodiment FIG. 1 is a plan view showing a configuration of a MIS type semiconductor device according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. -B arrow sectional view, and FIG.
6 (g) to 6 (i) are process diagrams showing a method of manufacturing the same MIS type semiconductor device in the order of steps. M in this example
In the IS type semiconductor device, as shown in FIGS. 1 to 3, for example, a P type well region 2 is formed in a P type silicon substrate 1,
An N-type drain region 3 and a source region 4 are selectively formed in the P-type well region 2, and a gate oxide film 5 is provided between the N-type drain region 3 and the N-type source region 4.
, An endless annular gate conductive layer 6 made of polycrystalline silicon is formed.

Here, the N-type drain region 3 has a high impurity concentration.
Degree 1 × 10¹⁹~ 1 × 10²⁰/ Cm³High impurity concentration
Degree area (N⁺Region) 3A and the high impurity concentration region 3A
Is formed adjacent to the periphery of the region and is higher than the high impurity concentration region 3A.
And shallow impurity concentration of 1 × 10 ¹⁷~ 1 × 10¹⁸/ Cm
³Low impurity concentration region (N⁻Area) 3B
ing. The N-type source region 4 is an N-type drain region.
3 has an impurity concentration of 1 × 10¹⁹~ 1 ×
10²⁰/ Cm³High impurity concentration region (N⁺(Area) 4A
It consists only of: Thus, the LDD structure becomes
L is limited to be formed only in the drain region 3 and L
In order to prevent an increase in the area occupied by the substrate 1 due to the DD structure.
It is planned. Also, the N-type drain region 3 is
Common drain region for the N-type source region 4 on the side
It is configured to operate.

The curved inner side surface of the gate conductive layer 6 has N
A first sidewall insulating film 7 made of a silicon nitride film is formed so as to cover low impurity concentration region 3B of type drain region 3, while an end of N-type source region 4 is formed on the outer side surface of gate conductive layer 6. A second sidewall insulating film 8 made of a silicon oxide film is formed to cover. When forming the high impurity concentration region 3A which is a part of the N-type drain region 3, the first sidewall insulating film 7 is formed only at a substantially central position of the low impurity concentration region 3B. Perform a masking action as described above. The second sidewall insulating film 8 acts as a mask so that when a silicide layer is formed in the N-type source region 4 as described later, the silicide layer is accurately formed on the surface of the N-type source region 4. I do. Reference numeral 10 denotes an element isolation insulating film made of a silicon oxide film.

On the surfaces of the N-type drain region 3, the N-type source region 4 and the gate conductive layer 6, cobalt (C
o), a silicide layer 11 made of a refractory metal such as titanium (Ti) or molybdenum (Mo) is formed to reduce the contact resistance when the drain electrode, the source electrode and the gate electrode are drawn. A first interlayer insulating film 12 made of a silicon nitride film or the like and a second interlayer insulating film 13 made of a silicon oxide film or the like are formed on the entire surface of the substrate 1, and the N-type of the first and second interlayer insulating films 12 and 13 is formed. Contact holes 14 are formed on the surfaces of the drain region 3 and the source region 4, respectively. Each contact hole 14 has a plug conductor 15 such as tungsten.
, And a drain electrode 16 and a source electrode 17 made of aluminum or the like are drawn out through the respective plug conductors 15. Further, the first and second interlayer insulating films 12, 1
A contact hole 19 is formed around the third gate conductive layer 6, and a gate conductor 20 such as polycrystalline silicon is formed in the contact hole 19. Further, a contact hole 14 is formed in the surface of the gate conductor 20, and a plug conductor 15 such as tungsten is buried in the contact hole 14, and a gate electrode 1 such as aluminum is formed through the plug conductor 15.
8 has been pulled out.

As described above, according to the MIS type semiconductor device of this example, the LDD structure is limited to only the drain region by forming the low impurity concentration region 3B only in the N type drain region 3, so that the LDD Since the area occupied by the structure in the substrate 1 can be reduced, the utilization rate of the semiconductor substrate can be improved. Thus, LD
Since the D structure does not exist in the source region, the occurrence of the source parasitic resistance can be suppressed, so that the drain current is increased by 10 to 30% as compared with the conventional example in which the LDD structure also exists in the source region. be able to. As a result, the driving capability of the MIS type semiconductor device can be improved.

Further, according to the structure of this example, the conductive layer 6 forming the insulating gate is formed in an endless ring, so that the gate resistance can be reduced. Also, N
Since the drain region 3 is operated as a common drain region for the N-type source regions 4 on both sides,
The drain capacitance can be reduced. Therefore,
This is advantageous when applied to high frequency applications, and can be operated in a higher frequency range, so that the applicable range can be expanded.

Next, FIGS. 4 (a) to 4 (c) to 6 (g)
With reference to (i) to (i), a method of manufacturing the MIS semiconductor device of this example will be described in the order of steps. First, as shown in FIG. 4A, for example, using a P-type silicon substrate 1 by a well-known LOCOS (Local Oxidation of Silicon) method.
After selectively forming the element isolation insulating film 10, a P-type impurity such as boron is ion-implanted in the substrate 1 to form the P-type well region 2. Next, after a silicon oxide film 23 having a thickness of 100 to 400 nm is formed on the entire surface by a CVD method, the silicon oxide film 23 at a position where a drain region is to be formed is selectively removed by a lithography method. .
An opening 24 of 5 to 2.0 μm is formed.

Next, as shown in FIG. 4B, a gate oxide film 5 having a thickness of 5 to 10 nm is formed on the surface of the P-type well region 2 in the opening 24 by thermal oxidation. A polycrystalline silicon film 25 having a thickness of 100 to 300 nm is formed on the entire surface by the method.

Next, as shown in FIG. 4C, the polycrystalline silicon film 25 is etched back and patterned to form an endless end having a width of about 0.1 μm on the side surface of the opening 24 of the silicon oxide film 23. An annular gate conductive layer 6 is formed.
At this time, the inner side surface of the gate conductive layer 6 is formed in a curved shape.

Next, after the gate oxide film 5 in the opening 24 is removed, as shown in FIG.
An N-type impurity such as phosphorus or arsenic is ion-implanted into the type well region 2 to have an impurity concentration of 1 × 10 ¹⁷ to 1 × 10
A low impurity concentration region 3B of ¹⁸ / cm ³ is formed. This low impurity concentration region 3B constitutes a part of the drain region and becomes an LDD region. Next, a silicon nitride film 26 having a thickness of 100 to 200 nm is formed on the entire surface by the CVD method.

Next, as shown in FIG. 5E, the silicon nitride film 26 is etched back and patterned to form a low impurity concentration region 3 on the inner side surface of the gate conductive layer 6.
A first sidewall insulating film 7 having a width of about 0.1 μm is formed so as to cover B. This first sidewall insulating film 7
Is formed under etching conditions in which the selectivity between the silicon oxide film 23 and the silicon nitride film 26 is approximately 1:50 or more, and only the silicon nitride film 26 is selectively removed. At this time, the first sidewall insulating film 7 is formed so as to expose the upper part of the gate conductive layer 6. As will be described later, when forming the high impurity concentration region 3A which is a part of the N-type drain region 3, the first sidewall insulating film 7 is formed such that the high impurity concentration region 3A is substantially the same as the low impurity concentration region 3B. It is formed so as to perform a masking action such that it is formed only at the center position.

Next, as shown in FIG. 5F, the silicon oxide film 23 is etched back and patterned to form a second sidewall insulating film having a width of about 0.1 μm on the outer side surface of the gate conductive layer 6. A film 8 is formed. The formation of the second sidewall insulating film 8 is performed under etching conditions in which the selectivity between the silicon oxide film 23 and the silicon nitride film constituting the first sidewall insulating film 7 is approximately 50: 1 or more. Then, only the silicon oxide film 23 is selectively removed. As will be described later, this second sidewall insulating film 8 is used to form the N-type source region 4 exactly when the silicide layer is formed in the N-type source region 4.
It is formed in order to perform a masking action such as that formed on the surface of the substrate.

Next, as shown in FIG. 6 (g), using the gate conductive layer 6, the first sidewall insulating film 7 and the second sidewall insulating film 8 as a mask, phosphorus and arsenic are formed in the P-type well region 2. By ion-implanting an N-type impurity such as, for example, the impurity concentration deeper than the low impurity concentration region 3B is set to about 1 × 10 ¹⁹ to 1 × 10
A high impurity concentration region 3A of ²⁰ / cm ³ is formed. At the same time, a high impurity concentration region 4A having the same impurity concentration as described above is formed at a position outside the gate conductive layer 6 where a source region is to be formed.

As described above, inside the gate conductive layer 6,
An N-type drain region 3 is formed which includes a high impurity concentration region 3A and a low impurity concentration region 3B formed adjacent to the periphery of the high impurity concentration region 3A and shallower than the high impurity concentration region 3A. Outside the gate conductive layer 6, an N-type source region 4 composed only of the high impurity concentration region 4A formed on both sides of the N-type drain region 3 is formed. Therefore, the LDD structure has the N-type drain region 3.
It is formed limited to only. Next, the substrate 1 is exposed to an inert atmosphere such as nitrogen,
And RTA (Rapid Thermal Annealin) for 10 to 60 seconds.
g: rapid thermal annealing)
The above-described N-type drain region 3 and source region 4 are activated.

Next, as shown in FIG. 6 (h), in order to reduce the contact resistance when each electrode is led out, the surfaces of the N-type drain region 3, the source region 4, and the gate conductive layer 6 are respectively silicided. The layer 11 is formed. In forming the silicide layer 11, a high melting point metal layer such as cobalt, titanium, or molybdenum is formed on the surface of each region in advance, and then heat treatment is performed to react with the silicon film.

Next, as shown in FIG. 6I, a first interlayer insulating film 12 made of a silicon nitride film or the like and a second interlayer insulating film 13 made of a silicon oxide film or the like are formed on the entire surface by the CVD method. After that, the first and second interlayer insulating films 12, 1
Contact holes 14 are formed on the surfaces of the N-type drain region 3 and the source region 4 respectively. Further, as shown in FIG. 3, after a contact hole 19 is formed around the gate conductive layer 6 of the first and second interlayer insulating films 12 and 13, a gate conductor such as polycrystalline silicon is formed in the contact hole 19. 20 is formed. Next, the gate conductor 20
Contact holes 14 are formed on the surface of the substrate. Subsequently, after plug conductors 15 such as tungsten are buried in the respective contact holes 14, a drain electrode 16, a source electrode 17, and a gate electrode 18 are formed through the respective plug conductors 15, whereby the MIS of this example is formed. Complete the semiconductor device.

As described above, according to the structure of this example, the N-type drain region 3 and the source region 4 are selectively formed in the P-type well region 2, and the N-type drain region 3 has an impurity concentration of 1 ×. A high impurity concentration region 3A of 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ and an impurity concentration of 1 × 10 ¹⁷ to 1 which is formed adjacent to the periphery of the high impurity concentration region 3A and is shallower than the high impurity concentration region 3A. × 10 ¹⁸ / cm ³ low impurity concentration region 3B, while N-type source region 4
Is composed of only the high impurity concentration region 4A having an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ formed on both sides of the N-type drain region 3, so that the LDD structure is
It can be limited to the mold drain region 3 only. Therefore, LD
By limiting the region where the D structure is formed, an increase in the area occupied by the semiconductor substrate can be prevented.

Second Embodiment FIG. 7 is a plan view showing a configuration of a MIS type semiconductor device according to a second embodiment of the present invention, FIG. 8 is a sectional view taken along the line CC of FIG. 7, and FIG. 7 is a sectional view taken along line D-D, and FIG.
12 (a) to 12 (c) to FIGS. 12 (g) and 12 (h) are process diagrams showing a method of manufacturing the same MIS type semiconductor device in the order of processes. The configuration of the MIS type semiconductor device of this example is significantly different from the configuration of the first embodiment described above in that the etching damage during the formation of the gate oxide film is suppressed. In the MIS type semiconductor device of this example, as shown in FIGS. 7 to 9, the end side annular gate conductive layer 27 has a curved outer side surface, as is apparent from comparison with the first embodiment of FIGS. On the inner side surface of the gate conductive layer 27, a first sidewall insulating film 28 made of a silicon nitride film is formed so as to cover the low impurity concentration region 3B of the N-type drain region 3, A second sidewall insulating film 29 made of a silicon oxide film is formed on an outer side surface of the gate conductive layer 27 so as to cover an end of the N-type source region 4. Other than this, it is substantially the same as the first embodiment described above.
Therefore, in FIG. 7 to FIG. 9, the same parts as those in FIG. 1 to FIG.

Next, FIGS. 10A to 10C to FIG.
With reference to (g) and (h), a method of manufacturing the MIS semiconductor device of this example will be described in the order of steps. First, FIG.
As shown in FIG. 1A, for example, a P-type silicon substrate 1 is used, and a well-known LOCOS method is used.
Is selectively formed, a P-type impurity such as boron is ion-implanted into the substrate 1 to form a P-type well region 2.
Next, a gate oxide film 5 having a thickness of 5 to 10 nm is formed on the surface of the P-type well region 2 by a thermal oxidation method.
After a polycrystalline silicon film 31 having a thickness of 100 to 300 nm is formed on the entire surface by a lithography method, the polycrystalline silicon film 31 at a position where a drain region is to be formed is selectively removed by a lithography method to have a diameter of 0.5. An opening 32 of ~ 2.0 μm is formed.

Next, after the gate oxide film 5 in the opening 32 is removed, N-type impurities such as phosphorus and arsenic are introduced into the P-type well region 2 from the opening 32 as shown in FIG. By ion implantation, the impurity concentration is 1 × 10 ¹⁷ to 1 × 10
A low impurity concentration region 3B of ¹⁸ / cm ³ is formed. This low impurity concentration region 3B constitutes a part of the drain region and becomes an LDD region. Next, a silicon nitride film 33 having a thickness of 100 to 200 nm is formed on the entire surface by the CVD method.

Next, as shown in FIG. 10C, the silicon nitride film 33 is etched to remove unnecessary portions, and is left only in the openings 32. Next, as shown in FIG. 11D, the polycrystalline silicon film 31 is etched back and patterned to form an endless annular ring having a width of about 0.1 μm on the side surface of the silicon nitride film 33 in the opening 32. A gate conductive layer 27 is formed. The outer side surface of the gate conductive layer 27 is formed in a curved shape.

Next, as shown in FIG. 11E, the silicon nitride film 33 is etched back and patterned, so that the width is substantially reduced so as to cover the low impurity concentration region 3B on the inner side surface of the gate conductive layer 27. A first sidewall insulating film 28 of 0.1 μm is formed. In forming the first sidewall insulating film 28, the etching is performed under the condition that the selectivity between the silicon nitride film 33 and the silicon oxide film constituting the element isolation insulating film 10 is about 50: 1 or more. Then, only the silicon nitride film 33 is selectively removed.

Next, N-type impurities such as phosphorus and arsenic are ion-implanted into the P-type well region 2 using the gate conductive layer 27 and the first sidewall insulating film 28 as a mask, and the inside of the gate conductive layer 27 is ion-implanted. At a substantially central position of the low impurity concentration region 3B at the position where the drain region is to be formed, an impurity concentration deeper than the low impurity concentration region 3B is 1 × 10 ¹⁹ to 1 × 1.
A high impurity concentration region 3A of 0 ²⁰ / cm ³ is formed. At the same time, a high impurity concentration region 3A having the same impurity concentration as described above is formed at a position outside the gate conductive layer 27 where the source region is to be formed.

As described above, inside the gate conductive layer 27, the high impurity concentration region 3A and the high impurity concentration region 3A are formed.
An N-type drain region 3 formed adjacent to the periphery of A and formed of a low impurity concentration region 3B shallower than the high impurity concentration region 3A is formed. Outside the gate conductive layer 6, an N-type source region 4 composed only of the high impurity concentration region 4A formed on both sides of the N-type drain region 3 is formed. Therefore, the LDD structure is formed limited to only N type drain region 3. Next, the substrate 1 is exposed to an inert atmosphere such as nitrogen,
RTA treatment for 10 to 60 seconds at
The mold drain region 3 and the source region 4 are activated.

Next, as shown in FIG.
A silicon oxide film 34 having a thickness of 100 to 400 nm is formed on the entire surface by the method. Next, as shown in FIG. 12G, the second sidewall insulating film 29 having a width of about 0.1 μm is formed on the outer side surface of the gate conductive layer 27 by etching back and patterning the silicon oxide film 34. Form. In forming the second side wall insulating film 29, the selectivity between the silicon oxide film 34 and the silicon nitride film forming the first side wall insulating film 28 is about 5
Only the silicon oxide film 34 is selectively removed under the etching condition of 0: 1 or more. At this time, the second sidewall insulating film 29 is formed so as to expose the upper portion of the gate conductive layer 27.

As described above, when forming the second sidewall insulating film 29, the silicon oxide film 34 is formed in advance on the entire surface, and then the silicon oxide film 34 is etched back and patterned. However, there is a possibility that etching damage may be caused to the substrate 1 during the etch back. Therefore, if a gate oxide film, which is an important factor determining the characteristics of the transistor, is formed thereafter, the gate oxide film may not be able to obtain desired characteristics due to the influence of etching damage. For example, defects such as a decrease in carrier mobility are caused, and characteristics are easily deteriorated. In this regard, according to the configuration of this example, since the gate oxide film 5 is formed in advance in the step of FIG. Therefore, the characteristics can be prevented from deteriorating, and the effect of significantly improving the yield can be obtained.

Next, a silicide layer 11 is formed on each of the surfaces of the N-type drain region 3, the source region 4, and the gate conductive layer 27 in order to reduce the contact resistance when each electrode is led out. In forming the silicide layer 11, a high melting point metal layer such as cobalt, titanium, or molybdenum is formed on the surface of each region in advance, and then heat treatment is performed to react with the silicon film.

Next, as shown in FIG.
After a first interlayer insulating film 12 made of a silicon nitride film or the like and a second interlayer insulating film 13 made of a silicon oxide film or the like are formed on the entire surface by the method, the first and second interlayer insulating films 12 are formed.
13, the surface of the N-type drain region 3 and the source region 4
Contact holes 14 are formed in each case. FIG.
As shown in (1), after a contact hole 19 is formed around the gate conductive layer 6 of the first and second interlayer insulating films 12 and 13, a gate conductor 20 such as polycrystalline silicon is formed in the contact hole 19. . Next, the gate conductor 2
A contact hole 14 is formed on the surface of the "0". continue,
After a plug conductor 15 such as tungsten is buried in each contact hole 14, each plug conductor 15 is formed.
By forming the drain electrode 16, the source electrode 17, and the gate electrode 18 through the MIS type, the MIS type semiconductor device of this example is completed.

As described above, according to the structure of this embodiment, substantially the same effects as those described in the first embodiment can be obtained. In addition, according to the configuration of this example, the yield can be improved because the gate oxide film is not damaged by etching when forming the sidewall insulating film.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there may be changes in the design without departing from the gist of the present invention. Is also included in the present invention. For example, the gate oxide film is not limited to an oxide film (Oxide Film), but may be a nitride film (Ni oxide film).
tride film) or a double film structure of an oxide film and a nitride film. That is, as long as the transistor is a MIS transistor, the transistor is not limited to a MOS transistor, but may be a MNS (Me
tal Nitride Semiconductor (type) transistor, or MNOS (Metal Nitride Oxide Semico)
nductor) type transistors.

The conductivity type of each semiconductor region can be reversed between P type and N type. That is, the present invention can be applied not only to the N-channel type but also to a P-channel type MIS transistor. Further, the present invention is not limited to the N-channel type or the P-type channel type, and a C (Complementary) MI
The invention can be applied to an S-type transistor. The interlayer insulating film is not limited to a silicon oxide film and a silicon nitride film, but may be a BSG (Boro-Silicate Glass) film, a PSG (Phos
pho-Silicate Glass) film, BPSG (Boro-Phospho-Sili)
Other insulating films such as a (cate Glass) film can be used. Further, the impurity concentration of each semiconductor region, the thickness of each insulating film and conductive film, the size of the opening, the heat treatment conditions, and the like are merely examples, and can be changed depending on the application, purpose, and the like.

[0053]

As described above, the MIS of the present invention is
According to the semiconductor device and the method of manufacturing the same, the drain region and the source region of the second conductivity type are selectively formed in the semiconductor region of the first conductivity type, and the drain region of the second conductivity type is formed of a high impurity concentration region. And a low impurity concentration region formed adjacent to the periphery of the high impurity concentration region and shallower than the high impurity concentration region, while the second conductivity type source region is formed on both sides of the second conductivity type drain region. Since the LDD structure is constituted only by the formed high impurity concentration region, the LDD structure can be limited to only the second conductivity type drain region. Therefore, it is possible to prevent the area occupied by the semiconductor substrate from increasing by limiting the formation region of the LDD structure.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a configuration of a MIS type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a sectional view taken along the line BB of FIG. 1;

FIG. 4 is a process chart showing a method for manufacturing the MIS type semiconductor device in the order of steps.

FIG. 5 is a process chart showing a method of manufacturing the MIS semiconductor device in the order of steps.

FIG. 6 is a process chart showing a method for manufacturing the MIS type semiconductor device in the order of steps.

FIG. 7 is a plan view schematically showing a configuration of a MIS type semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a sectional view taken along the line CC of FIG. 7;

9 is a cross-sectional view taken along the line DD in FIG. 7;

FIG. 10 is a process chart showing a method of manufacturing the MIS type semiconductor device in the order of steps.

FIG. 11 is a process chart showing a method for manufacturing the MIS type semiconductor device in the order of steps.

FIG. 12 is a process chart showing a method of manufacturing the MIS type semiconductor device in the order of steps.

FIG. 13 is a process chart showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 14 is a process chart showing a conventional method for manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 2 P-type well 3 N-type drain region 3 A N-type drain high impurity concentration region (N ⁺ region) 3 B N-type drain low impurity concentration region (N ⁻ region) 4 N-type source region 4 A N-type source height Impurity concentration region (N ⁺ region) 5 Gate oxide film 6, 27 Gate conductive layer 7, 28 First sidewall insulating film (silicon nitride film) 8, 29 Second sidewall insulating film (Silicon oxide film) 10 Element isolation Insulating film 11 Silicide layer 12 First interlayer insulating film 13 Second interlayer insulating film 14, 19, 21 Contact hole 15 Plug conductor 16 Drain electrode 17 Source electrode 18 Gate electrode 20 Gate conductor 23, 34 Silicon oxide film 24, 32 Openings 25, 31 Polycrystalline silicon film 26, 33 Silicon nitride film

Claims (12)

[Claims] A first conductive type semiconductor region selectively provided in the first conductive type semiconductor region;
A second conductivity type semiconductor region and a second second conductivity type semiconductor region are formed, and an insulating gate is formed between the first and second second conductivity type semiconductor regions. The first second conductivity type semiconductor region comprises a high impurity concentration region and a low impurity concentration region formed adjacent to the periphery of the high impurity concentration region and shallower than the high impurity concentration region. The second second conductivity type semiconductor region includes only high impurity concentration regions formed on both sides of the first second conductivity type semiconductor region, and the insulating gate is formed via a gate insulating film. An MIS type semiconductor device comprising an endless annular conductive layer. 2. A first sidewall insulating film is formed on an inner side surface of the conductive layer of the insulating gate so as to cover the low impurity concentration region of the first second conductive semiconductor region, 2. The M according to claim 1, wherein a second sidewall insulating film is formed on an outer side surface of the conductive layer so as to cover an end of the second second conductivity type semiconductor region.
IS type semiconductor device. 3. The MIS semiconductor device according to claim 1, wherein said conductive layer is made of polycrystalline silicon. 4. The MIS semiconductor device according to claim 2, wherein said first sidewall insulating film is made of a silicon nitride film. 5. The semiconductor device according to claim 2, wherein the second sidewall insulating film is made of a silicon oxide film.
The MIS type semiconductor device as described in the above. 6. The MIS semiconductor device according to claim 1, wherein said first second conductivity type semiconductor region is a drain region. 7. The method according to claim 1, wherein the first conductive type semiconductor region is selectively provided in the first conductive type semiconductor region.
Of a MIS type semiconductor device in which a second conductive type semiconductor region and a second second conductive type semiconductor region are formed, and an insulating gate is formed between the first and second second conductive type semiconductor regions. A method of forming a first conductive type semiconductor region by forming a conductive layer on the first conductive type semiconductor region via a gate insulating film, and then patterning the conductive layer into an endless ring. An opening forming step of forming an opening at a position; introducing a second conductivity type impurity into the first conductivity type semiconductor region from the opening to form a part of the first second conductivity type semiconductor region; Forming a low impurity concentration region to form a low impurity concentration region to be formed; and forming a first sidewall insulating film on the inner side surface of the conductive layer so as to cover the low impurity concentration region. And outside the conductive layer Forming a second sidewall insulating film on a side surface; forming a second sidewall insulating film on the side surface; using the first and second sidewall insulating films and the conductive layer as a mask in the first conductivity type semiconductor region; By introducing a two-conductivity-type impurity to form a high-impurity-concentration region that is part of the first second-conductivity-type semiconductor region deeper than the low-impurity-concentration region, The second conductive type semiconductor region on both sides of the second conductive type semiconductor region.
Forming a high-impurity-concentration region forming the second-conductivity-type semiconductor region. 8. The method according to claim 1, wherein the first conductive type semiconductor region is selectively provided in the first conductive type semiconductor region.
Of a MIS type semiconductor device in which a second conductive type semiconductor region and a second second conductive type semiconductor region are formed, and an insulating gate is formed between the first and second second conductive type semiconductor regions. A method of forming a first conductive type semiconductor region by selectively removing the conductive layer after forming a conductive layer on the first conductive type semiconductor region via a gate insulating film. An opening forming step of forming an opening at a position; introducing a second conductivity type impurity into the first conductivity type semiconductor region from the opening to form a part of the first second conductivity type semiconductor region; A low impurity concentration region forming step of forming a low impurity concentration region to be formed; and after patterning the conductive layer in an endless annular shape, forming a first sidewall insulating film on the inner side surface of the conductive layer so as to cover the low impurity concentration region. First sidewall insulation to be formed Forming a second conductivity type impurity in the first conductivity type semiconductor region by using the first sidewall insulating film and the conductive layer as a mask, and forming the lower impurity concentration region deeper than the low impurity concentration region. At the same time as forming a high impurity concentration region that constitutes a part of the first second conductivity type semiconductor region, the second second conductivity type semiconductor region is formed on both sides of the first second conductivity type semiconductor region. Forming a high impurity concentration region to form a high impurity concentration region, and forming a second sidewall insulating film on an outer side surface of the conductive layer so as to cover an end of the second second conductivity type semiconductor region. 2. A method for manufacturing a MIS type semiconductor device, comprising: a step of forming two side wall insulating films. 9. After the high impurity concentration region forming step,
9. The method of manufacturing a MIS semiconductor device according to claim 7, further comprising a heat treatment step of performing a heat treatment for activating the low impurity concentration region and the high impurity concentration region. 10. The MIS according to claim 7, wherein the conductive layer is made of polycrystalline silicon.
Of manufacturing a semiconductor device. 11. The method for manufacturing a MIS semiconductor device according to claim 7, wherein a silicon nitride film is used as said first sidewall insulating film. 12. The method for manufacturing a MIS semiconductor device according to claim 7, wherein a silicon oxide film is used as said second sidewall insulating film.