TW383408B - Forming method for gate-drain overlapped structure - Google Patents

Abstract

A kind of manufacturing method for gate-drain overlapped transistor structure which is to form field oxide, the first conductive well area, the second conductive well area, gate and gate oxide on the semiconductor substrate; then, forming the first dielectric layer on the surface of gate and gate oxide to recover the damaged gate oxide; forming respectively the LDD area in said the first conductive well area and second conductive well area; then, forming a plurality of amorphous silicon sidewall on both sides of the said gates; After forming densely doped source/drain area and gates, the LPD oxide sidewall on both sides of amorphous silicon sidewall; finally, metal silicide on the uncovered source/drain by the liquid deposited silicon oxide sidewall and on the surfaces of gate and amorphous silicon sidewall.

Description

V. Description of the Invention (/) Technical Field: Gate-a kind of integrated circuit feeding method, especially related to the manufacturing method of the gate / non-pole knife weight® transistor structure. Background of the Invention: The development trend of the product industry is towards the accounting of circuits that have greatly improved circuits. Butterfly interest_ rigid effect transistor, because of the extremely small size, high packaging density, power consumption A is a typical manufacturing method, is on a single-sided single-crystal semiconductor substrate pattern idler pattern, with a thin layer sandwiched between the two A thin layer of leisurely secrets. This gate structure can be used as a diffusion barrier layer to form a self-aligned source / inverter region in the substrate on both sides of the pole. Under the gate, from the county of the source == Xiao Zhaoshun Zhao_Ministry of Economy and Standards Bureau printed by the cooperative> On a 2-conductor substrate, the size of the field effect transistor (FET) should be reduced and Improving packaging density mainly depends on precise semiconductor technology, such as high-resolution lithography technology and anisotropic electrical engraving. For example, the current industry makes Linguan transistor _> Guan Changlin is less than one-half micron (0.5 micron), but if you want to increase the packaging density and enhance the function of components, you must "-face small The device's property, and even the clock domain, the channel length of the field-effect transistor (FE τ) must be reduced to less than one-fourth of a micron (actually less than 0.25 microns). However, when the component and channel length continue to shrink Γ paper and silver Standards apply to Chinese National Standard (CNS) A4 specifications (210X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 ____ 5. Description of the invention (〇?) Field-effect transistor (FET) will produce many unsatisfactory Electronic characteristics are generally called short channel effects. The smaller the component, the more severe these short channel effects are, because the band gap and the built-in potential of the junction are the intrinsic constants of the crystalline material. When the body circuit is started, the result of the electric field distribution in the channel area brings about bad short-channel effects, which causes many problems. For example, the electrons emitted from the drain electrode will obtain sufficient energy and enter the gate oxide layer. And accumulate charges in this layer, shifting the threshold voltage, unfortunately, when the product is used (in an electric field), this hot carrier effect will reduce the function of the device. Another bad effect It is a latch-up effect, because the distance between the η-well and the P-well is shortened, which causes problems in the isolation between them and seriously affects the performance of the field-effect transistor. In order to reduce the short-channel effect, the semiconductor industry in general The method is to add a double-diffused drain region (DDD) or a lightly doped drain (LDD) when fabricating the FET structure. In this DDD or LDD field-effect transistor (FET) structure, the drain of the gate is next to the gate The low impurity concentration in the region can change the electric field of the drain to reduce or eliminate the effects of hot electrons and latch-up. Another problem of traditional field transistor (FET) is that it needs to develop a gate pattern. When the polycrystalline silicon layer 3 is etched by the plasma, it will also cause damage to the gate oxide layer 1, which will affect the subsequent levels and the gate-drain overlapped device (GOLD) formed by the traditional method. Quality and good Rate (please refer to &s; COI1 Processing For the VLSI Era: Volume 3, Chapter 9, pp. 624-625, (1995) ") 〇 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (.Please read the notes on the back before filling this page)

A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (,) The present invention proposes a gate / drain partially overlapping transistor structure formed using silicon dioxide assisted by liquid phase deposition (LPD) The new process can improve the shortcomings of the above-mentioned conventional techniques. Liquid phase deposition is a newly developed technology that can selectively deposit plasticity silicon dioxide in a low temperature aqueous solution to achieve the effect of simplifying the process (see " A Selective Si02 Film Formation Technology Using Liquid Phase Deposition for Fully Planarized Multilevel Interconnections " J. Electrochem. Soc., V〇l. 140, No. 8, pp. 2410-2414, August 1993) Summary of the invention: The main object of the present invention is to provide a gate / pole overlap The manufacturing method of the transistor structure, with the aid of liquid-phase deposition of silicon dioxide (LpDoxide), makes the process: greatly simplified, and reduces the complexity and process variables of the process, which can effectively reduce production time and reduce production costs. A secondary object of the present invention is to provide a method for manufacturing a gate / drain partially overlapped transistor structure. The gate / drain partially overlapped (GOLD) structure formed by the manufacturing method is applied to a short-channel element (Short ch_d, It can effectively reduce the hot carrier effect and the latch-up effect. Another object of the present invention is to provide a method for manufacturing a gate / drain partially overlapped transistor structure. By using the gate / drain partially overlapped (GOLD) structure formed by the manufacturing method, Applied to short channel components (Short Channel, can effectively increase the size of the drive current. The present invention uses the following process methods to achieve the above purpose: (Please read the precautions on the back before filling in this page.) Order

Fifth invention description (A7 B7 Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs. Firstly define and form the N-well area and the p-well area on the silicon substrate, then form the field oxide layer for isolation, and the silicon outside the field oxide layer. A gate oxide layer and a polycrystalline silicon layer are continuously formed on the substrate surface, and then a pattern of the polycrystalline silicon gate is developed by using lithography and etching techniques, and then a first dielectric layer is formed on the surface of the gate and the gate oxide layer. Repair the damaged gate oxide layer. Next, a photoresist pattern is formed to protect the N-well area, and then N-type heterostom implantation is performed to form an N_-type lightly doped drain (LDD). A light is formed again A resist pattern is used to protect the P-well region, and then P-type ion implantation is performed to form a p_-type lightly doped drain (LDD). The next step is to form amorphous silicon sidewalls on both sides of the gate to It is used as a shield when the source / drain is heavily doped with ion implantation. Next, ion implantation is performed to form an N + -type doped source / electrode region and a gate electrode. Then, a liquid phase deposition (LpD) method is used to deposit A layer of silicon dioxide (Si〇2), and use! ^ ≫ 〇-8102 layer as a shield, p + Ion implantation to form P + -type concentrated dopant / electrode regions and gates. The next steps are one of the key points of the present invention: 'Anisotropic etching is used to etch the LPD-Si02 layer to form LPD- SiO,] wall, can ensure the electrical property of the gate / drain electrode of the present invention partially overlapping the transistor structure. Finally, a metal silicide layer is formed on the source / non-electrode and the gate which are not covered by the liquid-phase deposition and oxidation side wall. Electrode and amorphous silicon sidewall sub-surface, the gate / drain electrode of the present invention partially overlaps the transistor structure and is completed. Figure Description: Figure 1 is a gate oxide layer which is damaged by plasma etching using conventional techniques. Schematic diagram of the section. This paper standard is applicable to the national standard of the middle stack. (CNS) M specification (21〇 > < 297 public plague) (Please read the precautions on the back before filling this page) ---.---- L ..--_ _______ I 、、; ------ 、 1τ ------------------ 1- II --- · V. Description of the invention ('Figure The second is the schematic diagram of the implementation of the present invention—the first layer—the dielectric layer bridging the gate oxide layer that was damaged by electropolishing. Figure 5 is a schematic cross-sectional view of a lightly doped region (LDD). Figure 5 is a schematic cross-sectional view of a thin amorphous dream layer formed on the entire semi-conductive surface of the substrate according to an embodiment of the present invention. The cross-section diagrams of the sidewalls on the two sides of the idle pole are shown in the diagrams. Figures 7 to 10 are schematic diagrams of the cross-sections of the well regions and p-well regions in the embodiment of the present invention after the formation of a thick doped region and an LPD-SiO2 layer. An embodiment of the present invention is a schematic cross-sectional view of an LPD_SiO2 sidewall formed on both sides of an amorphous silicon sidewall. FIG. 12 is a schematic cross-sectional view of a gate / drain partially overlapped structure formed according to an embodiment of the present invention. {Please read the notes on the back before filling this page) Order the printed number description of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs: 1-gate oxide layer 21-semiconductor substrate 25-P well area 29-gate oxygen layer 33-first dielectric layer 37-ion beam 41-photoresist pattern 45-lightly doped drain (LDD) 49-photoresist pattern 3-multi-crystal wheat gate 23-N well region 27-field oxide layer_ 31 -Complex crystal layer 35-Photoresist pattern, 39-Lightly doped drain (LDD) 43-Ion beam 47-Amorphous silicon layer 51-Ion beam 01.

,--1 I s--II This paper size applies to the Chinese national standard (CNS > A4 size (210X297mm) A7 ----: ----- .. B7 V. Description of the invention (— 一 — ~ 一— ——- 53-Concentrated Doping Source / Drain 55_LpD_Si〇2 Layer 57-Ion Beam 59 · Concentrated Doping Source / Drain 61-Metal Silicide Layer Detailed Description of the Invention: This invention is a description-a kind of gate / The method of partially overlapping the drain electrodes, especially the complementary metal-oxide-semiconductor field-effect transistor (CMOS) as a specific embodiment of the present invention, those skilled in semiconductor technology should understand that, in the ion implantation process, appropriate conversion The type of doped impurities, that is, the manufacturing method of the present invention can be used as the manufacturing technology of P-channel or N-channel metal-oxide half field-effect transistor....... Please refer to FIG. 2, The starting material of the present invention is a single crystal semiconductor dream substrate 21. First, N well regions 23 and 1 > well regions 25 are defined and formed on the silicon substrate 21, and then a field oxide layer 27 for isolation is formed. On the surface of the silicon substrate 21 other than 27, a gate oxide layer 29 and a polycrystalline silicon layer 31 are continuously formed. After the pattern of the polycrystalline silicon gate is developed by the etching technology, a first dielectric layer 33 is formed on the surface of the gate and the oxide layer of the gate to repair the damaged oxide layer. The central standard of the Ministry of Economic Affairs. The N-well area printed by the company uses ion implantation to implant n-type impurities. Generally, it implants phosphorus ions (P31). The ion implantation energy is between 30 and 100 keV. The dose is between 5E12 and 1.5E13 ions / cm2, and then the drive-in action is performed. The p-well area is also implanted with P-type impurities by ion implantation. Generally, It is implanted with boron (Bn) ions, the ion implantation energy is between 30 and 100 keV, and the ion implantation dose (dose) is between 1E13 and 3E13 ions / cm2, and the impurities are driven into the paper. The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The A7 printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs _—— _ _B7____ 5. The operation of the invention (^ 7). The field oxide layer 27 is usually Is formed by thermally oxidizing the surface of the semiconductor silicon substrate 21 Its thickness is between 3000 and 6000 angstroms. The gate oxide layer 29 is also formed by a thermal oxidation method, and its thickness is between 80 and 200 angstroms. The polycrystalline silicon The layer 31 is usually formed by using a low pressure chemical vapor deposition (lpcvd) method of synchronous doped phosphor doped. The reaction gas is a mixed gas of 15% PH3 + 85% SfflU and 5% PH3 + 95% N2. The temperature is about 550 ° C and its thickness is between 1000 and 3000 Angstroms. The polycrystalline silicon layer 31 can be etched by plasma etching such as magnetic field enhanced active ion plasma etching (MERIE), electron cyclotron resonance plasma etching (eCR), or traditional active ion plasma etching (RIE). Technology, in the field of submicron integrated circuits in the Hsinchu Science Park, is usually etched using magnetic field enhanced active ion plasma etching technology (MERIE), and the reaction gas is a mixed gas of Ck, SF6 and HBr. The first dielectric layer is usually a silicon oxynitride formed under a thermal oxidation environment at a temperature between 850 and 1000 ° C, and has a thickness of about 65 to 100 angstroms. V Please refer to FIG. 3. Using photolithography technology, a first photoresist pattern 35 is formed to protect the N-well region 23, and then an N-type ion implantation 37 is performed at an implantation concentration of 1E13 to 1E14cm-2. At this time, phosphorus (P31) ions having an energy between 40 and 50 KeV to form an N · type lightly doped drain (LDD) 39. The first photoresist pattern 35 is then removed. Referring to FIG. 4, a second photoresist pattern 41 is formed by using a photolithography technique to protect the P-well region 25, and then a P-type implantation implantation 43 is performed. The implantation concentration used is 1E13 to 1E14cm In the meantime, the boron paper size between 30 and 40 KeV applies to Chinese national standards (CNS > A4 size (210X297 mm) (Please read the notes on the back before filling out this page) t Central Bureau of Standards, Ministry of Economic Affairs Negative consumption t-cooperative prints A7 1-... Β 7 V. Inventive g (/) one ~ ~~~-one-one (B12) or BF2 ions to form ρ-type lightly doped drain (LDD) 45. Then, the first photoresist pattern 41 is removed. Refer to FIG. 5 to form a two-layer thinner amorphous layer. The entire semi-learning difficulty is painful to the surface 21. The amorphous second 47 is usually obtained by using _ ' It is formed by slurry enhanced vapor deposition (PECVD) or chemical vapor deposition (CVD) at a reaction temperature between 300 and 550 ° C, and its thickness is between 2000 and 500 angstroms. Ji Referring to FIG. 6, by using an anisotropic etch-back (Etchbaek) technology, the amorphous second layer 47 is etched to form an amorphous silicon sidewall 47A on both sides of the gate as a source / inverter. Protective cover for doped ion implantation. ', Read FIG. 7 and use lithography technology to form a third photoresist pattern 49 to protect the N-well region 23 and then perform N + ion implantation 51. Phosphorus (P31) ions with a concentration between 1E15 and 1E16cm · 2 and an energy between 60 and 80KeV are formed to form an N + -type concentrated dopant source / drain region 53 and a gate electrode. Eight 'Using a liquid phase deposition (LPD) method, a layer of silicon dioxide (SiCy layer 55, with a thickness of about looo to about 3000 angstroms) is deposited. The silicon dioxide is described below as LPD-Si02' Then, the third photoresist pattern 49 is removed. The reaction formula of the liquid phase deposition silicon oxide (LPD-Si02) is as follows: H2SiF6 + 2H20〇6HF Hr Si02sl ·-~ (l), the reactants are H2SiF6 and The reaction formula of water is a reversible reaction. In order to generate SiO2 deposits, boric acid (H3B03) or aluminum (A1) which can easily react with hydrogen fluoride (hf) can be used. The reaction formula is described as follows: H3B〇3 + 4HF〇BF '+ M30 ++ 2H20- (2) 2A1 + 12HF〇6H3AlF6 + 3H2-(3) The standard of this paper is based on the standard (CNS) A4 specification (2 10X297 mm) (.Please read the notes on the back before filling this page)

A7 B7 5. Description of the invention (cadaver) / Once HF reacts with H3B03 or A1, the reaction in the formula is continued from left to right to re-deposit Si02, and the deposit Si02 Does not form on photoresist. xj 青 Refer to Fig. 9. Using LPD-Si02 layer 55 as a shield, perform P + ion implantation 57. The implantation concentration used is between 15 and 1E16cm-2, and the energy is between boron (B12 and B12). ) Or BF2 ions to form a p + -type doped source / drain region 59 and a gate. Please refer to FIG. 10. Using the aforementioned liquid phase deposition (LPD) method, a layer of LPD-SiOj 55 having a thickness of about 1000 to 3000 angstroms is deposited on the surface of the substrate in the N-well zone. Please refer to FIG. 11. This step is one of the key points of the present invention. The anisotropic etching technique is used to etch the LPD-Si02 layer 55 to form U ^ D-SiC ^ sidewalls 55A. The surface is about 10,000 angstroms, which can ensure the electrical property of the gate / drain partially overlapping transistor structure of the present invention. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Please refer to Figure 12 to form a metal silicide layer 61 by self-aligned silicide. On the surface of the source / inverter 53 and the gate 31 and the amorphous silicon sidewall 47A that are not covered by the liquid-phase deposition silicon oxide sidewall 55A, at the same time in a hot environment, the impurity ions in the drain and source regions may cause The diffusion effect diffuses to the middle to form a shallow channel junction in the drain / source region. The gate / inverter partially overlapped transistor structure of the present invention is completed in 焉. The silicide layer 61 is usually a low-resistance titanium silicide (TiSi2) generated by a self-aligned silicidation method (saHcide) to reduce the contact resistance between metal and transistors in the future. It can also be cobalt silicide or silicide. platinum. The rapid heat treatment is performed at a temperature between 850 and 900 T: for several tens of seconds. This paper size uses Chinese National Standard (CNS) M specifications (21 × '297 mm, 5) Printed by the Consumers' Cooperative of the China Bureau of Standards, A7 B7, Invention Description (/ θ) The present invention is described through specific examples. Illustrating the principles and spirit of the present invention, it should be understood that the present invention is not limited to the specific embodiments disclosed. 'Thus' the malting of any relevant details made under the principles and scope of the present invention' shall be deemed to be the present invention .A further embodiment of Ming. This paper size applies the Chinese national standard (⑽) Cong Mi (2 offering 297 public love) (Please read the precautions on the back before filling this page; >

Claims (1)

Patent application scope I. A method for forming a gate Λ and a pole overlapping structure, including: The steps include the following steps a. Provide a semiconductor substrate, and form a field oxygen on the substrate and the first-conductive thunder meaning # 1: conductive and substrate Gates and layers; ~ The first dielectric layer is formed on the surface of the well area, the multiple gates and the gate oxide layer to repair and damage the gate gasification layer. Within the region, · • 丄 forms a layer of amorphous silicon on the entire surface of the semiconductor substrate; e. Forms a plurality of amorphous silicon sidewalls on both sides of the free electrode; to form a concentrated 搀 f. In the first-conducting type Ion implantation in the well area, the source / drain area and the gate; g. Deposition-layer liquid Shen Weiqing (LPDQxide), on the surface of the substrate of an electrical type well area; Ionization implanted source / non-electrode area and gate electrode of the two conductive type; printed by the consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs I. Deposition-layer liquid Shen Weiqing, on the surface of the substrate of the second conductive type well area &Quot; J. Formation of a plurality of liquid-phase deposition oxidation complements Xi sidewall spacers on both sides of the spar;. K a gold soil exit thereof, in an oxygen-cut green liquid deposition source / drain and the gate sidewall spacers and the surface coverage of the amorphous silicon sidewall spacers. 6. Scope of patent application A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Lai and the second conductivity type energy well area are opposite conductivity types. " 3. Such as the scope of patent application! The method for forming a partially overlapped structure according to the item, wherein the thickness of the first dielectric layer oxymtnde is between 65 and 100 angstroms. 4_ The method for forming a partially overlapped structure of a gate electrode as described in the first patent application: > page, wherein the thickness of the amorphous silicon layer is between 200 and 5 Angstroms. 5'As claimed in the application of the full-length Cheron / Miscellaneous overlapping structure method, wherein the thickness of the liquid-phase-deposited oxide film (LpDoxide) layer is between 1000 and 3000 angstroms. 6. As described in the application of the special fiber 15 method described in the first part of the shape / record part of the overlapping structure 'method, wherein the metal precious metal is selected from the group consisting of Shixi Huayin (Ding Jiao), Shixi Cobalt, and silicide platinum group . 7. The method for forming a partially overlapped structure of a gate electrode as described in the application patent No. 6, wherein the metal silicide is formed by a self-aligned silicide method. 8. If the application is to revise the method of JUL7 / Long / Secret overlapping structure, wherein the process temperature of the self-aligned salicide method is between 850 and 90 (TC). A gate / and pole partially overlapping structure includes: a gate oxide layer on a surface of a semiconductor substrate; (Please read the precautions on the back before filling this page) W, 、 1T -P Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A8 C8 —-------- -D8' Application for patents ^ ~ '' ~ 一 ~ 一-一 ---- A polycrystalline hard layer is on the surface of the central part of the chemical layer, and the polycrystalline stone layer and the gate oxide layer form a gate electrode; the second dielectric layer is on the non-polycrystalline hard layer The surface of the gate oxide layer covered by layers and both sides of the polycrystalline silicon layer;-two source / drain regions in the semiconductor substrate on both sides of the gate; two amorphous silicon sidewalls on both sides of the gate; two The liquid-phase-deposited oxidized silicon oxide sidewalls are on both sides of the amorphous hair-shaped sidewalls; and the 'metal silicide layer is formed on the source / non-polar and gate and amorphous layers that are not covered by the liquid-phase-deposited silicon oxide sidewalls. Silicon sidewall surface. The gate / drain partially overlapped structure as described in item 9 of the scope of the patent application, wherein the source / drain region includes two parts, a lightly doped region and a thickly doped region, to form an LDD structure. 11. The gate / drain partial overlapping structure as described in item 9 of the scope of the patent application, wherein the dielectric layer is oxidized nitride (OXynitride) and its thickness is between 65 and 100 Angstroms. . 12. The gate / electrode partially overlapping structure according to item 9 of the scope of the patent application, wherein the thickness of the amorphous silicon sidewall is between 200 and 500 angstroms. 1.3. The gate / drain partial overlap structure according to item 9 of the scope of the patent application, wherein the thickness of the liquid-phase-deposited silicon oxide (LPD oxide) sidewall is between §00 and 1000 angstroms. 14. The gate / drain partial overlapping structure according to item 9 of the scope of the patent application, wherein the metal silicide is selected from one of the titanium silicide (TiSij, cobalt silicide, and platinum silicide groups. This paper uses China as the standard) Standard (CNS) A4 specification (210X29 * 7mm) (Please read the notes on the back before filling in. This page) AB B8 C8 D8 6. Application scope of patent 15. The gate / drain partial overlap structure described in item 14 of the scope of application for patent, wherein the metal silicide is formed by salicide using self-aligned silicide (16). The gate / inverted partial overlap structure according to item 15 of the application, wherein the process temperature of the self-aligned salicide is between 850 and 900 ° C. (Printed and printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs < Please read the notes on the back before filling this page) This paper uses Chinese National Standard (CNS) A4 (210X297 mm)