A6 304285 ___B6 五、發明説明（） 發明背景： 當場效電晶體元件尺寸愈小時，有效通道（Channel) 變短使電子被源極與汲極間之電場加速而得到超過矽與氧 化層間之能量障礙（一般而言為3.2 ev)，該電子即稱熱 電子。這些熱電子極易跳至閘氧化層，部份熱電子會流失 ，大部份電子會被當初成長閘氧化層之些許缺陷如介面陷 阱（Interface Traps)所捕捉•或是汲極，閛極當接高 電壓時，汲極與通道介面易產生累增崩溃（Avalanch)現 象，使電子極易獲得高能置形成熱電子·當這些熱電子被 氧化層捕捉，將造成元件工作產生不良效應，諸如起始電 壓（Vt)异高，由热電子形成之不必要閘極電流，汲極之 介面崩溃電壓降低，Gm (Transconductance)變小及降低 元件之工做#命等。 一般為了防止熱電子產生，係作一些元件結構改變以 避免於源/汲極與通道之介面形成高電場’如低度摻雜汲 極（Lightly Doped Drain, LDD)結構，如圖 1 所示。藉 由低濃度源./汲極N-與閘極（如圈1之斜線區域所示）或 其與通道間之電場強度得以滅弱，較不易產生熱電子。茲 在此簡述低度摻雜汲極（LDD)結構之製程：首先於P胃矽基 材上形成場效電晶體之閘極（如圖1之斜線區所示）後， 以低濃度雜質離子N -植入形成N- 源/汲極區再以CVD方 法沈積二氧化矽並藉回蝕刻（Etch Back)技術使其於閘 極邊牆處僅殘有該二氧化矽隔離物1 ，再將同一導電型之 高濃度雜質離子N +植入，以使閘極與具有高濃度雜質離子 -3 - 本1氏认尺度通用中a B家怵芈（CNS)甲4说格（210 X 297公贫） -------ΓΙΙ-ιί----------卜裝-1-----訂---- 線 - - · <«·先«讀背面之注意事'?再塡S本頁) 經濟部中夹徉华局工消費合作社印¾ 304285 A6 设濟部中失標箏扃Λ工消貧合作社印製 Β6 五、發明说明（） N*源/汲極相隔離’而不致於汲極周邊產生高電場及防止 通道内電手因獲得高能置形成熱寫子* 惟N -源/汲極區濃度不可太低，否則會形成通道之串 聯高電阻，造成汲極電流降低•然而，N -源/汲極區濃度 亦不可太高’否則不僅達不到防止熱電子產生之目的，且 極易造成流至矽基材之漏電流，形成不必要之功率消耗· 該基材漏電流值大小與濃度之關係可簡述如下：茲以NM 0S為例，當汲極與通道介面空乏區（Depletion Region) 產生如前述之累積崩溃（Avalanch Breakdown)不僅會形 成熱電子且在介面空乏區所產生之電洞會被矽基材之接地 端所收集造成基材漏電流，且N —浪度愈濃者其介面空乏區 之電塲強度愈高’導致電洞產生之數量愈多形成高基材漏 電流•因此在習知低度摻雜汲極結構該N-/P-區濃度必f 在滿足高汲極電流’高热電子抑制力及低基材漏電流等條 件下取得最佳值’也因此使部份電性特性變差· 囡此遂有提出一改良之倒T型低度揍雜汲極結構以解 決上述問題•該倒T型低度揍雜汲極結搆如豳2所示，主 要係該閘極呈一倒T字型且由第一複晶矽22及第二複晶# 24所構成，其中閘極係與N -源/汲極完全重藉上$之 Ν -源/汲極與閘極完全重疊使場效電晶體工作時n-源^^ 極可感應電子降低Ν —源/汲極之阻值，增加汲極電流 句話説，縱使降低Ν -源/汲極濃摩仍可得到原有之汲極 流，且藉該Ν -源/汲極濃度之降低可同時達到提高熱| + 之抑制力及降低基材漏電流等多重功效，而不會如 ~ 4 — 本紙张XJt通用中国國家標準（CNS)甲4 (210 X 297 ) ------ —A6 304285 ___B6 V. Description of the invention () Background of the invention: The smaller the field effect transistor element size, the shorter the effective channel (Channel), so that the electrons are accelerated by the electric field between the source and the drain to get beyond the energy barrier between the silicon and the oxide layer (Generally speaking, 3.2 ev), the electron is called hot electron. These hot electrons can easily jump to the gate oxide layer, some of the hot electrons will be lost, and most of the electrons will be captured by some defects of the original gate oxide layer, such as interface traps. When connected to a high voltage, the interface between the drain and the channel is susceptible to cumulative collapse (Avalanch), which makes it easy for electrons to obtain high energy and form hot electrons. When these hot electrons are captured by the oxide layer, it will cause adverse effects on the operation of the device, such as The starting voltage (Vt) is extremely high, unnecessary gate current formed by hot electrons, the breakdown voltage of the drain interface is reduced, Gm (Transconductance) becomes smaller, and the work life of the device is reduced. Generally, in order to prevent the generation of hot electrons, some device structure changes are made to avoid the formation of a high electric field at the interface between the source / drain and the channel, such as a lightly doped drain (LDD) structure, as shown in FIG. 1. By the low-concentration source./drain N- and gate (as indicated by the slanted area of circle 1) or the electric field strength between it and the channel is weakened, it is less likely to generate hot electrons. Here is a brief description of the process of the low-level doped drain (LDD) structure: first, the gate of the field-effect transistor (as shown by the diagonal line area in FIG. 1) is formed on the P stomach silicon substrate, and then the impurity is of low concentration Ion N-implantation to form the N-source / drain region, then deposit silicon dioxide by CVD method and use the Etch Back technique to make only the silicon dioxide spacer 1 remain at the gate side wall, and then Implanting high concentration impurity ions N + of the same conductivity type so that the gate electrode has high concentration impurity ions -3-Ben 1's recognized standard universal a B family 抵 芈 (CNS) A 4 said grid (210 X 297 Public Poverty) ------- ΓΙΙ-ιί ---------- Bu-Pack-1 ----- Subscribe ---- Line--< «· First« Read the back Attention '? Again on this page) Printed by the Industrial and Consumer Cooperatives of the Ministry of Economic Affairs, China, and China ¾ 304285 A6 Printed by the Ministry of Economic Affairs of the Lost Standard, Printed by the Cooperative Society for Poverty Alleviation B6 V. Description of Invention () N * Source / Drain phase isolation 'does not cause high electric field around the drain and prevent the electric hand in the channel from forming a hot writer due to the high energy setting * However, the concentration of the N-source / drain region should not be too low, otherwise it will form a high series resistance of the channel , Causing the drain current to decrease • However, the concentration of the N-source / drain region should not be too high. Otherwise, it will not only fail to prevent the generation of hot electrons, but also easily cause leakage current flowing to the silicon substrate, resulting in unnecessary power consumption. The relationship between the material leakage current value and the concentration can be briefly described as follows: Here we take NM 0S as an example. When the drain and channel interface depletion region (Depletion Region) produces the above-mentioned cumulative breakdown (Avalanch Breakdown), not only will form hot electrons and in The holes generated in the interface void area will be collected by the grounding end of the silicon substrate to cause substrate leakage current, and the stronger the N-wave is, the higher the electrical strength of the interface void area will result in more holes. More high substrate leakage current is formed. Therefore, in the conventional low-doped drain structure, the concentration of the N- / P-region must be optimized to meet the conditions of high drain current 'high hot electron suppression and low substrate leakage current. The value 'also degrades some electrical properties. Therefore, an improved inverted T-type low-level beat-drain structure has been proposed to solve the above-mentioned problems. The inverted T-type low-level beat-drain structure is as follows. As shown, it is mainly because the gate is in an inverted T shape It is composed of the first polycrystalline silicon 22 and the second polycrystalline # 24, in which the gate and the N-source / drain are completely re-borrowed with the $ N-source / drain and the gate completely overlapping so that the field effect transistor During operation, the n-source ^^ pole can sense electrons to reduce the resistance of the N-source / drain and increase the drain current. In other words, even if the N-source / drain concentration is reduced, the original drain current can still be obtained, and By reducing the concentration of N-source / drain can simultaneously achieve multiple effects such as improving the heat | + suppression and reducing the leakage current of the substrate, but not like ~ 4 — This paper XJt General Chinese National Standard (CNS) A 4 (210 X 297) ------ —
……^ ————.一—..... - ..... 82. Q -------ί — Γ.-----:-------Γ 裝—l·----訂----.線 IJ- - . (請先M讀«·面之注意事項再埔寫本頁) A6 A6 五、發明説明（ i度摻雜汲極結 以下將簡述該倒τ型 於矽基材10上形 氧化以成長閘氧 構般f犧 成第一導 之第一複晶矽22 ，如圖 温氧化 離子植 起始電 Λ濟部中夹«率為Λ工消费含作社印製 ,LT〇)23 及蝕刻低 ，再通道 ，以調整 ，之後進 然後進行 矽22為厚 沈積步驟 於該複晶 可達到選 複晶矽沈 度不夠， 質難以控 較為可行 晶體通道 然後 質離子植 為P—雜質 示。接著 行短時 一選擇 之第二 實質上 妙慕晶 擇性沈 積後再 晶片中 制，而 之製程 區之閘 去除低 入（如 離子） ，形成 化層21， 及低溫氧 3 A所示 層23後將 入，該難 壓及擊穿 間高温驅 性複晶矽 複晶妙2 4 為一磊晶 成長僅能 積之目的 蝕刻而達 心與周邊 選擇性複 •又該第 極，即如 温氧化層 P型井區 以形成N · 介電層隔 本紙ik人度適用中國《家標芈（CNS)甲4规格（210 X 297公铨〉 牲部份電性特性· 低度掺雖汲極結構之製程，首先 電型井區11後，整個晶片進行熱 再依序沈積一含高濃度雜質摻雜 化層（Low Temperature Oxide •接著，進行一閘區光罩經顯影 上述之部份第一複晶矽22曝露出 子和井區11相同皆為第一導電型 電壓（Punch-Through Voltage) 入形成通道區111如圖3 B所示。 沈積以形成一厚度遠較第一複晶 並含高濃度雜質摻雜•該選擇性 成長（Epitaxial Growth)，由 在第一複晶妙22表面進行，因此 •當然，該第二複晶矽亦可藉先 成，惟此時整個晶片之蝕刻均匀 之蝕刻程度差異很大造成製程品 晶矽沈積則無此現象，因此係/ 二複晶矽24實乃係一定義場效電 圖3 C所示。 23及進行一低浪度第二導電裂$ 則為N-雜質離子，而n琅井廣贵 /p-源/汲極，即如 離物25即如圖3 E所示，其哥藉 —5 — -------i — r.------ -------ill·----訂----線 - - (請先聞讀背面之注令？事項再項寫本頁)...... ^ ————. 一 —.....-..... 82. Q ------- ί — Γ .-----: ------- Γ —L · ---- Subscribe ----. Line IJ--. (Please read the notes of «· surface first and then write this page) A6 A6 V. Description of invention (below i-degree doped drain junction The inverse τ type is oxidized on the silicon substrate 10 to grow in a thyristor-like structure f to sacrifice the first polycrystalline silicon 22 as the first lead, as shown in FIG. Rate is Λ industry consumption including Zushi printing, LT〇) 23 and etching is low, and then channel, to adjust, and then proceed to silicon 22 as a thick deposition step. The polycrystal can achieve the selection of polycrystalline silicon It is difficult to control the more feasible crystal channel and then the mass ion implantation is shown as P-impurity. Then, a short time-selective second substantially Miaomujing selective deposition is performed on the wafer, and the gate of the process area removes the low input (such as ions) to form the chemical layer 21 and the low temperature oxygen 3 A layer After 23, the high-temperature drive polycrystalline silicon complex crystal between the hard-pressed and the breakdown 2 4 is etched for the purpose of epitaxial growth and only the product can be etched to achieve the selective recovery of the heart and the surroundings. Warmly oxidized layer P-type well area to form N. Dielectric layer partition paper ik is suitable for China's "Family Standards (CNS) A 4 specifications (210 X 297 Gongquan)> Electrical properties of livestock parts · Low-level mixing In the process of the polar structure, first, after the electrical well region 11, the whole wafer is thermally deposited and a doped layer containing low concentration impurities (Low Temperature Oxide) is deposited in sequence. Then, a gate mask is developed and the above part is developed. The exposed part of a polycrystalline silicon 22 is the same as the well region 11 and is of the first conductivity-type voltage (Punch-Through Voltage) into the formation channel region 111 as shown in FIG. 3B. It is deposited to form a thickness much greater than that of the first polycrystalline Doped with high concentration of impurities • The selective growth (Epitaxial Growth), It is performed on the surface of the first polycrystalline Miao 22, so of course, the second polycrystalline silicon can also be prepared first, but at this time, the etching of the entire wafer is uniformly etched, and the degree of etching is very different. Therefore, it is shown in Fig. 3C that the bi-polycrystalline silicon 24 is a field-effect electric circuit. 23 and conducting a low-wave second conductive crack $ is N-impurity ions, and n Langjing Guanggui / p -The source / drain, that is, if the object 25 is as shown in Figure 3E, its brother borrows -5 — ------- i — r .------ ------- ill · ---- book ---- line--(please read the note on the back? Matters and then write this page)
A6 B6 五、發明説明（） 先沈積介電屑（如氧 性濟部中喪«準局β：工消費含作钍印51A6 B6 V. Description of the invention () First deposit dielectric debris (such as in the Ministry of Oxygen Economy «Public Bureau β: industrial consumption contains thorium seal 51
Back )而逮 RIE)第一複 因此第一複 極·接著再 井區則為N ♦ 時介電層隔 入以形成N+ 之其中一主 二者係自我 知之低度摻 複晶矽22與 一具有雙重 又前述 井區，且若 程較NMOS， 外，於通道 離子植入步 阻覆蓋住。 過程中即需 極與1Γ /Ρ + 並使產品良 遂有必要提 製造成本之 成（圈中 晶矽2 2， 晶矽2 2與 進行高濃 雜質離子 離物25又 /Ρ* 源 要特色為 對準且完 雜汲極結 第二複晶 自我對準 之第一導 係屬互補 或PMOS複 區，Ν- / 驟中皆需 因此在互 四道光罩 源/汲 率變差同 出一種可 倒丁型低 化矽或氮化矽等）再 未示出）•之後，以 此時介電層隔離物25 第二複晶矽24構成一 度第二 ，而Ν 再一次 /汲極 該第一 全重* 構則未 矽2 4亦 之低度 電型井 式金氧 雜，除 Ρ- 源 增加二 補式金 方能完 極•由 時製造 縮短生 度摻雜 導電型雜質雕 型井區則為P t 做為遮罩，並 •此倒T型低 複晶矽22與N· 此由圖3 F明 具此特色*另 具有自我對準 摻雜汲極結構 區11可為N型 半導體製程（ 了需分別形成 /汲極及N* / 道光罩將不同 氧半導髗製程 成 N / P MOSt 於製程繁複極 成本亦無法降 產週期，提髙 汲極結構及其 一 6 — 回蝕刻 活性離 具有遮 具有倒 子植入 雜質讓 作短時 度摻雜 /P- 顧示出 (Etch 子蝕刻（ 罩作用， T型之閘 (如P型5 子），此! 間高温驅1 汲極結構 源/汲極 ，反觀習 一特色為該第一 作用，因此係屬 井區或 CMOS ) 不同導 P*源 導電型 之形成 N- / p- 易拉長 低，有 產品良 製法· 者是P型 ’則其製 電型井區 /汲極等 井區以光 源/汲極 源/汲 生產遇期 鑑於此， 率及降低 η 先 w 讀 背Back) and RIE) The first complex and therefore the first complex pole, and then the well area is N ♦ When the dielectric layer is separated to form one of N +, both of them are self-known low-doped polycrystalline silicon 22 and one It has the double well region mentioned above, and if it is more NMOS, it is covered by the channel ion implantation step. In the process, it is necessary to achieve 1Γ / Ρ + and make the product good. It is necessary to increase the cost of manufacturing (circular crystalline silicon 2 2, crystalline silicon 2 2 and high concentration impurity ion ion ion 25 / Ρ * source to be featured In order to align and complete the self-alignment of the second complex crystal of the drain junction, the first lead system is complementary or PMOS complex region. In the N- / step, it is necessary that the source / drain rate of the four mutual masks be the same. Reversible D-type reduced silicon or silicon nitride, etc.) (not shown again) • Later, with the dielectric layer spacer 25 at this time, the second polycrystalline silicon 24 constitutes a second, and N again / drain the first A full weight * structure is not silicon 2 4 and also low-degree electric well-type gold oxa, in addition to the P- source to increase the two-complement gold to complete the end The area is Pt as a mask, and the inverted T-type low polycrystalline silicon 22 and N. This is shown in Figure 3 F. * It also has a self-aligned doped drain structure. The area 11 can be N-type Semiconductor process (in order to form / drain and N * / channel photomask separately to process different oxygen semiconductors into N / P MOSt, the cost of the process is complicated and the production cycle cannot be reduced , To improve the structure of the dip-electrode and its 6-back etching activity away from the mask with the inverted implant implant impurities for short-term doping / P-Gu show (Etch sub-etching (mask effect, T-type gate (such as P-type 5 sub), this! Between high-temperature drive 1 Drain structure source / drain, in contrast, a characteristic is the first role, so it belongs to the well area or CMOS) Different conductivity P * source conductivity type formation N- / p- Elongation is low, and there are good production methods for the product. In the case of P-type, the production-type wells / drains and other wells are based on the light source / drain source / drain production period. In view of this, the rate and reduce η first w Read back
I 裝 訂 線 本认汰尺Λ通所中aa家怵苹（CNS>〒4 〇格uio X 297公»>I Binding line Aa Jiao Ping in the recognition ruler Λtong (CNS > 〒4 〇 格 uio X 297 公 »>
82. Q Λ6 Λ6 的係提供一種可簡化製程，縮 及降低製造成本之倒T型低度 短生產遇 掺雜汲極 簡化習知之具有雙重自我對準 要^/!>-及ΙΓ/卜二道離子植 —複晶矽厚度控制Ν-/ρ -浪度 /Ρ* 源/汲極於~~道難子植 簡化製程’提高產品良率，降 參數等多重功效者β 査委員對本發明技術手段及其功效能更 式並詳細説明如后·. 之低度掺 入步驟， ，使 N - / 入即可同 低製造成 —- ------ 五、發明説明（） 發明概述·· 本發明主要目 期，提高產品良率 結構及其製法。 本發明主要係 雜汲極結構製法需 於本發明中可藉第 p' 源/汲極及N♦ 時完成，以達具有 本及改善產品電性 為了使 贵審 加了解，茲附以圖 附圖説明： 圖1為傳統低度摻雜汲極結構之剖面圖· 圖2為習知倒τ型低度掺雜汲極結構之剖面。 圖3 A — 3 F為習知倒T型低度掺雜汲極結構之各主要製 程剖面圖。 ' 圖4 A — 4 Η為依據本發明之倒T型低度掺雜汲極結構之 各主要製程剖面圈。 首先請參閲圖 區11後，整個晶片 沈積一含高濃度雜 中高濃度雜質換雜 或擴散等·接著， -------------------------裝'—卜----.玎----'痒！ (請先《讀背面之注意事項*塡寫本頁) 緩濟部中夹«攀局Λ工消费合作杜印製 4 A，於矽基材1〇上形成第一導電型井 進行熱氧化以成長閘氧化層21，再依序 質掺雜之第一複晶矽22及氮化矽23，其 之方式有現場植入（In-Situ Doping) 再經一氮化矽光罩曝光，顯影及蝕刻氣 -7 - 本紙张尺度通和中BB家標準（CNS)〒4说格（210 X 297公* > g? Q αοη A6 A6 經濟部中央標準局R工消費合作社印製 B6_ 五、發明説明（） 化矽後形成具有如圖4 B所示之圖案以定義低度掺雜汲極 結構之通道區。 . 然後，再沈積一氧化層，該氧化層可以是一種低温氧 化層（LTO )，並藉回蝕刻（Etch-Back )技術使其在氮化 矽23之邊緣形成有第一氧化眉隔離物231，即如圖4 C所 示。接著，以氮化矽23及第一氧化層隔離物231為活性離 子蝕刻（RIE)之遮罩蝕刻第一複晶矽22，即如圖4 D所示。 再將整個晶片進行熱氧化，此時僅在第一複晶矽22之 邊緣處會與氧結合形成複晶氧化層221或先沈積氧化層再 藉回蝕刻技術形成第二氧化層隔離物以取代上述之複晶氧 化層221 ，以防止後續之磊晶成長（Epitaxial Growth)時 在第一複晶矽22邊緣之不當沈積，即如圖4 E所示。接著 ，再以濕蝕刻方式去除氮化矽2 3，形成如圖4 F所示之剖 面結構，並進行一選擇性沈積步驟。該選擇性沈積步驟實 質上為一磊晶成長，由於該複晶矽成長僅能在第一複晶矽 22表面進行，因此可達到選擇性沈積之目的。且該由磊晶 所成長之第二複晶矽24之厚度遠較第一複晶矽22為厚並以 現場植入方式使其具有高濃度雜質摻雜，如圖4 G所示。 由圖4 G亦明顯示出藉由選擇性複晶矽沈積可使第一 複晶矽22毋需任何光罩即可和第二複晶矽24自我對準並二 者短接形成一具有倒T型之閘極。 接著，再以濕蝕刻去除第一氧化層隔離物231及複晶 氧化層221 (或第二氧化層隔離物）並進行高濃度第二導 電型離子植入。此時在形成場效電晶體之晶片表面上具有 -8 - 本紙張尺度遴用中困國家攆準（CNS)甲4规格（210 X 297公货〉 --------------- --------r^ll·----訂---- J - . (請先聞讀背面之注意事項再坫寫本頁) 濟 部 肀 央 標 泽 Mj 消 貧 含 作 社 印 a 五、發明説明（） 三種不同厚度之區域，其中 係由第一複晶矽22,第二後& 厚者之厚度為第一複晶矽h 僅為閛氧化層21,因此當高與 時就呈現出不同之阻擋程度埃 次厚者則阻擋部份離子故形11 極’最薄者則讓绝大部份艇 p+源/汲極，即如圖 /汲極之濃度可由第一複晶 之N-/P-源/汲極與N*/ 域 子 所 P* 級 一複晶矽22與第二複晶矽24可 汲極與第一複晶矽22亦可自我 重自我對準之製程· 又本發明之第一導電型區 區以製成NMOS或PMOS低度辕雜 式金氧半導髏（CMOS )之低度 前述二者更為複雜，而本發明 供一較習知者更為簡化之製程 低濃度及高濃度之源/汲極n /P- 源/汲極與N+/P+ 源 此僅需二道光罩，意即於形成 構之前不必如習知般需以光阻 蓋。由於本發明可簡化製程， 入同時完成的•並且該源 厚者位 矽24和 W氧化 度雕子 於最厚 低度摻 通過故 示·明 22之厚 源/ 極離子 自我對 對準， 11可以 汲極結 摻雜汲 之主要 ，如前 四道光 /汲極 NM0S 或 將不同 因此對 -9 - A6 B6 於通道 閛氧化 眉21之 植入該 者則無 雜之N- 形成高 顯地， 度來調 汲極係 植入時 準外， 故本發 為N型 構•唯 極結構 特點即 面所述 罩*而 二者可 PM0S 低 導電型 縮短生 區上， 層21之 和，最 三種不 離子植 /P-度摻雜 該N- / 整*又 藉一次 除了前 Ν' / P- 明仍為 井區或 若欲形 ，則其 是可針 ’習知 本發明 同時完 度掾雜 3L區域 產遇袖 其厚度 和，次 薄者則 同厚度 入，於 源/汲 之 p- 源 本發明 離子植 述之第 源/ —具雙 -------Γ — ------------裝1-^-----訂----'-線 (請先閲讀背面之注意事項再塡S本頁) 本紙中《Β家料（CNS) T<5*Li?2° x 297 公货 B6 五、發明説明（） 產品良率，及降低製造成本等方面皆有莫大地助益· 又本發明仍保留有習知倒T犁低度掺雜汲極結構之優 點，即本發明之N-/P- 源/汲極與倒T型閘極完全重疊 使場效電晶體工作時N-/P- 源/汲極可感應電子/電洞 ，增加汲極電流。因此在不影響汲極電流之情沉下’本發 明之N-/P- 源/汲極濃度就可以降低，使N-/P- 源/ 汲極與通道介面空乏區之電場強度約減弱30¾ ’以達具有 提高熱電子之抑制力，延長元件之工作壽命，降低基材漏 電流，及減少不必要之功率消耗等多重功效。本發明誠符 合新穎性及進步性之專利要件，爰依法提出申請。 一 10 — (請先《讀背面之注♦?事項再項寫本頁) 娩濟部中夹標準局Λ工消费合作社印製 -...Μ _ 尽丨又:||_|_iiS ilimi Ιΐι6ιιίιί"ίιι0ι1ί^· - 本*Μ艮尺度通用中《國家標準（CNS) τ 4規格（210 X 297公址）82. The Q Λ6 Λ6 system provides an inverted T-type low-level short production that simplifies the process, shrinks and reduces the manufacturing cost. It has a dual self-alignment requirement ^ /! ≫-and ΙΓ / 卜Second ion implantation-polycrystalline silicon thickness control Ν- / ρ-wave / P * source / drainage ~~ Daonanzi plant simplifies the process' improving product yield, lowering parameters and other multiple effects β Inspect the member of the present invention The technical means and their functions can be more formalized and explained in detail as follows. The low-level incorporation step, so that N-/ into can be manufactured with the same low ----------- V. Description of the invention () Summary of the invention ·· The main objective of the present invention is to improve the product yield structure and its manufacturing method. The present invention is mainly based on the manufacturing method of the hybrid drain structure. In the present invention, it can be completed by the p 'source / drain and N ♦, in order to achieve the cost and improve the electrical properties of the product. DESCRIPTION OF THE DRAWINGS: FIG. 1 is a cross-sectional view of a conventional low-doped drain structure. FIG. 2 is a cross-section of a conventional inverted-τ low-doped drain structure. Figures 3A-3F are cross-sectional views of the main processes of the conventional inverted T-type low-doped drain structure. 4A-4H are the main process profile circles of the inverted T-type low-doped drain structure according to the present invention. First of all, please refer to Figure 11, after the entire wafer deposits a high-concentration impurity containing high-concentration impurities for replacement or diffusion, etc. Then, ---------------------- --- Pretend --- Bu -------- Ning ---- 'itch! (Please first read "Notes on the back of the page * 塡 write this page") The Ministry of Economic Affairs and Economics «Panju ΛWorks Consumer Cooperation Co., Ltd. printed 4 A, forming the first conductive well on the silicon substrate 10 for thermal oxidation to The gate oxide layer 21 is grown, and then the first polycrystalline silicon 22 and the silicon nitride 23 are sequentially doped, and the method is In-Situ Doping, then exposed through a silicon nitride mask, developed and Etching gas-7-This paper standard Tonghezhong BB standard (CNS) 〒4 said grid (210 X 297 g * * g? Q αοη A6 A6 Printed by the Ministry of Economic Affairs Central Standards Bureau R Industrial and Consumer Cooperatives B6_ V. Invention Description () After siliconization, a channel region with a pattern as shown in FIG. 4B is defined to define a low-doped drain structure. Then, an oxide layer is deposited, which may be a low-temperature oxide layer (LTO) , And borrow the Etch-Back technology to form the first oxide eyebrow spacer 231 on the edge of the silicon nitride 23, as shown in FIG. 4C. Then, the silicon nitride 23 and the first oxide layer The spacer 231 is a mask of active ion etching (RIE) to etch the first polycrystalline silicon 22, as shown in FIG. 4D. The entire wafer is then subjected to thermal oxygen At this time, only the edge of the first polycrystalline silicon 22 will combine with oxygen to form a polycrystalline oxide layer 221 or first deposit an oxide layer and then form a second oxide layer spacer by etching technology to replace the above polycrystalline oxide layer 221, to prevent improper deposition on the edge of the first polycrystalline silicon 22 during subsequent epitaxial growth, as shown in FIG. 4E. Then, the silicon nitride 23 is removed by wet etching to form The cross-sectional structure shown in FIG. 4F, and a selective deposition step is performed. The selective deposition step is essentially an epitaxial growth. Since the growth of the polycrystalline silicon can only be performed on the surface of the first polycrystalline silicon 22, it can be To achieve the purpose of selective deposition. The thickness of the second polycrystalline silicon 24 grown by epitaxy is much thicker than that of the first polycrystalline silicon 22 and it is doped with high concentration impurities by field implantation, as shown in the figure 4 G. It is also obvious from FIG. 4 G that selective polycrystalline silicon deposition can make the first polycrystalline silicon 22 self-align with the second polycrystalline silicon 24 without any photomask and the two are short Then, a gate with an inverted T shape is formed. Then, the first oxygen is removed by wet etching Layer spacer 231 and polycrystalline oxide layer 221 (or second oxide layer spacer) and high concentration second conductivity type ion implantation. At this time, the surface of the wafer where the field effect transistor is formed has -8-the size of this paper Use the CNS Grade A 4 specifications (210 X 297 public goods) --------------- -------- r ^ ll · --- -Subscribe ---- J-. (Please read the precautions on the back first and then write this page) The Ministry of Economic Affairs, Jiyang Biaoze Mj, Poverty Alleviation, Containing a Social Print a. V. Description of the invention () Three different thickness areas, Among them, it is composed of the first polycrystalline silicon 22, the thickness of the second rear & the thickest is that the first polycrystalline silicon h is only the oxide layer 21, so when the high and the high, it will show a different degree of blocking. Blocking part of the ions and forming the 11 poles' thinnest allows most boats to have p + source / drain, that is, the concentration of the figure / drain can be determined by the N- / P-source / drain and N of the first polycrystal * / The process of the P * grade polycrystalline silicon 22 and the second polycrystalline silicon 24 of the sub-domain can be drained and the first polycrystalline silicon 22 can also be self-realigning process. Also the first conductivity type region of the invention Made of NMOS or PMOS low-degree hybrid gold oxide semiconducting skeleton (CMO The low-level of S) is more complicated, and the present invention provides a more simplified process of low-concentration and high-concentration source / drain n / P-source / drain and N + / P + source. Only two photomasks are needed, which means that it is not necessary to cover the photoresist before the formation of the structure. Since the present invention can simplify the manufacturing process, it can be completed at the same time, and the source thickness of the silicon 24 and the W oxide is mixed at the thickest and lowest level, so the thick source / polar ion self-alignment of Ming 22 is shown, 11 The main of the junction can be doped with the junction, such as the first four channels of light / drain NM0S or it will be different. Therefore, for the implantation of -9-A6 B6 in the channel eyebrow oxide eyebrow 21, there is no heterogeneous N- formation. The degree of adjustment is very accurate when the implantation of the drain electrode system, so the present invention is N-type structure. The unique structure characteristic is the mask * and the two can be PMOS low conductivity type shortening the living area, the sum of layer 21, the most three Do not ion implant / P-degree doping the N- / integer * and borrow it again except for the former Ν '/ P- Ming is still a well area or if it is shaped, it can be used. The thickness of the sleeve in the 3L region is the same as that of the next thinnest, and the thickness of the sleeve is the same. The source of the source of the source is the first source of the ion implant described in this invention. -------- install 1-^ ----- order ----'- line (please read the precautions on the back before reading this page) "B House Material (CNS) T < 5 * Li? 2 ° x 297 cm B6 V. Description of the invention () The product yield, and the reduction of manufacturing costs are of great help. Also, the present invention still retains the advantages of the conventional inverted T plough low-doped drain structure, namely the N of the present invention. -/ P- source / drain and the inverted T gate completely overlap so that the N- / P- source / drain can sense electrons / holes when the field effect transistor is working, increasing the drain current. Therefore, without affecting the sink current, the concentration of the N- / P-source / drain of the present invention can be reduced, so that the electric field strength of the void region of the N- / P-source / drain and channel interface is reduced by about 30¾ 'In order to improve the suppression of hot electrons, extend the working life of components, reduce substrate leakage current, and reduce unnecessary power consumption and other multiple effects. The present invention truly conforms to the novelty and progressive patent requirements, and the application is filed according to law. 10 — (please read "Notes on the back"? Matters and then write this page) Printed by the Ministry of Labor and Economics, China Bureau of Standards, ΛGong Consumer Cooperatives -... Μ _ 並 丨 又: || _ | _iiS ilimi Ιΐι6ιιίιί " ίιι0ι1ί ^ ·-This * M Gen standard "National Standard (CNS) τ 4 specifications (210 X 297 public address)