TWI220537B - Method for forming high voltage CMOS by retrograde ion implantation - Google Patents

Abstract

This invention discloses a kind of method for forming high voltage CMOS by retrograde ion implantation, in which a retrograde ion implantation is applied to form the doped well regions and N- and P- drift regions of the high voltage CMOS structure, and a high voltage ion implantation is used to form such doped regions after the field oxide isolation structure is formed. The high voltage CMOS formed according to the invention has better electrical characteristics, higher breakdown voltage, larger driving current, and reduced surface area of the whole device.

Description

1220537 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a high voltage device (High Voltage Device) 'particularly' about a method of forming a high voltage by using a reverse (retr 〇grade) ion implantation method Method for complementary metal oxide semiconductor (CM0S) [prior art]

According to this, high-voltage components are applied to the parts of electronic products that need to be worked with high voltage. Generally, in the structure of integrated circuits, some products have more control components in the input / output (I / 0) area than in the core. In the element area, the required voltage of the control element is greater. This input / output area must have a component that can withstand more southerly voltage than the moon 'to avoid the phenomenon of current breakdown under normal high voltage operation. The structure is different from general components. —1 The structure of the South-China complementary metal-oxide-semiconductor element (CM0s) is as shown in Fig. 1. An N-well NMοΓγ · 1 I12 is first formed in a p-type semiconductor substrate 10, and then an N-type is formed. The drift (N_drift) region 14 is connected to the P-drift region 16 and the coffee region is connected to form a field oxide layer 18 on the substrate 10,

oxide) 20 and polysilicon gate 2 ?, 畀 尨 τlice formation layer [gate implantation method to form an N + type in the NM0S region within the substrate 10, and a type 3 source from the 3 region, and a drain (drain) ). At first glance, the source (the above-mentioned conventional process method, the surface of the channel is near the ^ -type drift region of the city ^ 14 ^ A point in the figure, the power line distribution (

Page 5 1220537 V. Description of the invention (2)

Electric Field) high density 'potential Crowding' makes the empty region (Depletion Region) formed by the N-type drift region 14 insufficient to resist the high-voltage power line distribution, which is prone to early breakdown (Breakdown) . In order to increase the breakdown voltage, the traditional method is to reduce the doping concentration of the N-type drift region 14 and increase the width of the empty region to increase the breakdown voltage. However, a decrease in the concentration of the N-type shift region 14 will increase the channel resistance (Channei), and its on-resistance (0n-resistance) will be increased, so that the current drive (ϋϋΓΓ6ηΐ DriVlng) capability of the element is similar _ Inverse :: Invented in view of the above-mentioned problems, we proposed a method to form a high-voltage complementary metal-oxide semiconductor by using the method to solve the conventional shortcomings. [Summary of the invention] Way day! 5 The main purpose is to provide a method of using complementary ion implantation to complement the complementary metal-oxide semiconductor, the high voltage formed by the semiconductor system has better electrical characteristics, And its crash-resistant electric ruler's current drive capability is also greater. Method two = 2 5 and another = purpose, is to provide a method using reverse ion implantation complementary 卞 = pressure complementary metal-oxide semiconductor, the high voltage produced is small, ^ = two semiconductor design specifications (design rule) can be Largely reducing the size of a body can effectively reduce a lot. Another purpose of 1 month is to provide a high-voltage complementary metal-oxide semiconductor manufacturing method capable of improving the latch-up effect (P effect).

V. Description of the invention (3) Method. An ion implantation method is formed on the conductor substrate, and the doped N-type drift causes the doped ions to drive on the semiconductor substrate and the polycrystalline silicon gates. It will be explained in the N-doped region and the heavy P-type ocean, respectively. Achieved the work to achieve the above purpose 'The present invention has an isolation structure and a sacrificial oxide layer; and the use of inverse = high voltage ion implantation & replacement of the hybrid region with -domain and P-type drift region i or; After thermal processing, it is inserted into the substrate, and then the sacrificial oxide layer is removed; a gate oxide layer and a polycrystalline silicon gate structure are formed thereon; ~ ion implantation in the semiconductor substrate on both sides of the structure + A heavy N-type doped region is formed in the P-type drift region, which is used as a source / drain. ^ ^ It is easy to understand the purpose, technical content, and special effects of the present invention by using specific embodiments and accompanying drawings. ", [Embodiment] The present invention uses a high-voltage ion implantation in a semiconductor substrate with an isolation structure to form a heavy-duty: well region and lightly doped N-dr ift and P-drift can be used as NMOS region and PMOS region of high-voltage complementary metal-oxide semiconductor (CMOS), respectively. Metal-oxide semiconductors have better electrical characteristics, so they can effectively solve these defects existing in the conventional technology. ^ The first (a) to the second (d) views of the stomach are cross-sectional views of the steps of the preferred embodiment of the present invention in the fabrication of a directional complementary metal-oxide semiconductor. As shown in the figure, the method disclosed in the present invention is Includes the following steps ... First, as the second (a

Page 7 1220537 V. Description of the Invention (4)) The figure provides a P-type semiconductor substrate 30. A thin oxide layer and an oxide layer are sequentially formed on the surface of the semiconductor substrate 30 by chemical vapor deposition technology. And a patterned silicon nitride layer (not shown), and using the patterned silicon nitride layer as a mask, the oxide layer is etched to form a field oxide as shown in the second (a) (F ie 1 d 0 X ide) isolation structure 3 2; subsequently, the nitride layer and the thin oxide layer are removed by engraving, and then a sacrificial oxide layer 34 is grown as shown in the figure. Next, referring to the second figure (b), the retrograde ion implantation method is used to dope the n-type phosphorous with a high voltage of about 400 to 800 kiloelectron volts (KeV). Ions are implanted into the semiconductor substrate 30 at a concentration of 5 * 1 〇12 ~ 1 * 1 〇 4 / cm 2 (cm 2) to form a heavily doped n-type doped well area%; and at 2000 ~ 6 The energy of about 〇〇KeV 'implants n-type doped ions such as arsenic or arsenic into the semiconductor substrate 30 at a concentration of 5 * 丨 〇12 ～ i 木 lj / cm2 to form a lightly doped n-type ions. Region 38; and then implanting 1) type dopant ions such as boron with an energy of about 100 to 300 KeV at a concentration of 丨 * 1013 ~ 丨 * 1014 / CD2 into the N-type of the semiconductor substrate 30 ^ The doped well region 36 forms a lightly doped p-type drift region 40. After: After thermal processing, doped ions are driven into the conductor substrate 3G, in order to drive people to adjust the concentration distribution region to strike the lattice structure to repair the lattice structure. Then The sacrifice oxide layer 34 is removed by etching. ^ As shown in the gate diagram, a n-layer is first grown on the surface of the semiconductor substrate 3G, and a polycrystalline silicon layer is deposited thereon. N-type drift region 38 and the p-type drift region

1220537 V. Description of the invention (5) Polycrystalline silicon gate structure 44 is formed above 40. An ion implantation step is performed in the semiconductor substrate 3 on both sides of the polycrystalline silicon gate structure 44, and the semiconductor substrate 30 and the N-type are respectively formed. A heavy N-type doped region 46 and a heavy P-type doped region 48 are formed in the drift region 38 and the P-type drift region 40 as shown in FIG. 2 (d). The heavy N-type doped region κ is used as N The source / drain of the type-drift region 38 is formed to form an OFF structure, and the heavily p-type doped region 48 is used as the source / drain of the p-type drift region 40 to form a P MOS structure. The structure of the high-voltage complementary metal-oxide semiconductor (CM0s) formed by the present invention is shown in FIG. 2 (d). The channel located below the field oxidation isolation structure 32 is an N-type drift region 38 or a P-type. The high-concentration production point in the drift region, and the position near the point A in the figure is the lowest concentration. Because the concentration of the channel under the field oxidation barrier structure 32 is much larger than the conventional method, and the concentration at the point a can be lower than that of the conventional method. Therefore, the breakdown voltage of the high-voltage CMOS formed according to the present invention can be higher, and the current driving capability is greatly improved. In addition, the design of the high-voltage complementary metal-oxide semiconductor fabricated by the present invention is also used. The design rule can be greatly reduced; for example, the field oxidation isolation structure used to isolate NM0S and PM0S, such as χ2 in the second (d) figure is about 5 // m, which is much smaller than the conventional technology in the first Χι in the figure needs about 5 claws. Therefore, the present invention can effectively reduce the overall component area significantly. Furthermore, the method of the present invention can also improve the problems caused by the latch-up effect.

1220537 V. Description of the invention (6) The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The limitation of the patent scope of the present invention, that is, all equal changes or modifications made according to the spirit disclosed by the present invention, should still be covered by the patent scope of the present invention. [Simplified description of drawing number] 10 P-type semiconductor substrate 12 N-type well 14 N-type drift region 16 P-type drift region 18 Field oxide layer 20 Gate oxide layer 22 Polycrystalline gate 24 N + type ion doped region 26 P + Type ion-doped region 30 P-type semiconductor substrate 32 field oxidation isolation structure 34 sacrificial oxide layer 36 N-type doped well region 38 N-type drift region 40 P-type drift region 42 gate oxide layer 44 polycrystalline silicon gate structure 46 heavy N-type Doped region: 48 heavy P-type doped regions

1220537

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Claims (1)

1220537 VI. Scope of patent application 1. A method for forming a high-voltage complementary metal-oxide semiconductor using reverse ion implantation, which includes the following steps: providing a semiconductor substrate on which an isolation structure and a sacrificial oxide layer are formed; The reverse ion implantation method is used to form a re-exchange well region with high-voltage ion implantation, and the doped N-type drift region and the p-type drift region are removed from the sacrificial oxide layer after 2 34; on the semiconductor substrate Forming a gate oxide layer, and forming a polycrystalline silicon gate structure by using a etch process; and performing a step in a semiconductor substrate on both sides of the polycrystalline silicon gate structure to form heavy N in the N-type drift region and the p-type pond, respectively. Doped region and heavily p-doped region 2 / drain. The method described in item 1 of the scope of patent application is a p-type semiconductor substrate, and the heavily doped well region is: the method described in item 1 of the scope of patent application, which is a field oxidation isolation structure. According to the method described in item 3 of the scope of patent application, the basin structure uses a patterned silicon nitride layer τ τ formed by the field. Dry curtain, the method described in item 1 of the scope of patent application for etching, wherein the weight is more important than the bottom, such as the separation layer and the middle, and the lithography 饳 ion implantation region is used as the source conductor base, and the doped well structure is oxidized. Doped well 5 1220537 The 7 8 9 10 region is doped into the semiconductor substrate at a power density of about 40 to 80 thousand kiloelectron volts (KeV), and the doped ions are within 5 * 1012 to PiOH / cm 2 / cm 2. Chen Duzhi The method according to item 5 of the scope of patent application, wherein the dopant is an N-type dopant ion, preferably a phosphorus ion. -The method as described in item 1 of the scope of the patent application, wherein the strict type region is an energy of about 2000 to 600 thousand electron volts (KeV) = wide N-type doped ions at 5 * 1 ( F square centimeters, the curvature is implanted into the semiconductor substrate. The method described in item 7 of the scope of the patent application, wherein the N-type doped ion is a phosphorus ion or an arsenic ion. The method according to item 1 of the patent scope, wherein the p-type drift region is an energy of about 100 to 300 kiloelectron volts (KeV), and the P-type doped ion is set to ~ 1 * 1014 / cm 2 (Cm2) is implanted into the semiconductor substrate. The method described in item 9 of the scope of patent application, wherein the p-type doped ion is boron ion. Page 13