TWI220297B - Manufacturing method of high-voltage device capable of improving device characteristic - Google Patents

Abstract

A kind of manufacturing method of high-voltage device capable of improving device characteristic is revealed in the present invention. On a semiconductor substrate where drift regions are formed, a thin oxide layer, a silicon nitride layer, and a patterned photoresist (PR) layer are formed. By using the patterned PR layer as the mask, silicon nitride layer is etched. After that, PR layer is removed. Then, a phosphor glass layer is formed on the semiconductor substrate, and phosphor ions are driven into the substrate below at high temperature to form a phosphor ion doped region. After that, the phosphor glass layer, the silicon nitride layer and thin oxide layer are removed. Then, the field oxide layer, the gate structure and the source/drain are sequentially formed on the semiconductor substrate. In the invention, the drift region having phosphor ion doped region with gradient distribution is used to raise the breakdown voltage and increase the driving current of device.

Description

1220297 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high voltage device (H i gh Voltage Device) capable of improving device characteristics and enhancing device efficiency . [Prior art]

According to this, high-voltage components are used in electronic products that require high-voltage operation. Usually in the architecture of general integrated circuits, some products have more control components in the input / output (I / 0) area than core components. The control element in the area requires a larger voltage, and this input / output area must have a component that can withstand higher voltages to prevent the normal operation of the component under high voltage from causing voltage breakdown (Breakdown) and other phenomena; so the high voltage component The structure is different from general components. When a conventional semiconductor element has a structure of a high-voltage metal-oxide semiconductor element, its structure is shown in the first figure. The manufacturing process of this high-voltage metal-oxide semiconductor element is: first form an N in a P-type semiconductor substrate 10 Type well

N-Well), and an N-dr ift region 1 2 in the high-voltage element is also formed at the same time; a field oxide layer (F ie 1 d Ox i de) is sequentially formed on the semiconductor substrate 10 1 4 And a gate structure 16 comprising a gate oxide layer (Gat e Oxide) 16 2 and a polycrystalline silicon layer 16 4; finally, an ion implantation technique is used to form N + -type ions in the semiconductor substrate 10 The doped region is used as the source 18 and the drain 2 0. In this conventional manufacturing method, the drift region 12 is along the channel surface and close to the point A in the figure. The electric field is higher and the potential is more crowded.

Page 5 1220297 V. Description of the invention (2) Crowding), Reg i on) are insufficiently tamped, and then the voltage is broken, and the degree of practicability is further increased; The shortcomings in the high technology "· [New content] The piezo element manufacturing method of the present invention has a breakdown voltage, and the piezo element manufacturing method of the present invention is located in the channel and the previous technology occurs to achieve the above. A nitride layer is used as a mask, and the empty area formed by the drift region 12 on the semiconductor substrate (D ep 1 eti ο η to resist high voltage is not enough to resist the high voltage power line is easy to cause the device to collapse early.) In order to improve the collapse solution, the width of the doped dense empty region of the drift region 12 is reduced to achieve the purpose of increasing the collapse voltage. The reduction of the concentration will increase the channel, and its on-resistance will increase. The transistor ’s current driving capability is also relatively reduced. The invention is to address the above-mentioned problems, and propose a method for improving the manufacturing of piezoelectric components to effectively solve the problem. The main purpose is to provide a high method that can improve the characteristics of the device, which uses an improved drift region structure to increase the driving current of the high-voltage device. Another object is to provide a method that can improve the characteristics of the device. The method uses a lower concentration in the ice shift region and a gradient distribution in the drift region near the pole to improve the shortcomings of premature collapse and reduced current drive capability. The purpose of the present invention is to provide a semiconductor substrate first. A drift region; sequentially forming a thin oxygen oxide layer and a patterned photoresist layer on the semiconductor substrate, and using the patterned photoresist to etch the nitride stone layer, and then remove the patterned photoresist layer; A layer of phosphorous glass, and the phosphorus ions in it are high temperature

V. Description of the invention (3) Wei Ru to the substrate below it ~ The scale breaks the glass layer and nitriding to form a phosphorus ion doped 4 ψ λ, ^ ^ layer and thin oxygen & > · p ; Etching removes the miscellaneous area. " Pole structure and source = Heavy ion doping with 导体 and Drain on the conductor base ^ The following is a concrete realization of the purpose of the present invention: j; together with the attached drawings, it will be explained in more detail. Technical contents, characteristics and achievement thereof: Implementation Modes ^ The present invention is to form a concentration in the field oxidation field = micro-doping, and form a concentration in the drift region close to the square, so that the The concentration of the channel below the layer is gradient and redundant to the value close to the semiconductor substrate =, the highest degree, and then its concentration is distributed in a gradient, the shift area is equivalent, so that the concentration in the use area is the lowest, and the concentration in this area and the voltage and drive Current. The structure of the drift region is improved to improve the steps of the second (a) to the second high-voltage component at the same time. The diagram is a preferred embodiment of the present invention. The manufacturing method includes the following steps = sectional view, as shown in the figure. The production of the present invention is shown in the second U). V / A P-type semiconductor substrate is first provided, and an N-type lightly doped semiconductor substrate 30 is formed. The semiconductor substrate 30 uses ion implantation transfer regions 32, which are used / used ^ This is the N-type drift used as a high-voltage component. The dopant ions such as dish ions have an energy of about 100 KeV to 180 KeV, and the semiconductor is doped in the semiconductor substrate 30 and heated. At a lx 10W per cubic centimeter in the semiconductor substrate 30 to form a heterogeneous dose medium 32 〇 knife to 5x 1 〇 3 / per cubic centimeter drift zone too. Page 7 1220297 V. Description of the invention (4) Simultaneous As shown in FIG. 2 (a), a thin oxide layer 34 and a nitride nitride layer 36 are sequentially deposited on the surface of the semiconductor substrate 30 by using a chemical vapor deposition technique. Next, as shown in FIG. 2 (b), a patterned photoresist layer 38 is formed on the semiconductor substrate 30 to cover the surface of the silicon nitride layer 36. The patterned photoresist layer 38 is developed. Form a ladder-shaped figure with an opening. With the patterned 38 photoresist layer as a mask, the silicon nitride layer 36 is etched using dry etching technology, and the patterned photoresist layer 38 can be removed after completion. At this time, the structure of the silicon nitride layer 36 is as follows. This is shown in the second (c) figure.

Next, a Phosphorus Glass deposition step is performed. At a temperature of about 9 75 ° C and in an environment of a mixed gas of nitrogen, oxygen and phosphorus oxyphosphate (poci 3), a chemical vapor deposition method is used on the semiconductor. A phosphorous glass layer 40 is formed on the substrate 30. As shown in the second (d) diagram, the phosphorous glass layer 40 covers and fills the surface of the silicon nitride layer 36; then 800 to: 1 is used. Moderately high temperature between 0 0 0 ° C, preferably about 9 7 5 ° C. A high temperature drive in step is performed to diffuse the phosphorus ions in the phosphor glass layer 40 to the semiconductor substrate below it. 3 0 In the drift region 32, a phosphorus ion doped region 42 having a gradient distribution is formed. After the scale ion-doped region 42 is completed, the aforementioned phosphorous glass layer 40, the silicon nitride layer 36, and the thin oxide layer 34 can be removed by wet etching. However, a thin oxide layer and a silicon nitride layer are re-grown, and then a lithographic etching process is performed to form a field oxide layer 44 as shown in FIG. 2 (e). Finally, a gate oxide layer 4 6 2 is grown on the surface of the semiconductor substrate 30, and a polycrystalline silicon layer 4 6 4 is deposited thereon, and then a patterned photoresist 1220297 is used. 5. Description of the invention (5), definition of the remaining time The polycrystalline stone layer 4 6 4 and the gate oxide layer 4 6 2 form a gate structure 4 6 having a polycrystalline silicon layer 4 6 4 and a gate oxide layer 4 6 2 below, please refer to the second (f As shown in the figure, an ion implantation step is performed in the semiconductor substrate 30 on the two sides of the gate structure 46 to form two N + -type heavy ion doped regions, which are respectively used as the source 48 and the drain. 50 0 uses.

Please refer to the second (f) diagram. Due to the high-voltage device manufactured by the present invention, the concentration of the drift region 32 under the field oxide layer 4 4 may have a lighter doping than usual, but it is near field oxidation. The concentration of the channel area under layer 44 is gradient distributed. In the phosphorus ion-doped region 42 having a gradient distribution, the region near the drain electrode 50 has the highest concentration, and the concentration in this region is equivalent to the drain electrode 50, and then in the phosphorus ion-doped region 42. The concentration of G is a gradient distribution, and the concentration near the point A shown in the figure is the lowest. The concentration in this area is equivalent to the drift region 32. At this time, because the concentration of the drift region 3 2 is relatively low, the purpose of increasing the breakdown voltage can be achieved; on the other hand, because the drift region 32 is located in the channel near the drain 50 and the concentration is relatively high and close to the drain With a doping concentration of 50, its driving current will be significantly increased.

Therefore, the present invention uses a lower concentration in the drift region and a gradient distribution in the region where the drift region is located in the channel and near the drain to increase the breakdown voltage and increase the drive current of the high-voltage component to improve the early breakdown of the prior art and The disadvantage of reduced current drive capability. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the patent of the present invention cannot be limited by it Range, ie large

1220297 V. Description of the invention (6) Any equal changes or modifications made in accordance with the spirit disclosed in the present invention shall still be covered by the patent scope of the present invention. Figure number description:

10 Semiconductor substrate 12 Drift region 14 Field oxide layer 16 Gate structure 162 Gate oxide layer 164 Polycrystalline silicon layer 18 Source 20 Drain 30 Semiconductor substrate 32 Drift region 34 Thin oxide layer 36 Silicon nitride layer 38 Patterned photoresist 40 Fill Glass layer 42 Hf ion-doped region 44 Field oxide layer. 46 1 Gate structure 462 Gate oxide layer 464 Polycrystalline silicon layer 48 Source 5 0 No pole Page 10 1220297 The diagram is a simple illustration The first picture is a conventional high voltage metal A structural cross-sectional view of a semiconductor element. Figures 2 (a) to 2 (f) are cross-sectional views of the structure of each step in the process of manufacturing a high-voltage component according to the present invention.

Claims (1)

122 ^ 297, ^ I have been replacing pages for many years, the month e Pi No. 92116086 is amended VI. Patent Application Scope L · A method for manufacturing high-voltage components that can improve the characteristics of the components, which includes the following steps: 1. Provide a semiconductor substrate, where The system has been formed into a drift region; a thin oxide layer and a silicon nitride layer are formed on the semiconductor substrate, and a patterned photoresist layer is formed on the surface of the nitride layer, and the patterned photoresist layer is Develop a ladder-like pattern with an opening size; use the patterned photoresist layer as a mask, etch the silicon nitride layer, and then remove the patterned photoresist layer; form a phosphorous glass layer on the semiconductor substrate, and perform Driving at high temperature causes phosphorus ions in the phosphorous glass layer to diffuse into the substrate below it to form a phosphorus ion doped region; removes the phosphorous glass layer, the silicon nitride layer, and the thin oxide layer; on the semiconductor substrate A field oxide layer and a gate structure are sequentially formed; and a heavy ion doped region is formed in the semiconductor substrate as a source and a drain. 2 · The method for manufacturing a high-voltage device according to item 1 of the scope of the patent application, wherein the drift region is an N-type lightly doped well region. ί · The method for manufacturing a high-voltage device according to item 2 of the scope of the patent application, wherein the N-type lightly doped well region uses an energy of 100 KeV to 180 KeV to implant N-type dopants such as phosphorus ions into the semiconductor substrate The dopant is driven into the formed by a thermal process. 4 · The method for manufacturing a high-voltage component as described in item 2 of the scope of the patent application, wherein the ion doping dose of the N-type lightly doped well region is between 1 * 1 0 12 / cm 3 to 5 * 1 0 13 / Between each cubic centimeter. > Page 12 No. 12 92116086 _η said Amendment 6. Scope of patent application 5 · If applying for the high level of the scale glass gas 6 · If applying for the high level in ##. 7 · If the application school fills in to 100 000 C 8 · If the application school removes the wet etch side 9 · If the application school uses the gate range, the glass layer is the best in the temperature range. Silicon nitride ranges from high ion to high temperature. The finish range of the phosphor range glass structure is based on a structure of a gate oxide layer and a polycrystalline silicon layer. The method for manufacturing a high-voltage element according to item 1, which is formed by injecting a mixture of nitrogen, oxygen, and oxychloride dishes, and using a chemical vapor deposition method. The method for manufacturing a high-voltage component according to item 1, in which the steps of the layer are completed using the dry I insect engraving technique. The method for manufacturing the high-voltage component according to item 1, in which the temperature is in the range of 8 0 1 The method for manufacturing a high-voltage device, the silicon nitride layer, and the thin oxide layer use the method for manufacturing a high-voltage device according to item 01, Page 13