434712 5746twf.doc/006 A7 B7 經濟部智慧財度局員工消費合作社印製 五、發明説明（/) 本發明是有關於一種積體電路的製程技術，且特別 是有關於一種自行對準金屬矽化物的製程。 當積體電路的積集度增加，使得金氧半電晶體（Metal Oxide Semiconductor ’ M〇S)元件之源極與汲極的電阻逐漸 上升到與通道的電阻相當時，爲了調降源極與汲極的片電 阻（Sheet Resistance)，並確保金屬與金氧半電晶體間的淺 接面（Shallow Junction)完整，在0.5微米以下的超大型積體 電路(Very Large Scale Integration，VLSI)製程中逐漸使用自 行對準金屬砂化物（Self-Aligned Silicide，Salicide)製程，以 減小多晶砂（Polysilicon)以及主動區域（Active Area)的電 阻，而在0.25微米製程中則以自行對準鈦金屬矽化物CH-Salicide)的製程爲主要的選擇。自行對準金屬矽化物乃是 在已定義閘極以及已建立間隙壁（S p ac e r)之晶片上沉積一 金屬薄膜，在高溫下，部份沉積的金屬薄膜會與金氧半電 晶體源極以及汲極上的矽以及閘極上的多晶矽反應，在矽 以及多晶矽的表面形成低電阻的金屬矽化物（Silicide)，再 以濕式蝕亥[J(Wet Etching)除去金屬薄膜。 自行對準鈦金屬矽化物(Ti-Salicide)的製程應用於0.18 微米以及0.18微米以下之製程時，其缺失之一爲窄線效應 (Narrow Line Effect):所謂窄線效應係由於閘極尺寸太小， 使得成長在閘極多晶矽上之金屬矽化物與多晶矽接觸的應 力（Stress)太大，或是成核位置(Nudeatmn Site)太少’造成 金屬矽化物中金屬與矽的比例有所改變’導致金屬砂化物 薄膜品質不佳，致使片電阻增加，而影響閘極操作的效能。 3 1- n n I n 訂 ~線 (請先閱讀背面之注意Ϋ項异4寫本頁) 本紙張尺度遍用中國國家標準（CNS ) Α4規格（210X297公釐） 4347 1 2 5 7 4 6twf . doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（；） 在金屬矽化物中又以矽化鈦（TiSi2)金屬的窄線效應更爲嚴 重。簡而言之，多晶矽的線寬越小，則自行對準鈦金屬矽 化物的電阻越高。 其另一缺失爲摻質效應（Dopant Effect):由於砷或磷 的原子半徑較矽大，在金屬矽化反應中會阻礙金屬與矽的 .接近，而造成金屬與矽的反應不完全，在0.18微米的N+ 多晶矽中會得到較高的片電阻。 其再另一缺失爲：在源極、汲極的表面與閘極表面 所形成之自行對準金屬矽化物層只受到間隙壁的阻隔，若 是金屬去除不完全，則容易在閘極與源極間以及閘極與汲 極間發生橋樑連接（Bridging)的現象。 因此，本發明的目的之一就是在提供一種自行對準 金屬矽化物的製程，可避免摻質效^的發生。 因此，本發明的另一目的就是在提供一種自行對準 金屬矽化物的製程，可避免在閘極與源極間以及閘極與汲 極間發生橋樑.連接的現象。 根據本發明之上述目的，提供一種自行對準金屬矽 化物的製程，其係在一基底上形成一閘氧化層，在閘氧化 層上形成具有一第一型離子摻雜之一多晶矽層，在摻雜之 多晶矽層上形成一未摻雜之多晶矽層，在未摻雜之多晶矽 層上形成一抗反射光層，定義該抗反射光層、該未摻雜之 多晶矽層與該摻雜之多晶矽層，以形成一閘極，於閘極之 側壁形成一間隙壁，於間隙壁外之基底中，形成一源極與 一汲極，去除閘極之抗反射光層，進行一第二型離子的植 4 (請先聞讀背面之注意事項^.,.寫本頁) -5 本紙張尺度適用中國國家標準（CNS ) A4規格（2Ϊ0Χ297公釐） 434712 5746twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（>) 入步驟，最後，在源極、汲極的表面與閘極表面形成一自 行對準金屬矽化物層。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，F文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 圖式之簡單說明： 第ΪΑ圖至第1E圖係繪示本發明之一種自行對準金 屬矽化物的製程。 標號說明： 200 : 基底 202 ：淺溝渠隔離 204 :閘氧化層 206 :多晶砂層 208 ： N型離子 210 -多晶矽層 212:抗反射光層 214 ： 閘極 215:淡摻雜區. 216:間隙壁 218: N型離子 220 ：濃摻雜區 221 :源極 222 :汲極 224: P型離子 5 I I I I I I I [裝 I I I I ί 訂— I I I I 線 (請先閲讀背面之注意事項苒从寫本頁) 本紙張尺度適用中國國家標率（CNS ) A4規格（2〖〇X297公嫠） 434712 5746twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ί/) 226:自行對準金屬矽化物層 竇施例 第1A圖至第1E圖係繪示本發明之一種自行對準參 屬矽化物的製程’本發明是以N型金氧半導體爲例，但並 不限於N型金氧半導體之製作。 請參照第1A圖，提供一基底200，在基底200上幵乡 成-元件隔離結構，例如，淺溝渠隔離（Shallow Trench Isolation ’ STI)結構202 ’然後’在基底200上形成一鬧氣 化層(Gate Oxide)2〇4，接著，在閘氧化層204上沉積一賻 度約爲1500至2500埃(A)的一多晶矽層206，較佳的厚度 約爲2000埃，之後對多晶矽層206進行一離子摻雜步驟， 其摻質比如爲N型離子208，以降低多晶矽層206的電阻。 請繼續參照第1B圖，在多晶矽層206上沉積一厚度 約爲200至400埃的一未摻雜多晶矽層210，較佳的厚度 約爲300埃，然後，在未摻雜多晶矽層210上沉積一厚的 抗反射光層（Anti-Reflection Layer，ARC)212，抗反射光層 212的材質包括氮氧化矽(SiON)或氮化矽（SiN)。434712 5746twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Smart Finance Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention relates to a process technology for integrated circuits, and in particular, to a self-aligned metal silicide Process of materials. When the accumulation degree of the integrated circuit increases, the resistance of the source and the drain of the Metal Oxide Semiconductor 'MOS device is gradually increased to be equivalent to the resistance of the channel. Sheet resistance of the drain electrode and ensure that the shallow junction between the metal and the metal-oxide-semiconductor transistor is intact, in the Very Large Scale Integration (VLSI) process below 0.5 microns Gradually use a self-aligned silicide (Salicide) process to reduce the resistance of polysilicon and active area, while self-aligning titanium in a 0.25 micron process The process of silicide (CH-Salicide) is the main choice. Self-aligning metal silicide is to deposit a metal thin film on a wafer with defined gates and established spacers. At high temperatures, part of the deposited metal thin film will interact with the metal-oxide semiconductor source. The silicon on the electrode and the drain and the polycrystalline silicon on the gate react to form a low-resistance metal silicide on the surface of the silicon and polycrystalline silicon, and then the metal thin film is removed by wet etching [J (Wet Etching). When the self-aligned titanium silicide (Ti-Salicide) process is applied to processes of 0.18 microns and below, one of the missing is the Narrow Line Effect: The so-called narrow line effect is because the gate size is too large. Small, making the metal silicide grown on the gate polysilicon and the polysilicon have too much stress (Stress), or too little nucleation site (Nudeatmn Site) 'cause the metal to silicon ratio in the metal silicide has changed' As a result, the quality of the metal sanding film is not good, which increases the sheet resistance and affects the gate operation efficiency. 3 1- nn I n Order ~ line (please read the note on the back first and write the difference on this page) This paper uses the Chinese National Standard (CNS) Α4 specification (210X297 mm) 4347 1 2 5 7 4 6twf. doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (;) In metal silicide, the narrow line effect of titanium silicide (TiSi2) metal is more serious. In short, the smaller the line width of polycrystalline silicon, the higher the resistance of self-aligned titanium silicide. Another deficiency is the dopant effect: As the atomic radius of arsenic or phosphorus is larger than that of silicon, the metal and silicon will be prevented from approaching in the silicidation reaction of the metal, resulting in an incomplete reaction between the metal and silicon, at 0.18 Higher sheet resistance is obtained in micrometers of N + polycrystalline silicon. Yet another deficiency is that the self-aligned metal silicide layer formed on the surface of the source, the drain, and the gate is only blocked by the barrier wall. If the metal is not completely removed, the gate and source are easily removed. Bridging occurs between the gate and the drain. Therefore, one of the objectives of the present invention is to provide a process for self-aligning metal silicide, which can avoid the occurrence of dopant effect. Therefore, another object of the present invention is to provide a self-aligned metal silicide process, which can avoid the phenomenon of bridge and connection between the gate and the source and between the gate and the drain. According to the above object of the present invention, a process for self-aligning metal silicide is provided. A gate oxide layer is formed on a substrate, and a polycrystalline silicon layer having a first type of ion doping is formed on the gate oxide layer. An undoped polycrystalline silicon layer is formed on the doped polycrystalline silicon layer, and an anti-reflective light layer is formed on the undoped polycrystalline silicon layer. The anti-reflective light layer, the undoped polycrystalline silicon layer, and the doped polycrystalline silicon are defined. Layer to form a gate, a gap wall is formed on the side wall of the gate, a source and a drain are formed in the substrate outside the gap wall, the anti-reflective light layer of the gate is removed, and a second type ion is performed Plant 4 (Please read the precautions on the back ^.,. Write this page) -5 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2Ϊ0 × 297 mm) 434712 5746twf.doc / 006 A7 B7 Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau. 5. Inventive steps. Finally, a self-aligned metal silicide layer is formed on the source, drain, and gate surfaces. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following is a detailed description of the preferred embodiment and the accompanying drawings, as follows: Brief description of the drawings: FIG. 1E illustrates a process for self-aligning metal silicide according to the present invention. Explanation of symbols: 200: substrate 202: shallow trench isolation 204: gate oxide layer 206: polycrystalline sand layer 208: N-type ion 210-polycrystalline silicon layer 212: anti-reflective light layer 214: gate 215: lightly doped region. 216: gap Wall 218: N-type ion 220: Strongly doped region 221: Source electrode 222: Drain electrode 224: P-type ion 5 IIIIIII [Pack IIII ί Order — IIII line (Please read the precautions on the back first, from the writing page) The paper scale is applicable to China National Standards (CNS) A4 specification (2 〖〇297297） 434712 5746twf.doc / 006 A7 B7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (ί /) 226: Examples of metalloid silicide layer sinuses Figures 1A to 1E show a process for self-aligning a reference silicide according to the present invention. The present invention takes an N-type metal-oxide semiconductor as an example, but it is not limited to N-type Production of metal oxide semiconductors. Referring to FIG. 1A, a substrate 200 is provided, and a device-isolation structure is formed on the substrate 200. For example, a Shallow Trench Isolation (STI) structure 202 'is then formed on the substrate 200. (Gate Oxide) 204. Next, a polycrystalline silicon layer 206 having a thickness of about 1500 to 2500 Angstroms (A) is deposited on the gate oxide layer 204, and the preferred thickness is about 2000 Angstroms. An ion doping step, the dopant is, for example, N-type ions 208 to reduce the resistance of the polycrystalline silicon layer 206. Please continue to refer to FIG. 1B. An undoped polycrystalline silicon layer 210 is deposited on the polycrystalline silicon layer 206 to a thickness of about 200 to 400 angstroms, preferably about 300 angstroms, and then deposited on the undoped polycrystalline silicon layer 210. A thick anti-reflection light layer (ARC) 212. The material of the anti-reflection light layer 212 includes silicon oxynitride (SiON) or silicon nitride (SiN).
請繼續參照第1C圖，定義抗反射光層212、多晶矽 層210與多晶砂層206，以形成一閘極214。之後，於閘極 214外之基底200中形成一淡摻雜區215，其例如是以一離 子植入方法來形成。然後，於閛極214之側壁形成一間隙 壁216，續於間隙壁216外之基底200中進行一離子植入 步驟，其摻質比如爲N型離子218，以於基底200中形成 —濃摻雜區220，淡摻雜區215與濃摻雜區220即形成N 6 本紙張尺度適用中®國家標準（CNS ) A4規格（210X297公釐} #,IiiI-----0 一褚^"stf背'%之法秦#'^/4寫束贫〉 434712 5746twf.doc/〇〇6 A7 B7 經濟部智慧財產局貝工消費合作社印製 五、發明説明（f) 型金氧半電晶體（N-Type Metal Oxide Semiconductor ’ NMOS) 的源極221與汲極222。 請繼續參照第ID圖，去除閘極214表面之抗反射光 層212，暴露出其下方之未摻雜多晶矽層210，其例如採 用磷酸進行濕蝕刻法來去除抗反射光層212 °之後’可以 對暴露出之未摻雜多晶矽層210進行一離子植入步驟’植 入的離子例如爲P型離子224，其方法例如包括於閘極外 之基底上形成一光阻後，再進行離子植入步驟。由於摻雜 P型離子的多晶矽並不受摻質效應的影響，因此此步驟並 不影響後續步驟的進行。 請繼|買麥照第1E圖’在源極221、汲極222的表面 與閘極214表面形成一低電阻的自行對準金屬矽化物層 226 1其方法包括於基底200上形成一金屬層(未繪示），之 後進行一快速回火製程以與金氧半電晶體源極221與汲極 222上的矽以及閘極214上的多晶矽層210中的矽反應， 而在源極221、汲極222的表面與閘極214表面形成一低 電阻的自行對準金屬矽化物層226，其中金屬層例如使用 鈦金屬’而此自行對準金屬矽化物層226則例如爲矽化鈦 由於多晶矽層210不是摻雜Ρ+離子就是未摻雜離子，故在 金屬矽化反應中不會發生摻質效應，因而可降低Ν+的多 晶矽層206之片電阻。 因此，本發明的優點係提出一種自行對準金屬矽化 物的製程，在0.18微米以及0.18微米以下之ν .型金氧半 電晶體製程中，使用一未摻雜之多晶砂層或一接雜ρ型摻 7 ---------^-------訂------# (請先閱讀背面之注意事項I4'寫本頁) 本紙張尺度適用中國國家操準（CNS ) Α4说格（210Χ297公釐） 4347 1 2 5746twf . doc/006 A7 B7 五、發明説明（έ) 質之多晶矽層與鈦金屬反應，可避免摻質效應的發生，利 於自行對準矽化物的形成。 本發明的另一優點係在除去抗反射光層後，在閘極 的間隙壁中形成一凹洞，此凹洞可以增加接下來在閘極、 源極以及汲極表面所形的自行對準金屬矽化物層之間的阻 隔效果，而可避免因金屬去除不完全而在閘極與源極間以 及閘極與汲極間發生橋樑連接(Bridging)的現象。 此外本發明除了可應用於N型電晶體之製作外，還 可應用於雙閘極（Dual Gate)製程之製作。 綜上所述，雖然本發明已以較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 — I I I 1 n I I 訂 I — 線 {請先閲讀背面之注意事項KViK寫本頁) 經濟部智慧財產局員工消費合作社印製 張 一紙 本 一通 樣 家 I釐 公 7 29Please continue to refer to FIG. 1C to define the anti-reflective light layer 212, the polycrystalline silicon layer 210, and the polycrystalline sand layer 206 to form a gate electrode 214. Thereafter, a lightly doped region 215 is formed in the substrate 200 outside the gate electrode 214, which is formed by, for example, an ion implantation method. Then, a spacer 216 is formed on the side wall of the pole 214, and an ion implantation step is performed in the substrate 200 outside the spacer 216. The dopant is, for example, N-type ion 218 to form in the substrate 200—concentrated doping. The miscellaneous region 220, the lightly doped region 215, and the heavily doped region 220 form N 6 This paper is applicable to the national standard (CNS) A4 specification (210X297 mm) #, IiiI ----- 0 Yichu ^ " stf 背 '% 的 法 秦 #' ^ / 4 写 束 残》 434712 5746twf.doc / 〇〇6 A7 B7 Printed by Shelley Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Crystal (N-Type Metal Oxide Semiconductor 'NMOS) source 221 and drain 222. Please continue to refer to Figure ID, remove the anti-reflective light layer 212 on the surface of the gate 214, and expose the undoped polycrystalline silicon layer 210 below it. After removing the anti-reflective light layer 212 ° with a wet etching method using phosphoric acid, for example, an ion implantation step can be performed on the exposed undoped polycrystalline silicon layer 210. The implanted ion is, for example, P-type ion 224. For example, the method includes forming a photoresist on a substrate outside the gate, and then performing an ion implantation step. Polycrystalline silicon doped with P-type ions is not affected by the dopant effect, so this step does not affect the subsequent steps. Please continue | buy Mai according to Figure 1E 'on the surface of the source 221, the drain 222 and the gate A low-resistance self-aligned metal silicide layer 226 is formed on the surface of the electrode 214. The method includes forming a metal layer (not shown) on the substrate 200, and then performing a rapid tempering process to contact the metal-oxide semiconductor transistor source. 221 reacts with the silicon on the drain 222 and the silicon in the polycrystalline silicon layer 210 on the gate 214, and forms a low-resistance self-aligned metal silicide layer on the surface of the source 221, the drain 222, and the surface of the gate 214 226, where the metal layer is, for example, titanium metal, and the self-aligned metal silicide layer 226 is, for example, titanium silicide. Since the polycrystalline silicon layer 210 is either doped with P + ions or undoped ions, it does not occur in the metal silicidation reaction. The dopant effect can reduce the sheet resistance of the N + polycrystalline silicon layer 206. Therefore, the advantage of the present invention is to propose a process for self-aligning metal silicides. Crystal In the process, use an undoped polycrystalline sand layer or a doped p-type doped 7 --------- ^ ------- order ------ # (Please read the back first Note for I4 'write this page) This paper size is applicable to China National Standards (CNS) Α4 grid (210 × 297 mm) 4347 1 2 5746twf. Doc / 006 A7 B7 V. Description of the invention (Strand) The quality of the polycrystalline silicon layer and Titanium reaction can avoid dopant effect and facilitate self-aligned silicide formation. Another advantage of the present invention is that after removing the anti-reflective light layer, a recess is formed in the gap wall of the gate, and this recess can increase the self-alignment formed next on the surface of the gate, source and drain. The barrier effect between the metal silicide layers can avoid the phenomenon of bridging between the gate and the source and between the gate and the drain due to incomplete metal removal. In addition, the present invention can be applied not only to the production of N-type transistors, but also to the production of dual gate processes. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. — I I I 1 n I I Order I — Line {Please read the note on the back KViK first to write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs