五、發明説明（ Α7 Β7 發明领域： 經濟部中央標準局貝工消費合作社印製 本發明係有關於一種半導體元件特别是一種製造極短 通道n型金氧半場效電晶體（nMOSFET)之方法。2·發明背景： 在現今半導體技術領域’金氧半場效電晶體（MOSFET) 特别是CMOS已廣泛的被應用，並且在極超大型積體電路 (ULSI)時代，元件的尺寸也是日益縮小以達到更高的性能。 然而在元件尺寸日益縮小的同時，寄生電路像RC延遲和源 /及極間串聯電阻很容易使得電路的性能衰退。一如Μτ Takagi 寺人在’’[EDM Tech. Dig. p.4455,1996” 提出在閘極 上傳遞延遲是通道寒度和閘極片電阻的函數。因此在閘極 某一定値的片電阻値將限制可用於ULSI之最大的通道寬 度β 在源極和没極之歐米接觸（Ohmic contacts)與閘極製程 自我對準Ti矽化物對要求低的閘極片電阻阻値輿低源極和 汲極之阻値是一個不錯的選擇，製造深短通道金氧半場效 電晶體以符合高速電路卻一如Μ. Ono等人在”IEDM Tech. 018.?.119，1 99 3”所提出’’由於時下光學微影技術的限制要 定義小於Ο.ΐμπι的閘極長度是很困難的。3.發明目的及概述： --- {請先閲讀背面之注意事項再填寫本頁) --訂 線 2 本紙張尺度通用中困困家標準（CNS )六4思格（210X297公釐） 五 、發明説明（ A7 B7 經濟部中央樣準局員工消費合作社印裝 麥於上述之發明背景中，傳統的製造極短通道金氡半場 效電晶體技術有光學微影技術的瓶頸，本發明的方法提供 利用簡單的製程以製作具有自我對準矽化物接觸之極短通 道金氧半場效電晶體元仵。以下將概述如下。首先在矽基 材上長一層薄的閘極氣化層，然後以LPCVD方法沉積一無 掺雜的複晶矽屉或者非晶質珍（α-Si)膜。接著沉積一氮化物 薄膜和一 n +掺雜的複晶矽層。然後以回蝕刻（back etch)此 n +捧雜的複晶5夕廣來定義閘極。一低溫氧蒸氣製程用來將 n +摻雜的複晶矽層氧化。在此步驟此n +掺雜的複晶矽閘極 宽度可以減少到奈米的等级的尺寸。以BOE和稀釋的HF 除去複晶矽閘極上的氧化膜並且殘留之掺雜的複晶矽層當 做軍幕蝕刻氮化矽層覆蓋層。接著我們使用殘留之¢ +捧雜 的複晶矽層和氮化矽層覆蓋層當做罩幕蝕刻無摻雜的複晶 矽層以形成一極短通道閘極。其次以化學氣相沉積一磷矽 玻璃（PSG)膜沉積再以回蝕刻以形成PSG側間味壁。去除氮 化矽覆蓋層。緊接著一貴金屬或耐高溫金屬沉積於所有的 區域。高劑量的砷或磷離子佈植穿越金屬層至基材以形成 源/汲極區。接著施以兩階段快速熱退火（RTP)製程形成自我 對準矽化物接觸以製造極短通道0型金氧半場效電晶體。 4.圈式簡單説明： (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 3 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） .A.-----：___；____ .A7 ' ------—______^_ 五、發明説明（） ~ ' 一 本發明的較佳實施例將於往後之説明文字中輔以下列 圖形做更詳細的闡述： 圖1爲根據本發明之一橫截面示意圖，製程的步裸是形成一 閘極氧化層一矽基材上並且一無掺雜的複晶矽層在此閘極 氧化層上。 圖2爲根據本發明之一橫截面示意圖，製程的步寐是形成氮 化發覆蓋層在此無捧雜的複晶碎層上； 圖3爲根據本發明之一橫截面示意圖，製程的步驟是形成已 摻雜的複晶矽層在氮化矽覆蓋層上； 圖4爲根據本發明之一橫截面示意圈，製程的步樣是定義一 閉極區。 圖5爲根據本發明之一橫截面示意圖，製程的步驟是在較低 溫形成熱氧化膜在n +摻雜的複晶矽層在氬化矽覆蓋層上； 圖6爲根據本發明之一橫截面示意圖，製程的步驟是除去此 熱氧化膜然後蝕刻氮化矽覆蓋層。 圈7爲根據本發明之一橫截面示意圖，製程的步驟是用該殘 留的n +摻雜的複晶矽層當做硬式革幕，蝕刻該無掺雜複晶 矽層； 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 圖8爲根據本發明之一橫截面示意圖，製程的步骤是形成 PSG氧化侧間隙壁； 囷9爲根據本發明之一橫截面示意圈，製程的步驟是蝕刻氮 化矽覆蓋層然後濺鍍貴金屬或对高溫金屬在閘極和基材 4 本紙張尺度適用中國國家標準（CNS ) A4規相( 210X297公釐） B7 ητ· ' - ---- - _ 五、發明説明（） 上； 圏10爲根據本發明之一橫截面示意圈，製程的步驟是實施 離子佈植以形成源極和汲極區； 圈11爲根據本發明之—橫截面示意围，製程的步驟是實施 兩階段段的快速熱退火製程以形成SALICIDE和延伸的源 極和汲極區。 5·發明詳輪説明： 本發明的細節可參表圈示來加以詳細説明。本發明之目 的在提供一種方法，用以製作自我對準矽化物接鏖也短通 道η型拿氧半場效電晶體高速元件。以下將詳細説明製程 的細節如下： 參考圖1’在較隹實施例裡，首先提供一<100>晶體方 向矽單晶基材2»先形成複數個厚場氧化層（field 〇xide簡 稱FOX)區4於此矽晶上做爲元件彼此間的區隔之用。例如 POX區4可經由缉影和蝕刻步驟來蝕刻I化-矽、二氧化石夕 複合層，在去光阻、濕式清潔後，在氧蒸氣環境下以熱氧 翅濟部中央樣準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 化法（thermal oxidation)長 FOX 區 4 至約 3000-8 000 埃》FOX 區4, 一如習知技術所熟悉，其也可用複數個淺溝渠（shallow tr§jL〇ii)隔絶取代之。接著在基材2上形成一二氧化..史層6 以做爲吼極之氧化層。一般，二氧化矽層6是在含氧的氣 氛在约700- 1 1 00 eC下來形成。在本實施例裡二氧化矽層的 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消费合作社印聚 A7 —_______B7______ 五、發明説明（） ' 厚度約15-250埃。其次，二氧化矽層6也可以用饪何適當 的氧化方式和步驟來形成。 然後用低壓化學氣相沉積製程沉積一無摻雜的農 j 8沉積在F〇x區4和二氧化矽層6上。無摻雜的複晶矽 層8可用非晶石夕(amorph〇us-Siiicon)廣取代.在一較隹實施 例裡無摻雜的褶晶矽層8的厚度大約Q立q埃。然後一 標準微影和蝕刻步驟用來形成一由二氧化矽層6和無挣雜 的複晶矽層8組成之閘極矽結構。 參考醑2’ 一氧化矽層10覆蓋層覆蓋在無摻雜的複晶 5夕層8之上。在本較隹實施例裡，氮化矽層10覆蓋層的厚 度约爲1 00-2000埃。 參考圖3，一 n +摻雜的複晶矽層接著沉.積在氮化矽 層覆蓋層1 0上。在一較隹實施例裡n +摻雜的複晶矽層i 2 的厚度大約是500-3000埃》 接著如圈4所示，一閘極區12a是以光阻層當做軍幕回 姓（back etch) n +摻雜的複晶矽層12來加以定義。然後如圖 5 ’ 一低溫蒸氣氧化製程用以氧化n +摻雜的複晶矽層1 2 » 在此一氧化製程實施後，在殘餘之η +摻雜的複晶矽層12上 生長一熱氧化膜1 4。在一較隹實施例裡，低溫蒸氣氧41^製 程是在約700-900。(：下持續5-60分鐘來達成。除此之外， 低溫蒸氣氧化製程也可以用低溫乾氣製程來做。在这個步 驟下n +摻雜的複晶矽層n +摻雜的複晶矽層1 2的大小可以 6 本紙張尺度適用中國國家標率（CNS ) A4規格（210x297公釐） 裝------.訂I.：-----線 (請先閱讀背面之注意事項再填寫本頁) - 經濟部中央標準局員工消費合作社印聚 A7 B7_ __ 五、發明説明（） 減少到_米的尺度大小。 參考圈6,熱氧化膜14可由BOE或稀釋的氫氟酸溶液 和n +掺雜的複晶矽層12當做硬軍幕（hardmask)以蝕刻氮化 f層覆蓋層1Q。在一較隹實施例裡，氮化矽層覆蓋層1〇可 以用象法去除。芦漿蚀刻劑可選自cf4/o2，chf3， C^6’ SFs/He族群》接著我們使用nt捧雜的複晶矽層12 和氮化矽層]J)覆蓋層當做軍幕蝕刻無摻雜的複晶矽層8以 形成一極短通道閘極，如圈7所示。渔刻劑可選自V. Description of the invention (Α7 Β7 Field of the invention: Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Shellfish Consumer Cooperative, the present invention relates to a semiconductor device, particularly a method for manufacturing an extremely short channel n-type metal-oxide-semiconductor field-effect transistor (nMOSFET). 2. Background of the invention: In today's semiconductor technology field, metal-oxide-semiconductor field-effect transistors (MOSFETs), especially CMOS, have been widely used, and in the era of ultra-large integrated circuits (ULSI), the size of components has been increasingly reduced to achieve Higher performance. However, while the component size is shrinking, parasitic circuits such as RC delay and source / and inter-electrode series resistance can easily degrade the performance of the circuit. As in Μτ Takagi Temple in "[EDM Tech. Dig. p.4455, 1996 "proposed that the propagation delay on the gate is a function of channel coldness and gate sheet resistance. Therefore, a certain chip resistance at the gate will limit the maximum channel width β that can be used for ULSI between the source and Ohmic contacts and self-alignment of the gate process. Ti silicide is a good requirement for low gate resistance and low source and drain resistance. The choice of manufacturing deep-short-channel metal-oxide-semiconductor half-field-effect transistors to meet high-speed circuits is the same as that proposed by M. Ono et al. In "IEDM Tech. 018.?.119, 1 99 3" due to the current optical lithography It is very difficult to define the gate length less than 0.ΐμπι due to technical restrictions. 3. Purpose and summary of the invention: --- {Please read the precautions on the back before filling this page)-Alignment 2 This paper is universal in size Standards for Difficulties (CNS) 6 4 Sigma (210X297 mm) 5. Description of the invention (A7 B7 Employees' Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs printed wheat on the background of the above invention, traditional manufacturing of extremely short channel gold氡 Half-effect transistor technology has the bottleneck of optical lithography technology. The method of the present invention provides the use of a simple process to make a very short-channel metal-oxide half-effect transistor with self-aligned silicide contact. The following is summarized as follows. First, a thin gate vaporization layer is grown on a silicon substrate, and then an undoped polycrystalline silicon drawer or an amorphous silicon (α-Si) film is deposited by the LPCVD method. Next, a nitride film and an n + doped polycrystalline silicon layer. Then The gate is defined by back etching the n + doped complex crystal. A low temperature oxygen vapor process is used to oxidize the n + doped complex silicon layer. In this step, the n + doped The width of the polycrystalline silicon gate can be reduced to the nanometer size. The oxide film on the polycrystalline silicon gate is removed with BOE and diluted HF and the remaining doped polycrystalline silicon layer is used as a military curtain to etch the silicon nitride layer. Cover layer. Next, we use the remaining ¢ + doped polycrystalline silicon layer and silicon nitride layer as the mask to etch the undoped polycrystalline silicon layer to form a very short channel gate. Secondly, the chemical vapor phase A PSG film is deposited and then etched back to form a PSG side taste wall. Remove the silicon nitride coating. A precious metal or a refractory metal is then deposited in all areas. High doses of arsenic or phosphorus ions are implanted across the metal layer to the substrate to form source / drain regions. A two-stage rapid thermal annealing (RTP) process is then applied to form a self-aligned silicide contact to produce a very short channel type 0 oxymetallic half field effect transistor. 4. Brief description of the circle type: (Please read the notes on the back before filling this page). Binding. Order 3 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm). A .---- -: ___; ____ .A7 '----------______ ^ _ V. Description of the invention () ~' A preferred embodiment of the present invention will be supplemented by the following figures in the following explanatory text for more detailed Explanation: FIG. 1 is a schematic cross-sectional view according to the present invention. The step of the process is to form a gate oxide layer on a silicon substrate and an undoped polycrystalline silicon layer on the gate oxide layer. FIG. 2 is a schematic cross-sectional view according to the present invention. The process steps are to form a nitrided hair cover layer on the uncrystallized multi-crystal fragmentation layer. FIG. 3 is a schematic cross-sectional view according to the present invention. A doped polycrystalline silicon layer is formed on the silicon nitride capping layer. FIG. 4 is a schematic cross-section of a circle according to the present invention. The steps of the process are to define a closed electrode region. 5 is a schematic cross-sectional view according to the present invention. The process step is to form a thermal oxide film at a lower temperature on an n + -doped polycrystalline silicon layer on a silicon argon cover layer. FIG. 6 is a cross-sectional view according to the present invention. A schematic cross-sectional view of the manufacturing process includes removing the thermal oxide film and etching the silicon nitride coating. Circle 7 is a schematic cross-sectional view according to the present invention. The process step is to use the residual n + -doped polycrystalline silicon layer as a hard leather curtain to etch the undoped polycrystalline silicon layer; Printed by the Industrial and Consumer Cooperative (please read the precautions on the back before filling out this page). Figure 8 is a schematic cross-sectional view of the present invention. The steps of the process are to form the PSG oxidized side spacer. The cross section shows a circle. The process steps are to etch the silicon nitride coating and then sputter the precious metal or the high temperature metal on the gate and the substrate. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 phase (210X297 mm) B7 ητ · '------_ V. Description of the invention (); 圏 10 is a cross-sectional schematic circle according to the present invention, and the process step is to perform ion implantation to form source and drain regions; circle 11 is based on In the present invention, the cross-section is schematically illustrated. The process step is to implement a two-stage rapid thermal annealing process to form SALICIDE and extended source and drain regions. 5. Detailed description of the invention: The details of the invention can be described in detail by referring to the table. The purpose of the present invention is to provide a method for fabricating a self-aligned silicide interface and a short-channel n-type oxygen field half-effect transistor high-speed device. The details of the manufacturing process will be described in detail as follows: Referring to FIG. 1 ', in a comparative embodiment, a < 100 > crystal-oriented silicon single crystal substrate 2 is first provided. A plurality of thick field oxide layers (field 0xide, referred to as FOX) are formed first. The region 4 is used to separate the elements from each other on this silicon crystal. For example, the POX area 4 can be etched through the shadowing and etching steps to etch the I-Si, SiO2 composite layer. After removing the photoresist and wet cleaning, the center of the Ministry of Heat and Oxygen is used in the oxygen vapor environment. Printed by Pui Gong Consumer Cooperative (please read the notes on the back before filling this page) Thermal oxidation Long FOX zone 4 to about 3000-8 000 Angstroms "FOX zone 4, as familiar to the known technology, its It can also be replaced by a plurality of shallow troughs (shallow tr§jLoi). Next, a dioxide layer is formed on the substrate 2 as the oxide layer. Generally, the silicon dioxide layer 6 is formed in an oxygen-containing atmosphere at about 700-1 100 eC. In this example, 5 paper sizes of the silicon dioxide layer are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). Printed Poly A7, Shellfish Consumer Cooperative, Central Standards Bureau of the Ministry of Economic Affairs. _______B7______ 5. Description of the invention () About 15-250 Angstroms. Secondly, the silicon dioxide layer 6 can also be formed by any appropriate oxidation method and procedure. A low-pressure chemical vapor deposition process is then used to deposit an undoped agricultural j 8 deposited on the Fox region 4 and the silicon dioxide layer 6. The undoped polycrystalline silicon layer 8 may be widely replaced with amorphous silicon (Smorphon). In a relatively large embodiment, the thickness of the undoped pleated silicon layer 8 is about Q q q. A standard lithography and etching step is then used to form a gate silicon structure composed of a silicon dioxide layer 6 and an undoped polycrystalline silicon layer 8. The reference 醑 2 'silicon oxide layer 10 covers the non-doped polycrystalline silicon layer 8 on the cover layer 8. In this comparative example, the thickness of the cover layer of the silicon nitride layer 10 is about 100-2000 angstroms. Referring to FIG. 3, an n + -doped polycrystalline silicon layer is then deposited on the silicon nitride layer cover layer 10. In a comparative example, the thickness of the n + -doped polycrystalline silicon layer i 2 is about 500-3000 Angstroms. Then, as shown in circle 4, a gate region 12a uses a photoresist layer as a military curtain to return the name ( back etch) n + doped polycrystalline silicon layer 12 to define. Then, as shown in FIG. 5 ′, a low-temperature vapor oxidation process is used to oxidize the n + -doped polycrystalline silicon layer 1 2 »After this oxidation process is implemented, a heat is grown on the residual η + doped polycrystalline silicon layer 12 Oxide film 1 4. In a comparative example, the low temperature steam oxygen process is about 700-900. (: It takes 5-60 minutes to achieve. In addition, the low temperature steam oxidation process can also be done using a low temperature dry gas process. In this step, the n + doped complex silicon layer n + doped complex The size of the crystalline silicon layer 1 2 can be 6 This paper size is applicable to China National Standards (CNS) A4 specifications (210x297 mm) Packing ------. Order I .: ----- Line (Please read the back first Please pay attention to this page, please fill in this page)-The Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, A7 B7_ __ V. Description of the invention () Reduced to the size of _ meters. Reference circle 6, thermal oxidation film 14 can be BOE or diluted hydrogen The fluoric acid solution and the n + -doped polycrystalline silicon layer 12 are used as a hard mask to etch the nitrided f-layer cover layer 1Q. In a comparative embodiment, the silicon nitride layer cover layer 10 can be used as Method. Resin etchant can be selected from the group of cf4 / o2, chf3, C ^ 6 'SFs / He. "Then we use nt mixed polycrystalline silicon layer 12 and silicon nitride layer.] J) Overlay as the military curtain. The undoped polycrystalline silicon layer 8 is etched to form a very short channel gate, as shown by circle 7. Fisherman
SiCl4/Cl2，BC13/C12，Br2/SF6。 其次參考圖8，以化學氣相沉積一碟多玻璃 (phosphosilicate glass簡稱RSG)氧化膜』6沉積在F〇X區4 上（對pMOSFET而言則是硼梦玻璃BSG氧化膜）無择雜的複 晶梦層8與基材2上面。接著非等向性蝕法使用於pS(3氧 化膜16以形成PSG氧化側隙壁（side-wall spacer)16於閘 極8的側壁上。在本較隹實施例裡，PSG氧化膜16是當做 擴散源以形成延伸的S/；p接面（junction)以使得符合最小接 面深度的要求。 -- 如圖9所示，氮化矽覆蓋層1〇先以熱h3P〇4溶液去除。 緊接著一貴金屬或对高早金屬18(refractory metal)沉積於 所有的區域。在本較隹實施例裡贵金屬或耐高溫金屬18可 選自Ti，W，Co，Pt，Ni，Cr等金屬族群的其中之一種。 參考囷10’以閘極8和PSG侧間味壁16做爲軍幕，高 7 本紙張从適财 @ @ 雜CNS)A4itfe.( 210X297/^* ) --------丨抑衣------II-----^ (請先閱讀背面之注意事項再填商本頁) - 經濟部中央標隼局貝工消費合作社印製 A7 _____B7 五、發明説明（） 劑量的坤或鱗離子佈植穿越金屬層18至基材2以形成源/ 汲極區20 (source/drain regions)在一較隹實施例裡，離子佈 植的能量約 5-1 50 keV，劑量約 5χ 1 〇14-5x 1 016i〇ns/cm2。 參考圖1卜爲了形成自我對準矽化物接觸22 (salicided contact)與延伸源/汲極接面24，接著施以兩階段快速熱退 火（RTP)製程。第一段的RTP製程是用來形成金屬矽化物在 閘極8的上面。在本較隹實施例裡，第_道的RTP製程的 溫度約300-700。(：，時間约30-180秒《任何未反應的金屬 將被蚀刻而僅閘極8，源極和汲極區20上面留下金屬矽化 物22然後第二道的RTP製程是用來將在PSG側間隙堃16 的雜質趕入延伸的源極和汲極區接面24。在本較隹實施例 裡，第二道的RTP製程的溫度約700-1 150 °C，時間約ΙΟ-ΐ 0 0 秒。 .本發明的優點是（1)自我對準矽化物接觸方法製造極短 通道η型金氧半場效電晶體之製程可用時下的微影轚程技 術來遠成；並且（2)延伸的源坧/辺*&菡接面可以以PSG當做 擴散源來改善短通道效應》 以上所述僅爲本發明之較佳實施例而已，並非用以限定 本發明之申請專利範園；凡其它未脱離本發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專 利範圍内。例如，本發明之方法提到自我對準矽化物接觸 方法製造深短通道η型金氧半場效電晶體之製程也同樣適 8 本紙张尺度適用中國國家標率（CNS > Α4规格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝' 訂 绂 A7 _B7_ 五、發明説明（） 用於P型金氧半場效電晶體之製程而PSG則代換以BSG， 另外互補式金氧半場效電晶體之製程也同時包括在内。 --------'—裝------.訂-------線 (請先閱讀背面之注意事項再填艿本頁) ~ ' 經濟部中央標準局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）SiCl4 / Cl2, BC13 / C12, Br2 / SF6. Secondly, referring to FIG. 8, a chemical vapor deposition of a plate of phosphosilicate glass (RSG) oxide film “6 is deposited on the FOX region 4 (for pMOSFET, it is a boron dream glass BSG oxide film). The multiple crystal dream layer 8 is on the substrate 2. Next, an anisotropic etching method is used for pS (3 oxide film 16 to form a PSG oxide side-wall spacer) 16 on the sidewall of the gate electrode 8. In this comparative example, the PSG oxide film 16 is Used as a diffusion source to form an extended S /; junction to meet the minimum junction depth requirement.-As shown in Figure 9, the silicon nitride capping layer 10 is first removed with a hot h3P04 solution. Next, a noble metal or refractory metal 18 is deposited in all areas. In this comparative example, the noble metal or refractory metal 18 may be selected from the metal groups such as Ti, W, Co, Pt, Ni, Cr, etc. Refer to 。10 'with gate 8 and PSG side wall 16 as the military curtain, high 7 papers from Shicai @ @ 杂 CNS) A4itfe. (210X297 / ^ *) ----- --- 丨 Yi ------ II ----- ^ (Please read the precautions on the back before filling out this page)-Printed by A7 __B7, Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Description of the Invention () A dose of Kun or squama ion implantation passes through the metal layer 18 to the substrate 2 to form source / drain regions 20. In a comparative example, the energy of ion implantation The amount is about 5-1 50 keV, and the dose is about 5χ 1 014-5x 1 016 oons / cm2. Referring to FIG. 1B, in order to form a salicided contact 22 and an extended source / drain interface 24, a two-stage rapid thermal annealing (RTP) process is performed. The first RTP process is used to form a metal silicide on the gate 8. In this comparative example, the temperature of the RTP process of the first lane is about 300-700. (:, The time is about 30-180 seconds "any unreacted metal will be etched and only the gate 8, the metal and silicide 22 are left on the source and drain regions 20 and then the second RTP process is used to The impurities of the PSG side gap 堃 16 drive into the extended source and drain junction 24. In this comparative example, the temperature of the second RTP process is about 700-1 150 ° C, and the time is about 10-ΐ 0 0 seconds. The advantages of the present invention are (1) the self-aligned silicide contact method for manufacturing an extremely short channel n-type metal-oxide half-field effect transistor can be made using current lithography process technology; and (2) ) The extended source 坧 / 辺 * & 菡 interface can use PSG as a diffusion source to improve the short channel effect. "The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention. ; All other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of the following patent applications. For example, the method of the present invention refers to the self-aligned silicide contact method to produce deep The process of the short channel η-type metal oxide half field effect transistor is also suitable for 8 papers. The scale is applicable to China's national standard (CNS > A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page). Binding A7 _B7_ V. Description of the invention () For P-type metal oxygen half field The process of the effect transistor is replaced by PSG, and the process of the complementary metal-oxide half field effect transistor is also included. --------'— 装 ------. Order- ------ line (please read the notes on the back before filling this page) ~ 'The paper size printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)