KR101044467B1 - Titanium silicide forming method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming titanium silicide of a semiconductor device, wherein titanium silicide is formed in an amorphous state using polysilicon and titanium, and then the amorphous silicon is changed to crystalline polysilicon through laser annealing to give a line width of 0.25 μm or less. It is characterized by the fact that it is possible to form titanium silicide in the device of, thus reducing the resistance of the gate resistance of the semiconductor device and the contact resistance between the source and the drain region, especially in the case of using a mixture of conventional cobalt and titanium Titanium silicides can be formed using a single titanium material, which has the advantage of reducing the complexity of the process according to the product.

Description

Titanium silicide forming method of semiconductor device

The present invention relates to a method for forming titanium silicide of a semiconductor device, and more particularly, to enable silicide to be formed using polysilicon and titanium in a device having a line width of 0.25 μm or less, thereby reducing the resistance and contact resistance of the gate. A method for forming titanium silicide in a semiconductor device.

As the design rule is miniaturized due to high integration of semiconductor devices, the width of the gate gate of the transistor and the size of the contact are reduced, so that silicide ( salicide process has been developed.

The silicide process is an abbreviation of 'self aligned silicide'. After forming the gate electrode, the source / drain and the LDD spacer when forming the MOS transistor, the group 8 group is used to lower the resistance of the source / drain region and the gate wiring of the transistor element. After depositing metal (Ni, Co, Pt, etc.) or Ti, an annealing process is performed to react with silicon and the metal material and to remove the non-reacted metal, that is, the region except the source / drain and the top of the gate. Refers to a series of processes for removing metals by wet etching.

1 is a cross-sectional view showing a semiconductor device formed by a silicide formation method according to the prior art.

As shown in FIG. 1, the gate oxide film 220 and the gate electrode 230 sequentially formed on the semiconductor substrate 210, both sidewalls of the gate electrode 230, and a part of the surface of the semiconductor substrate. A spacer 240 formed at the upper portion, source / drain regions 250 formed at the lower left and right sides of the gate electrode 230, and silicide 260 formed at the gate electrode 230 and the source / drain regions 250. It consists of.

Here, the silicide 260 is low thermal stability (agglomeration) by the subsequent heat treatment not only increases the contact resistance (sheet resistance) and sheet resistance (sheet resistance) of the source / drain region 250, There is a problem in that the junction leakage property is deteriorated due to the diffusion of metal atoms. Accordingly, titanium silicide and cobalt silicide, which have high stability at low temperatures and low resistivity, are most widely used.

In general, titanium is used up to a line width of 0.25um, and cobalt is generally used at line widths below that. There are various reasons for using titanium and cobalt separately depending on the line width. However, materials are used differently depending on the presence or absence of phase transition of the crystal structure in the line width. That is, when the line width of titanium is less than 0.2um in TiSi ₂ structure on the C49 is not a phase transition to TiSi ₂ structure on the C54. The reason is that no phase transition occurs because the particle size of the polysilicon deposited to reduce the general resistance is smaller than the line width of 0.2 um.

Accordingly, although titanium silicide has high stability and low resistivity at high temperature, cobalt silicide having a small dependency on gate line width is mainly used in semiconductor devices having a 0.25 μm-class design rule.

Accordingly, the present invention is to solve the above-described problems, it is possible to form a silicide using polysilicon and titanium in a device having a line width of 0.25㎛ or less to reduce the contact resistance between the gate resistance and the source / drain region It is an object of the present invention to provide a method for forming titanium silicide of a semiconductor device.

In order to achieve the above object, the present invention comprises the steps of depositing amorphous silicon on a semiconductor substrate, and patterning it by a photolithography process to form a gate electrode; Forming a spacer on a sidewall of the gate electrode and forming a source / drain region of a lightly doped drain (LDD) structure through an ion implantation process; Depositing Ti / TiN on the gate electrode and source / drain regions; Subjected to a primary anneal by the step of annealing was subjected to the following secondary forming TiSi ₂ in the C49 structure forming the TiSi _2, TiSi ₂ of the C49 structure with a C54 structure; And performing laser annealing to transform amorphous silicon into crystalline polysilicon.

The present invention is characterized in that the polysilicon deposition is carried out at 500 ~ 580 ℃.

In addition, the present invention is characterized in that the laser annealing is carried out at a temperature range of 620 ~ 1020 ℃.

Furthermore, the present invention further includes the step of implanting N-type ions into the gate electrode or source / drain region before the primary annealing or after the secondary annealing.

The N-type ion is characterized in that the implantation of P + ions.

In the method for forming titanium silicide of the semiconductor device according to the present invention, titanium silicide is formed in an amorphous state using polysilicon and titanium, and then the amorphous silicon is changed to crystalline polysilicon through laser annealing, so that the device has a line width of 0.25 μm or less. It is possible to form titanium silicide at. Therefore, it is possible to reduce the resistance of the gate of the semiconductor device and the contact resistance between the source and the drain region, and in particular, in the case of using a mixture of cobalt and titanium, titanium silicide may be formed using a single titanium material. The complexity of the process can be eliminated.

Hereinafter, the configuration and operation of the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views of semiconductor devices by processes for explaining a method of forming titanium silicide of a semiconductor device according to an embodiment of the present invention.

The present invention forms titanium silicide in an amorphous state using polysilicon and titanium, and then changes the amorphous silicon to crystalline polysilicon through laser annealing to form titanium silicide 170 even in devices having a line width of 0.25 μm or less. Its features are that it makes it possible.

To this end, the method of forming the titanium silicide 160 of the semiconductor device according to the present invention comprises depositing amorphous silicon on the semiconductor substrate 110, patterning it by a photolithography process to form a gate electrode 130, the Forming a spacer 140 on sidewalls of the gate electrode 130, and forming a source / drain region 150 having a lightly doped drain (LDD) structure through an ion implantation process, the gate electrode 130 and the source / depositing a Ti / TiN on the drain region 150, subjected to the primary annealing and which form a TiSi ₂ of the C49 structure, and then subjected to secondary annealing for forming the TiSi ₂ of the C49 structure with TiSi ₂ of the C54 structure And laser annealing to transform the amorphous silicon into crystalline polysilicon.

Referring to FIG. 2A, in more detail, in the present invention, polysilicon is first deposited on the semiconductor substrate 110 at a temperature of 580 ° C. or lower, and patterned by a photolithography process to form an amorphous silicon gate electrode 130. Forming a spacer 140 on sidewalls of the gate electrode 130, and forming a source / drain region 150 having a lightly doped drain (LDD) structure through an ion implantation process.

In general, the polysilicon deposition process includes polysilicon for forming the gate electrode 130 on the semiconductor substrate 110 on which a shallow trench isolation (STI) type isolation layer is formed, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition): Hereinafter referred to as LPCVD). In this case, prior to depositing polysilicon, an oxide layer 120 for forming a gate insulating layer may be formed on the semiconductor substrate 110.

In this case, according to the present invention, it is very important to deposit polysilicon at a temperature of 580 ° C. or less during the polysilicon deposition process. This is because crystalline polysilicon is deposited when the temperature at the time of deposition of polysilicon exceeds 580 ° C. When crystalline polysilicon is deposited, it is difficult to form TiSi ₂ having a C54 structure even by annealing as suggested in the conventional problem. Therefore, amorphous silicon is not formed by depositing polysilicon at a temperature of 580 ° C. or lower. It is desirable to form vaginal silicon. More preferably, the polysilicon is deposited at a temperature of 500 to 580 ° C. If the deposition temperature is less than 500 ℃ there is a problem that the deposition of polysilicon is not made smoothly. As described above, the deposition of polysilicon to form amorphous silicon forms a Ti54 structure having a C54 structure through an annealing process described later, and then changes the structure of amorphous silicon into crystalline polysilicon through laser annealing, and has a line width of 0.25 μm or less. In order to enable the formation of the titanium silicide 160 also.

After polysilicon deposition, it is patterned through a conventional photolithography process to form the amorphous silicon gate electrode 130. Although not shown in the drawing, the photolithography process is performed by exposing and developing a photoresist on polysilicon, followed by exposure and development using an exposure mask defining a gate to form a photoresist pattern covering the gate electrode region, and protecting with a photoresist pattern. The gate electrode is formed by removing the gate forming polysilicon and the gate insulating film forming oxide film by anisotropic etching such as dry etching.

When the formation of the gate electrode 130 is completed, self-alignment is performed on the gate electrode 130 by injecting P-type impurities such as boron ions at low concentration in the case of an N-channel MOS transistor as an insulating material. Forming a low concentration source / drain region. Then, a spacer 140 is formed on the sidewall of the gate electrode 130 by depositing silicon nitride with an insulating material on the front surface and dry etching the same. After the process, a high concentration of ions are implanted to form a high concentration source / drain region which is self-aligned to the spacer 140. As a result of the above process, source / drain regions 150 of LDD (Lightly Doped Drain) structures are formed. In this case, the source / drain annealing that is typically performed in the process of forming the source / drain region 150 may be performed by laser annealing.

Formation of the source / drain region 150 is completed, and as shown in FIG. 2B, Ti / TiN is deposited on the gate electrode 130 and the source / drain region 150.

In this case, a cleaning process may be performed before depositing the Ti / TiN. For example, it is possible to form high quality titanium silicide by performing a process of removing the native oxide film formed on the active region of the semiconductor substrate 110 with dilute hydrofluoric acid solution. Thereafter, Ti / TiN is deposited on the semiconductor substrate 110 to form a Ti metal layer 170. Deposition may be performed by plasma vapor deposition (PVD) or chemical vapor deposition (CVD) using plasma.

After the Ti deposition is completed, the first and second annealing process is performed to form TiSi ₂ having a C54 structure so that titanium silicide may be formed on the gate electrode 130 and the source / drain region 150. . Even if 2c with reference to Figure 2d, first, the first subjected to an annealing to form a TiSi ₂ (180) of the C49 structure, since two of the TiSi ₂ (180) C54 structure of the C49 structure subjected to primary annealing TiSi ₂ (190 ) Formed.

The first annealing is carried out at a low temperature, usually annealing at 750 ~ 850 ℃ to remove the unreacted titanium. Upon completion of the primary annealing, TiSi ₂ 180 on C49 is formed. Secondary annealing is carried out at a somewhat high temperature of about 850 ~ 950 ℃, this results in the formation of TiSi ₂ (190) of a low resistance C54 phase.

At this time, the removal of titanium that did not react after the first annealing can be removed using an etching solution in which H ₂ O, H ₂ O ₂ , and NH ₄ OH are mixed at a ratio of 5: 1: 1.

After the formation of TiSi ₂ 180 on C54 is completed, laser annealing is performed as shown in FIG. 2E to transform amorphous silicon into crystalline polysilicon to finally obtain desired titanium silicide 160.

The laser annealing process is performed to change amorphous silicon into crystalline polysilicon, and is preferably annealed at 620 to 1020 ° C. to induce a change in crystal structure.

In this case, the present invention may further include implanting N-type ions into the gate electrode or source / drain region before the first annealing or after the second annealing.

The N-type ion implantation step is to reduce the resistance inside the polysilicon, in one embodiment of the present invention was implanted with phosphorus ions (P +), for example 1E15 ~ 1E16 implanted under the conditions of 15 ~ 30keV .

Although the present invention has been described on the basis of the preferred embodiments shown in the drawings, the present invention is not limited to the above embodiments and can be practiced in various modifications and variations within the scope not departing from the technical gist of the present invention. It is obvious to those of ordinary skill in the art.

1 is a cross-sectional view showing a semiconductor device formed by a silicide formation method according to the prior art.

2A through 2E are cross-sectional views of semiconductor devices by processes for explaining a method of forming titanium silicide of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

110: semiconductor substrate

120: oxide film

130: gate electrode

140: spacer

150: source / drain area

160: titanium silicide

Claims (5)

Depositing amorphous silicon on the semiconductor substrate and patterning the same by using a photolithography process to form a gate electrode; Forming a spacer on a sidewall of the gate electrode and forming a source / drain region of a lightly doped drain (LDD) structure through an ion implantation process; Depositing Ti / TiN on the gate electrode and source / drain regions; Subjected to a primary anneal by the step of annealing was subjected to the following secondary forming TiSi ₂ in the C49 structure forming the TiSi _2, TiSi ₂ of the C49 structure with a C54 structure; And And performing laser annealing to deform amorphous silicon into crystalline polysilicon. The method according to claim 1, The polysilicon deposition is titanium silicide forming method of a semiconductor device, characterized in that carried out at 500 ~ 580 ℃. The method according to claim 1 or 2, The laser annealing is titanium silicide forming method of a semiconductor device, characterized in that performed at a temperature range of 620 ~ 1020 ℃. The method according to claim 1 or 2, And implanting N-type ions into the gate electrode or source / drain region before the first annealing or after the second annealing. The method according to claim 4, The N-type ion is a titanium silicide forming method of a semiconductor device, characterized in that for implanting P + ions.

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