經濟部智慧財產局員工消費合作社印製 561506 A7 — B7 五、發明説明（） 發明領域： 本發明係有關於一種金氧半場效電晶體（M0SFET)的 製造方法。特別是有關於一種應用鑲嵌製程（Damascene Process)和後形成輕摻雜汲極（Ught Doped Drain ; LDD)之 金氧半場效電晶體的製造方法。 發明背景： 近年來’半導體產業蓬勃發展，積體電路如今已發展 到超大型積體電路（Ultra Large Scale Integrated Circuit , ULSI)的領域。為了追求更高密度、高速度以及低功率消 耗的積體電路，金屬氧化物半導體元件必須不斷的縮小。 Ik著半導體元件積集度的增加，短通道效應亦愈嚴重，於 是各種不同的金氧半場效電晶體被提出來解決短通道效 應（short channel effect)的問題，其中形成輕摻雜汲極區 便是一相當普遍的方法。另一方面，閘極長度攸關著金屬 氧化物半導體元件的縮小化，特別是在進入〇.〇9微米以 下的製程後’超小的閘極長度大幅增加了微影 (Lithography)製程的負擔。 習知之金氧半場效電晶體的製造方法通常係在形成閘 極氧化層後，便進行多晶矽（p〇ly_ Si)閘極的沉積。以微影 和姓刻製程形成多晶石夕閘極圖案（Pattern)之後，先形成輕 摻雜汲極區，然後形成間隙壁（Spacer)於多晶矽閘極上， 以防止多晶矽閘極在後續之形成源極/汲極重摻雜區時，受 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ................裝.........、訂.........^ (請先閲讀背面之注意事項再填寫本頁) 561506 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 到離子植入（Ion Implantation)的損傷。形成源極/汲極重摻 雜區之後’再進行源極/及極快速熱回火（R a p i d T h e r m a 1 Anneal ; RTA)，藉以將非晶矽表面恢復成原來的結晶狀 態。習知之金氧半場效電晶體（MOSFET)的製造方法有下列 的缺點：間隙壁的精密度與光滑度要求高，否則無法防止 多晶矽閘極受到離子植入的損傷；源極/汲極快速熱回火 時’其中之高溫會使易使摻雜質擴散，而不易維持較淺的 fe摻雜及極區，因而失去改善短通道效應的功能；形成超 小閘極長度時’微影製程的負擔加重，大幅增加製程的困 難度與成本。 因此，非常迫切需要發展出一種金氧半場效電晶體 的製造方法，可以有效地形成輕摻雜汲極區，減少形成超 小閘極長度時微影製程的負擔，防止多晶矽閘極受到離子 植入的損傷，以減少製造上的困難度和提高金氧半場效電 晶體之閘極的品質。 發明目的及概述： #於上述之發明背景中，習知之金氧半場效電晶體的 製造方法不易形成較淺的輕摻雜汲極區、超小閘極長产， 且易使閘極受到損傷。 經濟部智慧財產局員工消費合作社印製 因此，本發明之-目的為提供一種金氧半場效電晶體 的製造方法，先形成源極/汲極重摻雜區，進行源極/汲極快 速熱回火後，再形成輕摻雜沒極區，藉以形成較淺的輕播 雜〉及極區’而可改善短通道效應。 經濟部智慈財產局員工消費合作社印製 561506 、發明説明（） :發月之再一目的為提供一種金氧半場效電晶體的製 以 *中形成以襯犧牲層包住的多晶矽閘極結構，藉 斂衫製程的負擔較輕鬆來形成超短的閘極長度。 ▲ 么月之又一目的為提供-種金氧半場效電晶體的製 =、另：’其中在多晶矽閘極形成之後，僅須進行形成輕摻 :員：5區的步驟，藉以無需製作間隙壁便可避免閘極受 妒據本《明之上述目的，因此本發明提供-種金氧半 ;效：晶體的製造方法，此製造方法至少包括：提供一基 芦，/、中在基材上已依序形成有閘極氧化層和閘極材料 ^且在閘極聽層和問極材料層的側壁（SidewaH)上形成 °襯犧牲層，閘極襯犧牲層的兩側形成有填充犧牲 ’而在閘極材料層的兩側之基材中形成有一源極/汲極重 :雜區’·進行問極摻雜的步驟，藉以將問極材料層轉變成 '極推雜層；依序去除填充犧牲層和襯犧牲層；以及進行 摻雜、及極的步驟，葬 八 , 糟以刀別在基材上之閘極摻雜層的兩側 形成摻雜汲極區。 另外’本發明之製造方法可至少包括：提供一基材， 其中此基材已定義有P井區和N井區，而p井區與N井區 之間和其不相鄰的兩端係以複數個隔離區相分隔，此基材 /成有、、S止層和犧牲層；依序去除部分之犧牲層和部 止層，以疋義出第一閘極犧牲層與一第一閘極終止 ;P井區上，和一第二閘極犧牲層與一第二閘極終止層 .............裝.........訂.........線 (請先閲讀背面之注意事項再場寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 561506 A7 — B7 V. Description of the Invention () Field of the Invention: The present invention relates to a method for manufacturing a metal oxide half field effect transistor (MOSFET). In particular, it relates to a method for manufacturing a gold-oxygen half field-effect transistor using a damascene process and then forming a lightly doped drain (Ught Doped Drain; LDD). BACKGROUND OF THE INVENTION: In recent years, the semiconductor industry has boomed, and integrated circuits have now developed into the field of ultra large scale integrated circuits (ULSI). In order to pursue integrated circuits with higher density, higher speed, and lower power consumption, metal oxide semiconductor devices must be continuously reduced. As Ik increases the concentration of semiconductor elements, the short-channel effect becomes more serious. Therefore, various metal-oxide-semiconductor field-effect transistors have been proposed to solve the problem of short channel effect, in which a lightly doped drain region is formed. This is a fairly common method. On the other hand, the gate length is related to the reduction of metal oxide semiconductor devices, especially after entering the process below 0.09 micrometers. 'Ultra-small gate length greatly increases the burden of Lithography process . A conventional method for manufacturing a metal-oxide half-field effect transistor is generally performed after depositing a gate oxide layer and then depositing polycrystalline silicon (polly_Si) gates. After the polycrystalline silicon gate pattern is formed by the lithography and surname engraving process, a lightly doped drain region is formed first, and then a spacer is formed on the polycrystalline silicon gate to prevent the subsequent formation of the polycrystalline silicon gate. When the source / drain region is heavily doped, the paper size is subject to the Chinese National Standard (CNS) A4 specification (210X297 mm) .... ....., order ......... ^ (Please read the notes on the back before filling this page) 561506 A7 B7 V. Description of the invention () (Please read the notes on the back before filling in this Page) to Ion Implantation. After the source / drain re-doped region is formed, the source / and extremely rapid thermal tempering (Rapid d T h e r m a 1 Anneal; RTA) is performed to restore the surface of the amorphous silicon to the original crystalline state. The conventional manufacturing method of metal-oxide-semiconductor field-effect transistor (MOSFET) has the following disadvantages: the precision and smoothness of the spacer wall are high, otherwise the polycrystalline silicon gate cannot be prevented from being damaged by ion implantation; the source / drain is rapidly heated During tempering, 'the high temperature will make it easy to diffuse the dopants, and it is difficult to maintain the shallower Fe doping and polar regions, thus losing the function of improving the short channel effect; when forming an ultra-small gate length, the lithography process' The burden is increased, which greatly increases the difficulty and cost of the process. Therefore, it is very urgent to develop a method for manufacturing a metal-oxide half-field-effect transistor, which can effectively form a lightly doped drain region, reduce the burden of the lithography process when forming an ultra-small gate length, and prevent the polycrystalline silicon gate from being ion-implanted. In order to reduce the manufacturing difficulty and improve the quality of the gate electrode of the metal oxide half field effect transistor. Purpose and summary of the invention: #In the above background of the invention, the conventional manufacturing method of gold-oxygen half field effect transistors is not easy to form shallower lightly doped drain regions, long production of ultra-small gates, and easy damage to the gates . Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, the purpose of the present invention is to provide a method for manufacturing a metal-oxygen half field effect transistor, firstly forming a source / drain heavily doped region, and performing rapid source / drain heating. After tempering, a lightly doped non-polar region is formed to form a shallower light-doped region and a polar region, which can improve the short channel effect. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 561506, Description of Invention (): Fayuezhi's other purpose is to provide a polycrystalline silicon gate structure with a metal oxide half field effect transistor formed by a sacrifice layer. It is easier to form the ultra-short gate length by taking the burden of the shirt manufacturing process. ▲ Another purpose of Moyue is to provide-a kind of gold-oxygen half field effect transistor system =, another: 'where after the polycrystalline silicon gate is formed, only the light doping step: member: 5 steps are needed, so that there is no need to make a gap The wall can prevent the gate from being jealous. According to the above-mentioned purpose of the present invention, the present invention provides-a kind of gold and oxygen half; effect: a method for manufacturing crystals, this manufacturing method at least includes: providing a base reed, A gate oxide layer and a gate material have been sequentially formed and a sacrificial lining sacrificial layer is formed on the side wall (SidewaH) of the gate listening layer and the interrogating material layer, and a sacrificial filling sacrificial layer is formed on both sides of the sacrificial layer of the gate lining. A source / drain weight is formed in the substrates on both sides of the gate material layer: a hetero region '. The step of interrogating doping is performed to transform the interlayer material layer into a' polar doping layer '; Removing the filling sacrificial layer and the lining sacrificial layer; and performing the doping and polarizing steps, and then forming doped drain regions on both sides of the gate doped layer on the substrate. In addition, the manufacturing method of the present invention may include at least: providing a substrate, wherein the substrate has been defined with a P-well area and a N-well area, and the p-well area and the N-well area and its non-adjacent ends are It is separated by a plurality of isolation regions, and the substrate / former, S stop layer, and sacrificial layer are sequentially removed, and a part of the sacrificial layer and the stop layer are sequentially removed to define a first gate sacrificial layer and a first gate. Pole termination; on the P well area, and a second gate sacrificial layer and a second gate termination layer ............. install ... ....... line (please read the notes on the back before writing this page)
561506 五、發明説明（） 於N井區上，進行源極’汲極重摻雜的步驟，藉 形成N +源極/汲極重 任暴材上 填充犧牲層至完全：蓋？ 源極/… 層和部分之基材牲層、該第二問極犧牲 /、中位於基材上之填充犧牲層的高度高 於或等於第一閘極犧牲層和第二閘極犧牲層；進行化 械研磨⑽⑽ icalMechanicalpolishing;CMP)的步驟，以 平坦化填充犧牲層至約暴露出第一間極犧牲層和第二問極 犧牲層，進订钱刻步驟，以去除第一間極犧牲層、第二問 ★犧牲4帛閘極終止層和第二閘極終止層，而暴露出 第一閘極開口和第-代鬥 . 一’極開’共形地（Conformal)形成襯 犧牲層來覆蓋第一閘極開口和第二閘極開口的側壁 (SidewaU)與底部’和填充犧牲層；回姓（Ε_Β_概犧牲 層，以去除位於填充犧牲層i m極開口與第二問 極開口之底部上的襯犧牲層；進行閘極氧化（GMe 〇xidati〇n) 的步驟，以分別形成第一閘極氧化層於第一閘極開口之底 部上，和第二閘極氧化層於第二閘極開口之底部上；沉積 閘極材料填充層至填滿第一閘極開口與第二閘極開口，並 覆蓋填充犧牲層；進行第二化學機械研磨的步驟，以平坦 化閘極材料填充層至約暴露出填充犧牲層，而形成第一閘 極材料層和第二閘極材料層；進行閘極摻雜的步驟，藉以 由第一閘極材料層和第二閘極材料層形成N+閘極摻雜層和 P閘極b雜層’依序去除填充犧牲層和剩餘的襯犧牲層； 進行輕摻雜汲極的步驟，藉以分別在基材上之第一閘極材 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公楚) 11 f 11裝 * — (請先閲讀背面之：/i意事項再場寫本頁) -、v" 線 經濟部智慧財產局員工消費合作社印製 561506 A7 B7 五、發明説明（ (請先閲讀背面之注意事項再填寫本頁) 料層和第二閘極材料層的兩側形成N_輕摻雜汲極區和p-輕 摻雜汲極區；分別形成複數個間隙壁於N+閘極摻雜層和P + 閘極摻雜層的四周；以及分別形成複數個金屬矽化物 (Salicide)層於N+閘極摻雜層與P+閘極摻雜層的上部分，和 N+源極/汲極重摻雜區與p +源極/汲極重摻雜區上。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1 A圖至第1 R圖為繪示本發明之金氧半場效電晶 體的製造方法之剖面流程示意圖。 圖號對照說明： 12 基材 14 終止層 1 4 a、1 4 b 閘極終止層 18 犧牲層 18a、18b 閘極犧牲層 20a、 20b、 20c 隔離區 30 、 40 井區 32 > 42 源極/汲極重摻雜區 3 4' 44 閘極開口 經濟部智慧財產局員工消費合作社印製 36 ' 46 輕摻雜汲極區 72 填充犧牲層 7 4 襯犧牲層 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 561506 A7 B7 五、發明説明（ 74a 76a 80 80a 8 1a 92 96 150 170 250 74b 76b 80b 閘極襯犧牲層 閘極氧化層 閘極材料填充層 閘極材料層 8 1 b閘極摻雜層 間隙壁 經濟部智慧財產局員工消費合作社印製 金屬石夕化物層 152 、 154 、 160 、 162 、 164 離子植入 172 回火步驟 252 、 254 、 260 、 262 、 264 光阻圖案 發明詳細說明： 本發明揭路一種金氧半場效電晶體的製造方法。此製 造方法先形成源極/汲極重摻雜區，進行快速熱回火，再應 用鑲嵌製程形成四周以襯犧牲層包住的多晶矽閘極結構， 再進行輕摻雜汲極的步驟。 請參照第1A圖至第1R圖，第1A圖至第1R圖為繪 示本發明之金氧半場效電晶體的製造方法之剖面流程示 意圖。 首先，如第1 A圖所示，本發明之製造方法提供一基 材12，而基材12上定義有井區30和井區40,其中井區30 可為例如P井（P Well)區，而井區40可為例如N井（N Well) 區。井區30與井區40之間、和其不相鄰的兩端以複數個 隔離區20a、20b和20c來相分隔，這些隔離區20a、20b (請先閲讀背面之注意事項再填寫本頁) 太紙張尺唐谪用中國國玄標進（CNS)A4规棬m〇X 297公蝥） 經濟部智慧財產局員工消費合作社印製 561506 A7 -----— .__B7_ 五、發明説明（） c 可為堯溝渠隔離（Shallow Trench Isolation ; S ΤΙ)結 另外基材1 2上更形成有終止層14和犧牲層1 8，其 終、、，；止層1 4和犧牲層丨8係分別由不同材料所製成，例如： '層14之材質可為氮化矽或氮氧化矽，而犧牲層18之 材質可為氧化矽。 然後’依序去除部分之犧牲層丨8和部分之終止層14， 以疋義出閘極犧牲層18a與閘極終止層14a於井區3〇上； 疋義出閘極犧牲層1 8b與閘極終止層14b於井區上，如 第1 B圖所示。 夹J後，如第1 C圖和第1 D圖所示，進行源極/沒極重 ，雜的步驟，藉以在基材丨2上形成源極/汲極重摻雜區3 2 彳C。其中，以光阻圖案（Photoresist Pattern)250覆蓋住 井區40，來對井區3〇進行例如N型摻雜（即n。的離子植 入丨5〇,藉以形成N型（即的源極/沒極重摻雜區32。在 去除光阻圖案250後，再以光阻圖案26〇覆蓋住井區3〇， 來對井區40進行例如p型摻雜（即p + )的離子植入16〇，藉 以形成P型（即P + )的源極/汲極重摻雜區42。去除光阻圖案 260後，如第1E圖所示，再進行回火步驟17〇，藉以將非 曰曰矽表面恢復成原來的結晶狀態。回火步驟1 7 〇可使用快 速熱回火的方法。由於此時之閘極結構係分別為由閘極犧 牲層18a與閘極終止層14a，和閘極犧牲層18b與閘極終止 層1 4 b所組成的暫時結構（將於後續的步驟中去除），故可 容許被離子植入150和160所損傷。而回火步驟17〇的溫 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ................裝.......：訂.......線 (請先閲讀背面之注意事項再場寫本頁} 561506 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（ ，雖然相當高’但由於輕摻雜汲極區尚未形成，故不會因 咼溫離子擴散而破壞輕摻雜汲極區的淺度。 然後，沉積填充犧牲層72至完全覆“極犧牲層⑴ 和m、及部分之基12，其中位於部分之基材i2上之填 充犧牲層72的高度必須高於或等於閘極犧牲層18&和 1 8b，而填充犧牲層72之材質可為氮化矽。接著，進行化 學機械研磨的步驟（未繪示），藉以平坦化填充犧牲層Μ至 約暴露出閘極犧牲層1 8 a和1 8 b，如第1 ρ圖所示。 然後，先進行蝕刻步驟，以去除閘極犧牲層丨8a和 18b、以及閘極終止層14a和14b，而暴露出閘極開口 34 和44。接著，共形地（c〇nformai)形成襯犧牲層來覆蓋 閘極開口 34和44的側壁（Sidewall)與底部，並覆蓋填充犧 牲層72，如第1 G圖所示。其中襯犧牲層74之材質可為氧 化矽。 然後，回蝕（Etch Back)襯犧牲層74的水平部分，以去 除位於填充犧牲層7 2上，和閘極開口 3 4和4 4之底部上的 襯犧牲層74，而保留有位於閘極開口 34和44四周之襯犧 牲層74的垂直部分，即閘極襯犧牲層74a和74b，其中閘 極襯犧牲層7 4 a和7 4 b的上端會受到些微的姓刻。接著， 進行閘極氧化（Gate Oxidation)的步驟，以分別形成閘極氧 化層7 6 a和7 6 b於該閘極開口 3 4和4 4之底部上，如第1 Η 圖所示。 然後，如第11圖所示，沉積閘極材料填充層8 〇至填 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公釐) ...............裝.........訂.........線 (請先閱讀背面之注意事項再填寫本頁) 561506 A7561506 V. Description of the invention () In the N-well region, perform the source ’s drain heavily doped step to form the N + source / drain heavy task. Fill the sacrificial layer to complete: cover? The source / ... layer and part of the substrate sacrificial layer, the second intervening sacrificial layer, and the filling sacrificial layer located on the substrate are higher than or equal to the first gate sacrificial layer and the second gate sacrificial layer; Performing a mechanical polishing (CMP) step, filling the sacrificial layer with a flattening layer to expose the first sacrificial sacrificial layer and the second sacrificial sacrificial layer, and performing a engraving step to remove the first sacrificial sacrificial layer Second question sacrificing 4 sacrificial gate termination layer and second gate termination layer, while exposing the first gate opening and the first-generation bucket. A 'pole-open' conformally forms a lining sacrificial layer to Cover the sidewalls (SidewaU) and the bottom of the first gate opening and the second gate opening, and fill the sacrificial layer; return the surname (Ε_Β_ almost sacrificial layer) to remove the im gate opening and the second interrogation opening located in the filled sacrificial layer. A sacrifice layer on the bottom; performing gate oxidation (GMe 〇xidati〇n) steps to form a first gate oxide layer on the bottom of the first gate opening, and a second gate oxide layer on the second On the bottom of the gate opening; Fill the first gate opening and the second gate opening and cover the filling sacrificial layer; perform a second chemical mechanical polishing step to planarize the filling layer of the gate material to approximately expose the filling sacrificial layer to form the first gate Material layer and second gate material layer; performing a gate doping step, so that an N + gate doped layer and a P gate b-hybrid layer are sequentially formed from the first gate material layer and the second gate material layer; Remove the filling sacrificial layer and the remaining lining sacrificial layer; perform the step of lightly doping the drain electrode so that the first gate material on the substrate is separately used. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297). 11 f 11 装 * — (Please read the following: / i Italian matter before writing this page)-, v " Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Online Economics 561506 A7 B7 V. Description of the invention ((Please read first Note on the back side, please fill in this page again) N_ lightly doped drain region and p-lightly doped drain region are formed on both sides of the material layer and the second gate material layer; a plurality of spacers are formed on the N + gate, respectively. Around the doped layer and the P + gate doped layer; and forming a plurality of gold, respectively A silicide layer is on the upper part of the N + gate doped layer and the P + gate doped layer, and on the N + source / drain heavily doped region and the p + source / drain heavily doped region. Brief description of the formula: The preferred embodiment of the present invention will be described in more detail in the following explanatory texts with the following figures, where: Figures 1 A to 1 R are diagrams illustrating the metal-oxygen half field effect of the present invention. A schematic cross-sectional flow chart of a method for manufacturing a transistor. Comparative illustration of drawing numbers: 12 substrate 14 termination layer 1 4 a, 1 4 b gate termination layer 18 sacrificial layer 18 a, 18 b gate sacrificial layer 20 a, 20 b, 20 c isolation region 30 , 40 well area 32 > 42 source / drain heavily doped region 3 4 '44 gate opening printed by Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative 36' 46 lightly doped drain region 72 filled with sacrificial layer 7 4 lining Sacrificial layer This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 561506 A7 B7 V. Invention description (74a 76a 80 80a 8 1a 92 96 150 170 250 74b 76b 80b Gate lining sacrificial layer gate oxidation Layer gate material filling layer gate material layer 8 1 b gate doped layer gap wall Ministry of Economic Affairs Bureau ’s consumer cooperative prints metal oxide layer 152, 154, 160, 162, 164, ion implantation 172, tempering step 252, 254, 260, 262, 264. Photoresist pattern. Detailed description of the invention: The invention uncovers a kind of metal oxide Method for manufacturing half field effect transistor. This manufacturing method first forms a source / drain heavily doped region, performs rapid thermal tempering, then applies a damascene process to form a polycrystalline silicon gate structure surrounded by a sacrificial layer, and then performs a lightly doped drain step. Please refer to FIGS. 1A to 1R. FIGS. 1A to 1R are schematic cross-sectional views illustrating a method for manufacturing the metal-oxide-semiconductor field-effect transistor of the present invention. First, as shown in FIG. 1A, the manufacturing method of the present invention provides a substrate 12, and the substrate 12 has a well area 30 and a well area 40 defined therein, where the well area 30 may be, for example, a P well area. The well area 40 may be, for example, an N Well area. The well area 30 and the well area 40 and the non-adjacent ends are separated by a plurality of isolation areas 20a, 20b, and 20c. These isolation areas 20a, 20b (please read the precautions on the back before filling this page) ) Tang Zhi, a paper ruler of China, uses China National Xuan Biaojin (CNS) A4 regulations (m0X 297). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 561506 A7 -----. .__ B7_ ) C may be a Shallow Trench Isolation (S TIL) junction. In addition, a stop layer 14 and a sacrificial layer 18 are formed on the substrate 12. The termination layer 14 and the sacrificial layer 丨 8 They are made of different materials, for example: 'The material of layer 14 may be silicon nitride or silicon oxynitride, and the material of sacrificial layer 18 may be silicon oxide. Then 'sequentially remove part of the sacrificial layer 丨 8 and part of the termination layer 14 to define the gate sacrificial layer 18a and the gate termination layer 14a on the well area 30; to define the gate sacrificial layer 18b and The gate stop layer 14b is on the well area, as shown in FIG. 1B. After clamping J, as shown in FIG. 1C and FIG. 1D, a source / non-heavy and hetero step is performed to form a source / drain heavily doped region 3 2 彳 C on the substrate 2 . The photoresist pattern 250 covers the well area 40 to perform, for example, N-type doping (ie, n. Ion implantation) 50 on the well area 30 to form an N-type (ie, source electrode). / Not very heavily doped region 32. After removing the photoresist pattern 250, the well region 30 is covered with the photoresist pattern 26o to perform, for example, ion implantation of p-type doping (ie, p +) on the well region 40. In order to form a P-type (ie, P +) source / drain heavily doped region 42, the photoresist pattern 260 is removed, and as shown in FIG. 1E, a tempering step 17 is performed, so that the non- The surface of the silicon is restored to its original crystalline state. A rapid thermal tempering method can be used in the tempering step 170. Because the gate structure at this time is composed of the gate sacrificial layer 18a and the gate termination layer 14a, and The temporary structure composed of the gate sacrificial layer 18b and the gate termination layer 1 4b (will be removed in subsequent steps), so it can be damaged by ion implantation 150 and 160. The temperature 8 in the tempering step 17o This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) .................... Order Line (please read the back first Note for rewriting this page} 561506 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (, although quite high, but because the lightly doped drain region has not yet been formed, it will not cause Diffusion destroys the shallowness of the lightly doped drain region. Then, the filled sacrificial layer 72 is deposited to completely cover the "electrode sacrificial layers ⑴ and m, and a portion of the base 12, wherein the filled sacrificial layer 72 is located on a portion of the substrate i2. The height must be higher than or equal to the gate sacrificial layer 18 & and 18b, and the material for filling the sacrificial layer 72 may be silicon nitride. Then, a step of chemical mechanical polishing (not shown) is performed to flatten the filling sacrificial layer. The gate sacrificial layers 18 a and 18 b are exposed from about M to about 1, as shown in Fig. 1. Then, an etching step is first performed to remove the gate sacrificial layers 8a and 18b, and the gate termination layers 14a and 14a. 14b, and the gate openings 34 and 44 are exposed. Then, a conformal lining sacrificial layer is formed to cover the side walls and bottom of the gate openings 34 and 44 and cover the sacrificial layer 72, such as It is shown in Fig. 1 G. In which the sacrificial layer 74 is lined The material may be silicon oxide. Then, a horizontal portion of the sacrificial sacrificial layer 74 is etched back to remove the sacrificial sacrificial layer 74 on the filling sacrificial layer 72 and the bottom of the gate openings 34 and 44. The vertical portions of the lining sacrificial layer 74 located around the gate openings 34 and 44 are retained, that is, the gate lining sacrificial layers 74a and 74b, and the upper ends of the gate lining sacrificial layers 7 4 a and 7 4 b will be slightly surnamed. engraved. Next, a gate oxidation step is performed to form gate oxidation layers 7 6 a and 7 6 b on the bottoms of the gate openings 3 4 and 4 4, respectively, as shown in FIG. 1. Then, as shown in Fig. 11, the gate material filling layer 80 is deposited to the paper size of the paper to apply the Chinese National Standard (CNS) A4 specification (210 × 297 mm) ............. ..Install ......... order ......... line (please read the precautions on the back before filling this page) 561506 A7
五、發明説明（） 和44，並覆蓋填充犧牲層72。其中閘極材 而形成閘極材料層 進行閘極摻雜的步 其中，以光阻圖案 滿閘極開 料填充層80之材質可為多晶矽（p〇iy_si) 然後，進行化學機械研磨的步驟，以平坦化閑極材料 填充層80至約暴露出填充犧牲層72 80a和80b，如第1J圖所示。 然後’如第1 K圖和第！ l圖所示 驟’藉以形成閘極摻雜層8丨a和8丨b , … Γ-α. 固 杀. 252覆蓋住井區40的上方，來對如第丨一 ，， 不耵3弗1 J圖所不之閘極材 料層80a進行例如N型摻雜（即N + )的離子植入Μ]，藉以 形成例如N型摻雜（即N + )的閘極摻雜層8u。去除光卩^圖 案252後，以光阻圖案262覆蓋住井區3〇的上方，來對 如第1J圖所示之閘極材料層8〇b進行例如p型摻雜（即 的離子植入162，藉以形成例如p型摻雜（即p + )的問極摻 雜層81b。接著，並去除光阻圖案262。 然後，依序去除填充犧牲層72和剩餘的閘極襯犧牲層 74a和74b，如第1M圖所示。值得一提的是，閘極襯犧牲 層74a和74b的寬度可決定閘極長度，亦即在定義如第 圖所示之閘極區域（如閘極犧牲層18a和18b)後，當問極概 犧牲層74a和74b的寬度愈大時，實際製得的閘極長度（即 閘極摻雜層8 1 a和8 1 b的寬度）便會愈小。換言之，本發明 可先定義較寬閘極區域，使微影製程的負擔較為輕鬆，再 經由上述之鎮欲製ί王的步驟於閘極區域上形成分別由問極 襯犧牲層7 4 a和7 4 b夾住閘極摻雜層§ 1 a和8 1 b的結構， 10 本紙張尺度適用中國國家標準(CNS)A4規格(2ι〇χ297公釐) « ![........裝.........訂.........線 (請先閲讀背面之注意事項再填寫本頁j 經濟部智慧財產局員工消費合作社印製 561506 A7 B7V. Description of the invention () and 44 and cover and fill the sacrificial layer 72. The gate material is used to form a gate material layer to perform gate doping. Among them, the material of the gate opening filling layer 80 filled with a photoresist pattern may be polycrystalline silicon (poiy_si). Then, a step of chemical mechanical polishing is performed. The filling sacrificial layer 80 is planarized to approximately expose the filling sacrificial layers 72 80a and 80b, as shown in FIG. 1J. Then ’as the 1st K picture and the first! The step shown in the figure is used to form the gate doped layers 8 丨 a and 8 丨 b,… Γ-α. The solid killer 252 covers the upper area of the well area 40 to align with the first one. The gate material layer 80a shown in FIG. 1J is subjected to, for example, N-type doping (ie, N +) ion implantation M], thereby forming, for example, an N-type doped (ie, N +) gate doped layer 8u. After removing the photoresist pattern 252, the photoresist pattern 262 is used to cover the top of the well area 30 to perform, for example, p-type doping (that is, ion implantation) on the gate material layer 80b as shown in FIG. 1J. 162, so as to form, for example, a p-type doped (ie, p +) interrogation doped layer 81b. Then, the photoresist pattern 262 is removed. Then, the fill sacrificial layer 72 and the remaining gate liner sacrificial layer 74a and 74b, as shown in Figure 1M. It is worth mentioning that the width of the gate lining sacrificial layers 74a and 74b can determine the gate length, that is, in the definition of the gate region shown in the figure (such as the gate sacrificial layer) After 18a and 18b), when the width of the interrogation sacrificial layers 74a and 74b is larger, the actual gate length (ie, the width of the gate doped layers 8 1 a and 8 1 b) is smaller. In other words, the present invention can first define a wider gate region, so that the burden of the lithography process is easier, and then through the above-mentioned steps of controlling the king, a gate lining sacrificial layer 7 4 a and Structure of 7 4 b sandwiching gate doped layer § 1 a and 8 1 b, 10 This paper size is applicable to China National Standard (CNS) A4 specification (2ι〇χ297 Li) «! [........ install ......... order ...... line (please read the precautions on the back before filling out this page j Ministry of Economy Wisdom Printed by the Property Bureau's Consumer Cooperatives 561506 A7 B7
、發明説明( 經濟部智慧財產局員工消費合作社印製 再藉由控制閘極襯犧牲 的閑極長度。 牲層74a和7則寬度，來製作超小 然後，如第1N圖釦笛！ n 步驟.. 第〇圖所示，進行輕摻雜汲極的 /驟，精以形成輕摻雜汲極區 ^ ^ 匕Μ和46。其中，以光阻圖 案254覆蓋住井區4〇 圃 的上方，來對基材12進行例如N型 擦雜（即N-)的離子植入】一 ，稭以形成例如N型摻雜（即 N )的輕摻雜汲極區3 6。名本^ ^ ^ 圖安 6在去除光阻圖案254後，以光阻 圖案264覆蓋住井區3〇的 ..,^ 的上方，來對基材12進行例如Ρ t摻雜（即ρ -)的離子拮 ^ 64 ,稭以形成例如ρ型摻雜（即 輕摻隸極區46。在去除光阻圖案264後，如第lp :所示’進行回火步驟172。回火步驟172使用快速数回 ，法。由於形成輕摻雜汲極區36和46時，源極/汲極 、摻雜區已經形成，且其後之源極/汲極回火步驟亦已完 成因此，輕摻雜及極區36和46 *會受到高溫破壞。 然後，如f 1 Q圖所#，分別形成複數個間隙壁Μ於 問極換雜層⑴和m的四周。由於所有的離子值入步驟 均已完成，此時間隙壁92僅須應用於金屬矽化的步驟，因 此，間隙壁92製作的要求可以降低，亦即可不必如習知之 間隙壁般平滑和精細。值得一提的是，閘極摻雜層8 1 &和 8 1 b的形成過程沒有遭到源極/汲極重摻雜之離子值入的損 害’因而可保持閘極的完整性。 接著，如第1 R圖所示，分別形成複數個金屬矽化物 層96於閘極摻雜層8丨a和8丨b上部分，和源極/汲極重摻 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) ...............裝.........訂.........線 (請先閲讀背面之注意事項再填寫本頁) 561506 A7 B7 五、發明說明（ 雜區32和42上。如此’便完成金氧半場效電晶體的製造。 (請先閲讀背面之注意事項再場寫本頁} 综合上述，本發明之一優點為提供一種金氧半場效電 晶體的製造方法，由於本發明係先形成源極"及極重摻雜 區’進行源極/汲極快速熱回火後，再形成輕摻雜沒極區， 故可避免高溫使換雜質擴散，因而維持較淺的輕推雜沒極 區’來改善短通道效應。 本發明之再一優點為提供一種金氧半場效電晶體的製 造：法，本發明形成以襯犧牲層包住的多晶石夕閘極結構， 使微影製程可先製作較大長度的閘極加襯犧牲層，而在去 除襯犧牲層後，便可得到超小的問極長度。故可在微影製 程的負擔相當輕鬆的情況下，製作超小的閘極長度。 本發明之又一優點為提供一種金氧半場效電晶體的製 造方法，由於本發明在多晶矽閘極形成之後，僅須進行形 成輕摻雜汲極區的步驟，其中所使用的離子植入較輕微， 故無需製作間隙壁便可避免閘極受損。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍’凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Description of the invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and then controlling the length of the idle pole sacrificed by controlling the gate lining. The widths of the animal layers 74a and 7 are made ultra-small, and then, as shown in Fig. 1N, the flute! N Steps .. As shown in FIG. 0, a lightly doped drain / step is performed to form a lightly doped drain region ^^ and 46. Among them, a photoresist pattern 254 covers the top of the well region 40. To implant N-type doping (ie, N-) ion implantation of the substrate 12] First, to form, for example, N-doped (ie, N) lightly doped drain region 36. Namebook ^ ^ ^ After removing the photoresist pattern 254, Tu'an 6 covers the well area 30 with the photoresist pattern 264 over the .., ^ to perform, for example, P t doping (ie, ρ-) on the substrate 12. ^ 64, to form, for example, p-type doping (ie, lightly doped slave region 46. After removing the photoresist pattern 264, the tempering step 172 is performed as shown in lp :. The tempering step 172 uses a rapid number of cycles, Since the lightly doped drain regions 36 and 46 are formed, the source / drain and doped regions have been formed, and the subsequent source / drain tempering steps have been completed. Therefore, the lightly doped The polar regions 36 and 46 * will be damaged by high temperature. Then, as shown in f 1 Q map, a plurality of gaps M are formed around the interlayer 杂 and m, respectively. Because all the ion input steps have been completed At this time, the spacer 92 only needs to be applied to the step of silicidation of the metal, so the requirements for the production of the spacer 92 can be reduced, that is, it does not need to be as smooth and fine as the conventional spacer. It is worth mentioning that the gate doping The formation of layers 8 1 & and 8 1 b was not damaged by the source / drain heavily doped ions, thus maintaining the integrity of the gate. Then, as shown in Figure 1 R, respectively A plurality of metal silicide layers 96 are formed on the gate doped layers 8 丨 a and 8 丨 b, and the source / drain electrodes are re-doped. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm). .............. install ......... order ......... line (please read the precautions on the back before filling this page) 561506 A7 B7 V. Description of the invention (on the miscellaneous regions 32 and 42. In this way, the fabrication of the metal-oxide half-field-effect transistor is completed. (Please read the precautions on the back before writing this page.) In summary, this One of the advantages of the invention is to provide a method for manufacturing a metal-oxide half-field effect transistor. Since the present invention first forms a source " and a very heavily doped region ' The non-polar region can avoid the high-temperature diffusion of the impurity, thereby maintaining a shallow nudge region to improve the short channel effect. Another advantage of the present invention is to provide a metal-oxygen half field-effect transistor manufacturing method: The invention forms a polycrystalline stone gate structure surrounded by a sacrificial lining sacrificial layer, so that a lithography process can first produce a gate and lining sacrificial layer of a larger length, and after removing the sacrificial lining, an ultra-small Asked pole length. Therefore, it is possible to make ultra-small gate lengths while the burden of the lithography process is relatively easy. Another advantage of the present invention is to provide a method for manufacturing a metal-oxide half field effect transistor. Since the present invention only needs to perform a step of forming a lightly doped drain region after the polycrystalline silicon gate is formed, the ion implantation used in Slight, so no need to make a spacer to avoid damage to the gate. As will be understood by those familiar with this technology, the above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application of the present invention. Effective changes or modifications should be included in the scope of patent application described below. Printed by the Consumer Goods Agency of the Intellectual Property Office of the Ministry of Economic Affairs 12 This paper is sized to the Chinese National Standard (CNS) A4 (210X297 mm)