TWI792874B - Transistor structure and manufacturing method thereof - Google Patents

Abstract

A transistor structure including a substrate, a first gate, a second gate, a first doped region, a second doped region, a source region, and a drain region is provided. The first gate and the second gate are separated from each other and disposed on the substrate. The first gate and the substrate are electrically insulated from each other. The second gate and the substrate are electrically insulated from each other. The first doped region and the second doped region are separated from each other and are located in the substrate on two sides of the first gate. The second doped region is adjacent to the second gate. The source region and the drain region are separated from each other and are located in the substrate on two sides of the first gate and the second gate. The source region is adjacent to the first gate. The drain region is adjacent to the second gate. The first doped region is located between the source region and the first gate. The second doped region continuously extends from one side the first gate to the drain region and passes directly below the second gate.

Description

Transistor structure and its manufacturing method

The present invention relates to a semiconductor structure and its manufacturing method, and in particular to a transistor structure and its manufacturing method.

The figure of merit (FOM) of a transistor device is determined by the product of the on-resistance (R _on ) and the amount of charge charged on the gate/drain (Q _gd ). In addition, the gate/drain charging charge (Q _gd ) is determined by the miller capacitance between the gate and drain. Currently, in order to improve the energy conversion efficiency of the transistor device and suppress power loss, it is necessary to reduce the figure of merit (FOM) of the transistor device. Therefore, how to effectively reduce the quality factor of transistor elements is the goal of continuous efforts.

The invention provides a transistor structure, which can effectively reduce the quality factor of transistor components.

The present invention proposes a transistor structure, including a substrate, a first gate, a second gate, a first doped region, a second doped region, a source region and a drain region. The first gate and the second gate are separated from each other and disposed on the substrate. The first gate and the substrate are electrically insulated from each other. The second gate and the substrate are electrically insulated from each other. The first doped region and the second doped region are separated from each other and located in the substrates on both sides of the first gate. The second doped region is adjacent to the second gate. The source region and the drain region are separated from each other and located in the substrate on both sides of the first gate and the second gate. The source region is adjacent to the first gate. The drain region is adjacent to the second gate. The first doped region is located between the source region and the first gate. The second doped region extends continuously from one side of the first gate to the drain region and passes directly under the second gate.

According to an embodiment of the present invention, in the above-mentioned transistor structure, part of the first doped region may be located in the substrate directly below part of the first gate.

According to an embodiment of the present invention, in the above-mentioned transistor structure, part of the second doped region may be located in the substrate directly below part of the first gate, and part of the second doped region may be located in the first gate In the substrate between the electrode and the second gate, and part of the second doped region can be located in the substrate directly below the entire second gate.

According to an embodiment of the present invention, in the above transistor structure, the gate length of the second gate can be smaller than the gate length of the first gate.

According to an embodiment of the present invention, the above transistor structure may further include a third doped region, a first well region and a second well region. The third doped region is located in the base of the source region on a side away from the first gate. The first well region is located in the substrate. The first doped region, the second doped region, the source region, the drain region and the third doped region may be located in the first well region. The second well region is located in the substrate. The first well area may be located in the second well area.

According to an embodiment of the present invention, the above transistor structure may further include a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed between the first gate and the substrate. The second gate dielectric layer is disposed between the second gate and the substrate.

According to an embodiment of the present invention, the above-mentioned transistor structure may further include a first spacer, a second spacer, and a third spacer. The first spacer and the second spacer are located on the substrates on both sides of the first gate and the second gate. The first spacer is disposed on the sidewall of the first gate. The second spacer is disposed on the sidewall of the second gate. The third spacer is disposed in the gap between the first gate and the second gate.

According to an embodiment of the present invention, in the above-mentioned transistor structure, part of the first doped region may be located in the substrate directly below the first spacer. Part of the second doped region can be located in the substrate directly below the second spacer, and part of the second doped region can be located in the substrate directly below the entire third spacer.

The invention proposes a method for manufacturing a transistor structure, which includes the following steps. Provide the base. A first gate and a second gate separated from each other are formed on the substrate. The first gate and the substrate are electrically insulated from each other. The second gate and the substrate are electrically insulated from each other. A first doped region and a second doped region separated from each other are formed in the substrate on both sides of the first gate. The second doped region is adjacent to the second gate. A source region and a drain region separated from each other are formed in the substrate on both sides of the first gate and the second gate. The source region is adjacent to the first gate. The drain region is adjacent to the second gate. The first doped region is located between the source region and the first gate. The second doped region extends continuously from one side of the first gate to the drain region and passes directly under the second gate.

According to an embodiment of the present invention, in the manufacturing method of the above-mentioned transistor structure, the forming method of the first doped region and the second doped region may include an oblique-angle ion implantation process or an oblique-angle ion implantation process and Combination of tempering processes.

Based on the above, in the transistor structure and its manufacturing method proposed by the present invention, since the second doped region continuously extends from one side of the first gate to the drain region and passes directly under the second gate, therefore The on-resistance (R _on ) can be reduced. In addition, since the second gate can be used as a split gate, the gate/drain charging charge (Q _gd ) can be reduced. In this way, the quality factor of the transistor element can be effectively reduced, thereby improving the energy conversion efficiency of the transistor element and suppressing power loss.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1E are cross-sectional views of the fabrication process of transistor structures according to some embodiments of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In addition, a well region 102 may be formed in the substrate 100 . The well area 102 may be a deep well area. The well region 102 may have a first conductivity type (eg, N type). Additionally, a well region 104 may be formed in the substrate 100 . Well area 104 may be located in well area 102 . The well region 104 may have a second conductivity type (eg, P-type). Hereinafter, the first conductivity type and the second conductivity type may be one and the other of N-type conductivity and P-type conductivity, respectively. In this embodiment, the first conductivity type is an example of an N-type conductivity type, and the second conductivity type is an example of a P-type conductivity type, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type.

Next, a gate 106 and a gate 108 separated from each other are formed on the substrate 100 . There may be a gap G between the gate 106 and the gate 108 . The gate length L2 of the gate 108 may be smaller than the gate length L1 of the gate 106 . The material of the gate 106 and the gate 108 is, for example, doped polysilicon. In addition, a gate dielectric layer 110 may be formed between the gate 106 and the substrate 100 , and a gate dielectric layer 112 may be formed between the gate 108 and the substrate 100 . Thereby, the gate 106 and the substrate 100 can be electrically isolated from each other, and the gate 108 and the substrate 100 can be electrically isolated from each other. The material of the gate dielectric layer 110 and the gate dielectric layer 112 is, for example, silicon oxide. In some embodiments, the forming method of the gate 106 , the gate 108 , the gate dielectric layer 110 and the gate dielectric layer 112 may include the following steps, but the invention is not limited thereto. Firstly, a gate dielectric material layer (not shown) and a gate material layer (not shown) can be sequentially formed on the substrate 100 . Then, the gate material layer and the gate dielectric material layer can be patterned by a lithography process and an etching process (eg, a dry etching process) to form the gate 106 , the gate 108 , the gate dielectric layer 110 and the gate. Dielectric layer 112.

Referring to FIG. 1B , a patterned photoresist layer 114 may be formed on the substrate 100 . The patterned photoresist layer 114 can expose part of the substrate 100 . The patterned photoresist layer 114 can be formed by a photolithography process.

Next, a doped region 116 and a doped region 118 separated from each other are formed in the substrate 100 on both sides of the gate 106 . The doped region 116 and the doped region 118 can serve as lightly doped drains (LDDs), respectively. The doped region 118 is adjacent to the gate 108 . The doped region 116 and the doped region 118 can have a first conductivity type (eg, N type). Part of the doped region 116 may extend into the substrate 100 directly below the gate 106 . A portion of the doped region 118 may extend into the substrate 100 directly below the gate 106, a portion of the doped region 118 may be located in the substrate 100 between the gate 106 and the gate 108, and a portion of the doped region 118 may extend into the substrate 100 directly below the gate 106. In the substrate 100 directly below the gate 108 . The method for forming the doped region 116 and the doped region 118 may include an inclined-angle ion implantation process IP. For example, the oblique-angle ion implantation process IP can be performed on the substrate 100 by using the patterned photoresist layer 114 as a mask to form the doped region 116 and the doped region 118 . In addition, since the gate length L2 of the gate 108 can be smaller than the gate length L1 of the gate 106, the gate 108 can have a smaller gate length, which is helpful to use the tilt angle ion implantation process IP to incorporate the dopant Implanted into the substrate 100 directly below the gate 108 .

In this embodiment, the doped region 118 may include a doped portion 118a and a doped portion 118b separated from each other formed by an inclined-angle ion implantation process IP, that is, the doped region 118 may be a discontinuous structure, but The present invention is not limited thereto. The doped part 118 a and the doped part 118 b are located in the substrate 100 on both sides of the gate 108 . Part of the doped region 118a may extend into the substrate 100 directly below the gate 106, part of the doped region 118a may be located in the substrate 100 between the gate 106 and the gate 108, and part of the doped region 118a may extend to In the substrate 100 directly below the gate 108 . Part of the doped region 118b may extend into the substrate 100 directly below the gate 108 . In this embodiment, since the doped region 118 formed by the inclined angle ion implantation process IP is a discontinuous structure, the doped portion 118a and the doped portion 118b will be diffused due to the subsequent tempering process. They are connected to each other, so that the doped region 118 can become a continuous structure, and the doped region 118 can pass directly under the gate 108 . In some other embodiments, the doped region 118 with a continuous structure can be directly formed by an inclined-angle ion implantation process IP, so that the doped region 118 passes right under the gate 108 . In addition, by adjusting the width W of the gap G, the dopant implantation condition of the tilt angle ion implantation process IP in the substrate 100 below the gate 108 can be controlled.

Referring to FIG. 1C , the patterned photoresist layer 114 can be removed. The removal method of the patterned photoresist layer 114 is, for example, dry stripping or wet stripping.

Next, a spacer 120 and a spacer 122 may be formed on the substrate 100 on both sides of the gate 106 and the gate 108 , and a spacer 124 may be formed in the gap G between the gate 106 and the gate 108 . The spacer 120 is located on the sidewall of the gate 106 . The spacer 122 is located on the sidewall of the gate 108 . The spacer 124 can be connected to the sidewall of the gate 106 and the sidewall of the gate 108 . The spacer 120 , the spacer 122 and the spacer 124 can be a single-layer structure or a multi-layer structure respectively. The material of the spacer 120 , the material of the spacer 122 and the material of the spacer 124 are, for example, silicon oxide, silicon nitride or a combination thereof.

In some embodiments, the forming method of the spacer 120 , the spacer 122 and the spacer 124 may include the following steps, but the invention is not limited thereto. First, a spacer material layer (not shown) may be conformally formed on the substrate 100 , wherein the spacer material layer covers the gate 106 and the gate 108 and fills the gap G. As shown in FIG. In some embodiments, the width W of the gap G is less than or equal to twice the film thickness of the spacer material layer, whereby the gap G can be filled up by the spacer material layer. Next, an etch-back process (for example, a dry etching process) may be performed on the spacer material layer to form the spacer 120 , the spacer 122 and the spacer 124 .

Referring to FIG. 1D , a source region 126 and a drain region 128 separated from each other are formed in the substrate 100 on both sides of the gate 106 and the gate 108 . The source region 126 is adjacent to the gate 106 . The drain region 128 is adjacent to the gate 108 . The doped region 116 is located between the source region 126 and the gate 106 . The source region 126 and the drain region 128 can have a first conductivity type (eg, N type). The depth of the source region 126 and the depth of the drain region 128 may be greater than the depth of the doped region 116 and the depth of the doped region 118 . In addition, the source region 126 can cover a portion of the doped region 116 , and the drain region 128 can cover a portion of the doped region 118 . The method for forming the source region 126 and the drain region 128 is, for example, an ion implantation method. For example, a patterned photoresist layer (not shown) can be used as a mask to perform an ion implantation process on the substrate 100 to form the source region 126 and the drain region 128 . In addition, during the ion implantation process for forming the source region 126 and the drain region 128 , the spacer 120 , the spacer 122 and the spacer 124 can be used to prevent the dopant implanted in the above ion implantation process from being implanted into the spacer 120 . , in the substrate 100 below the spacer wall 122 and the spacer wall 124 .

In addition, a doped region 130 may be formed in the substrate 100 on the side of the source region 126 away from the gate 106 . The doped region 130 may have a second conductivity type (eg, P type). The depth of the doped region 130 may be greater than the depth of the doped region 116 and the depth of the doped region 118 . A method for forming the doped region 130 is, for example, an ion implantation method. For example, a patterned photoresist layer (not shown) can be used as a mask to perform an ion implantation process on the substrate 100 to form the doped region 130 .

In some embodiments, the source region 126 and the drain region 128 may be formed first, and then the doped region 130 is formed, but the invention is not limited thereto. In other embodiments, the doped region 130 may be formed first, and then the source region 126 and the drain region 128 are formed.

Referring to FIG. 1E , a tempering process can be performed. The tempering process can make the doped part 118a and the doped part 118b in FIG. 1D be connected to each other due to diffusion, thereby forming the doped region 118 of the continuous structure in FIG. 1E, and making the doped region in FIG. 1E 118 extends continuously from one side of the gate 106 to the drain region 128 and passes directly under the gate 108 . In addition, the tempering process can make the dopants in the source region 126 uniformly distributed due to diffusion. The tempering process can make the dopants in the drain region 128 uniformly distributed due to diffusion. The tempering process can make the dopants in the doped region 130 uniformly distributed due to diffusion.

In some other embodiments, in the step of FIG. 1B, if the doped region 118 with a continuous structure has been formed, the tempering process in FIG. 1E may also be performed, so that the dopant in the doped region 118 is diffused and uniform. distribution, thereby reducing the resistance value.

Based on the above embodiments, it can be seen that the method for forming the doped region 116 and the doped region 118 in FIG. 1E may include an oblique-angle ion implantation process or a combination of an oblique-angle ion implantation process and an annealing process.

Hereinafter, the transistor structure 10 of this embodiment will be described with reference to FIG. 1E . In addition, although the method for forming the transistor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1E , the transistor structure 10 includes a substrate 100 , a gate 106 , a gate 108 , a doped region 116 , a doped region 118 , a source region 126 and a drain region 128 . In some embodiments, the transistor structure 10 may be a power metal oxide semiconductor (MOS) transistor, such as a lateral diffused metal oxide semiconductor (LDMOS) transistor. .

The gate 106 and the gate 108 are separated from each other and disposed on the substrate 100 . The gate 106 and the substrate 100 are electrically insulated from each other. The gate 108 and the substrate 100 are electrically insulated from each other. The gate length L2 of the gate 108 may be smaller than the gate length L1 of the gate 106 . The doped region 116 and the doped region 118 are separated from each other and located in the substrate 100 on both sides of the gate 106 . The doped region 118 is adjacent to the gate 108 . The source region 126 and the drain region 128 are separated from each other and located in the substrate 100 on both sides of the gate 106 and the gate 108 . The source region 126 is adjacent to the gate 106 . The drain region 128 is adjacent to the gate 108 . The doped region 116 is located between the source region 126 and the gate 106 . The doped region 116 can be connected to the source region 126 . A portion of the doped region 116 may be located in the substrate 100 directly below a portion of the gate 106 . The doped region 118 continuously extends from one side of the gate 106 to the drain region 128 and passes directly under the gate 108 . The doped region 118 can be connected to the drain region 128 . The partially doped region 118 may be located in the substrate 100 directly below the gate 106, the partially doped region 118 may be located in the substrate 100 between the gate 106 and the gate 108, and the partially doped region 118 may be located in the substrate 100 between the gate 106 and the gate 108. In the substrate 100 right below the entire gate 108 .

The transistor structure 10 may further include a doped region 130 , a well region 104 and a well region 102 . The doped region 130 is located in the substrate 100 on a side of the source region 126 away from the gate 106 . A well region 104 is located in the substrate 100 . The doped region 116 , the doped region 118 , the source region 126 , the drain region 128 and the doped region 130 may be located in the well region 104 . Well region 102 is located in substrate 100 . Well area 104 may be located in well area 102 .

The transistor structure 10 may further include a gate dielectric layer 110 and a gate dielectric layer 112 . The gate dielectric layer 110 is disposed between the gate 106 and the substrate 100 , so that the gate 106 and the substrate 100 can be electrically insulated from each other. The gate dielectric layer 112 is disposed between the gate 108 and the substrate 100 , so that the gate 108 and the substrate 100 can be electrically insulated from each other.

The transistor structure 10 may further include a spacer 120 , a spacer 122 and a spacer 124 . The spacer 120 and the spacer 122 are located on the substrate 100 at two sides of the gate 106 and the gate 108 . The spacer 120 is disposed on the sidewall of the gate 106 . The spacers 122 are disposed on sidewalls of the gate 108 . The spacer 124 is disposed in the gap G between the gate 106 and the gate 108 . The spacer 124 can be connected to the sidewall of the gate 106 and the sidewall of the gate 108 . Part of the doped region 116 may be located in the substrate 100 directly below the spacer 120 . A portion of the doped region 118 may be located in the substrate 100 directly below the spacer 122 , and a portion of the doped region 118 may be located in the substrate 100 directly below the entire spacer 124 .

In addition, regarding the materials, forming methods and functions of each component in the transistor structure 10 , reference can be made to the descriptions in the above embodiments, and no further description is given here.

Based on the above-mentioned embodiments, in the transistor structure 10 and its manufacturing method, since the doped region 118 continuously extends from one side of the gate 106 to the drain region 128 and passes directly under the gate 108, the conduction can be reduced. resistance (R _on ). In addition, since the gate 108 can be used as a split gate, the gate/drain charging charge (Q _gd ) can be reduced. In this way, the quality factor of the transistor element can be effectively reduced, thereby improving the energy conversion efficiency of the transistor element and suppressing power loss.

To sum up, the transistor structure and its manufacturing method proposed in the above embodiments can reduce the on-resistance (R _on ) and the charging charge of the gate/drain (Q _gd ), thus effectively reducing the quality of the transistor components. Factor, thereby improving the energy conversion efficiency of transistor elements and suppressing power loss.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Transistor structure 100: base 102, 104: well area 106, 108: gate 110, 112: gate dielectric layer 114: Patterned photoresist layer 116, 118: doped area 118a, 118b: doping part 120, 122, 124: Spacers 126: source region 128: Drain area 130: doping area G: Gap IP: Inclined Angle Ion Implantation Process L1, L2: gate length W: width

1A to 1E are cross-sectional views of the fabrication process of transistor structures according to some embodiments of the present invention.

10: Transistor structure

100: base

102,104: well area

106,108: gate

110,112: gate dielectric layer

116,118: doped area

120,122,124: gap wall

126: source area

128: Drain area

130: doping area

G: Gap

L1, L2: gate length

Claims (10)

A transistor structure, comprising: a substrate; a first gate and a second gate, separated from each other and disposed on the substrate, wherein the first gate and the substrate are electrically insulated from each other, and the second gate electrically insulated from the substrate; the first doped region and the second doped region are separated from each other and located in the substrate on both sides of the first gate, wherein the second doped region is adjacent to in the second gate; and a source region and a drain region separated from each other and located in the substrate on both sides of the first gate and the second gate, wherein the source region adjacent to the first gate, the drain region adjacent to the second gate, the first doped region between the source region and the first gate, and the first gate The two-doped region continuously extends from one side of the first gate to the drain region and passes directly under the second gate. The transistor structure according to claim 1, wherein part of the first doped region is located in the substrate directly below a part of the first gate. The transistor structure according to claim 1, wherein part of the second doped region is in the substrate directly below a part of the first gate, and part of the second doped region is in the first In the substrate between the gate and the second gate, and part of the second doped region is located in the entire substrate directly below the second gate. The transistor structure according to claim 1, wherein the gate length of the second gate is smaller than the gate length of the first gate. The transistor structure according to claim 1, further comprising: a third doped region located in the substrate on the side of the source region away from the first gate; a first well region located in In the substrate, wherein the first doped region, the second doped region, the source region, the drain region and the third doped region are located in the first well region and a second well region in the substrate, wherein the first well region is in the second well region. The transistor structure according to claim 1, further comprising: a first gate dielectric layer disposed between the first gate and the substrate; and a second gate dielectric layer disposed on the second between the gate and the substrate. The transistor structure according to claim 1, further comprising: a first spacer and a second spacer, located on the substrate on both sides of the first gate and the second gate, wherein the The first spacer is arranged on the sidewall of the first gate, and the second spacer is arranged on the sidewall of the second gate; and the third spacer is arranged on the first gate and the gap between the second gate. The transistor structure according to claim 1, wherein part of the first doped region is located in the substrate directly below the first spacer, and part of the second The doped region is located in the substrate directly below the second spacer, and part of the second doped region is located in the entire substrate directly below the third spacer. A method for manufacturing a transistor structure, comprising: providing a substrate; forming a first gate and a second gate separated from each other on the substrate, wherein the first gate and the substrate are electrically insulated from each other, and the second The second gate and the substrate are electrically insulated from each other; a first doped region and a second doped region separated from each other are formed in the substrate on both sides of the first gate, wherein the second doped region adjacent to the second gate; and a source region and a drain region separated from each other are formed in the substrate on both sides of the first gate and the second gate, wherein the source region adjacent to the first gate, the drain region adjacent to the second gate, the first doped region between the source region and the first gate, and the The second doped region continuously extends from one side of the first gate to the drain region and passes directly under the second gate. The method for manufacturing a transistor structure according to claim 9, wherein the forming method of the first doped region and the second doped region includes an oblique angle ion implantation process or the oblique angle ion implantation process and Combination of tempering processes.

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