TW200840025A - NAND type non-volatile memory and fabricating method thereof - Google Patents

Abstract

A fabricating method of NAND type non-volatile memory is provided. First, a substrate having a first area and a second area is provided. The first area and the second area are arranged in parallel in the first direction. A dielectric layer, a first conductive layer and an inter-gate dielectric layer are formed on the substrate. Two openings extended in a second direction are formed in the inter-gate dielectric layer. The second direction is perpendicular to the first direction. The two openings only formed on the first area. A second conductive layer is formed on the substrate to fill in the two openings. The second conductive layer, the inter-gate dielectric layer, the first conductive layer and the dielectric layer are patterned to formed a plurality of stacked gate structures and two select gate structures having the openings therein. The stacked gate structures and the two select gate structures extend in the second direction and across the first area and the second area.

Description

200840025 pi.ap/6^ 22641twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory device, and in particular to an anti-gate type NAND type non-volatile memory and its manufacturing method. [Prior Art] Since non-volatile memory components have the advantages of multiple data storage, reading, erasing, etc., and the stored data does not disappear after power-off, it has become a personal computer and A memory component widely used in electronic devices. Typical non-volatile memory components are typically designed to have a stacked-gate structure including floating gates doped with doped polysilicon (F1〇ating) Gate) and control gate (Control Gate). The floating gate is located between the control gate and the substrate, and is in a floating state, not connected to any circuit, and the control gate is connected to the word line (Word Line), and further includes a tunneling oxide layer ( Tunneling Oxide and Inter-Gate Didectric Layer are located between the substrate and the floating gate and between the floating gate and the control gate. On the other hand, the non-volatile memory arrays currently used in the industry include an inverted OR gate (NOR) type array structure and a NAND type array structure. Since the non-volatile memory structure of the NAND type array is such that the memory cells are connected in series, the degree of integration and area utilization is better than that of the non-volatile memory of the gate (NOR) type array. It has been widely used in many 200840025 pi.ap/6^ 22641twf.doc/e electronic products. Fig. 1A is a top view showing the structure of a conventional anti-gate type non-volatile memory. 1 is a cross-sectional view showing the structure of the line along the Α-Α in FIG. 1C is a cross-sectional view showing the structure of the line Β-Β' in FIG. Referring to Figures 1A through 1C, an element isolation structure 102 is provided in the substrate 1 to define the active region 104. A plurality of bit lines BL (Bit Line), a plurality of word lines WL (Word Line), and a selection gate line SG (Select Gate Line) are provided on the substrate 1A. Each of the bit lines BL corresponds to a memory row of the parent point of the word line WL. The portion of the word line WL that crosses the active area 104 serves as a memory cell M. The memory cell M is composed of a tunneling dielectric layer 106, a floating gate 1〇8, a gate dielectric layer ho, and a control gate 112. The portion of the delivery gate line SG across the active region 1〇4 serves as a selection unit T. The selection unit T is composed of a dielectric layer 114, a conductor layer 116, an inter-gate dielectric layer 110, and a conductor layer 120. Among them, the memory cell "and the selection unit T are usually made in the same process. Therefore, in the process of the gate type non-volatile memory, after the gate dielectric layer is formed, it is removed. The portion of the inter-gate dielectric layer 11G on the region where the gate line SG is selected is formed to electrically connect the conductor layer 116 of the selection unit τ to the conductor layer 12. In the conventional anti-gate type non-volatile memory In the manufacturing method, for example, after the formation of the inter-gate dielectric layer 11 ,, the inter-gate dielectric layer m of the region 124 is removed. Since the entire gate line is selected, the dielectric layer is turned off. Was removed, due to the pouring of the line extension plug (fine (10) Gate Line Pick_up Plug) directly across the main secret 1〇2 6 200840025 puap / 〇 H 22641twf.doc / e (selection of the gate line extension The dielectric layer 114 is only separated between the plug and the active region 102. This will cause the reliability of the memory device to deteriorate. Therefore, in order to avoid the selection of the gate line extension plug directly across the active region 1〇2, It is necessary to set a large area element around the memory array area MA (Memory Array Area). The isolation structure 102 functions as a dummy area DA (Dummy Area), and then the selection gate line extension plug 122 is disposed in the virtual area DA (as shown in FIG. 1C). However, the area occupied by the virtual area DA is large ( Generally, the area of the 13 bit lines is increased, and the size of the memory element is increased, and the memory element accumulation degree cannot be improved. SUMMARY OF THE INVENTION The present invention provides an anti-gate type non-volatile memory and a method of fabricating the same. There is no need to provide a large component isolation region for selecting a gate line extension plug, which can save memory area and increase component accumulation. The present invention provides a reverse gate type non-volatile memory and a method of fabricating the same. The problem that the reliability of the memory component is deteriorated due to the direct connection between the gate extension plug and the active region below the gate line can be solved. The invention provides a reverse gate type non-volatile memory and a manufacturing method thereof. The manufacturing method is simple, and no additional process is required, and the manufacturing cost can be saved. The invention provides an anti-gate type non-volatile memory, including a plurality of u cells. Column 'each memory cell array includes a plurality of component isolation structures, a plurality of bit lines and a township virtual touch element line, a pure word line, a two-turn gate line, a plurality of drain regions, a plurality of source regions, and a source The pole line and the plurality of selection gate lines extend the plug. The plurality of element isolation structures are arranged in parallel in the base to define the main 200840025 yi.ay / 〇-+ 22641 twf.doc/e

Moving area. These component isolation structures extend in a first direction. The plurality of bit lines are disposed on the substrate in parallel with the plurality of dummy bit lines, and extend in the first direction, wherein the virtual bit lines are arranged every N bit lines, N and M are positive integers, and N The strip bit lines constitute a bit line area, and the M virtual bit lines constitute a virtual bit line area. A plurality of word lines are arranged in parallel on the substrate and extend to the second = direction, and the second direction is interleaved with the first direction, wherein the intersection of each of the bit lines and the word line corresponds to a memory cell line. The second selection gate line is set on the word line=two sides, and the intersection of each bit line and the two selection gate lines corresponds to one selection unit. Each of the selection gate lines includes a first conductor layer, a dielectric layer, a second conductor layer, and a gate dielectric layer. The first conductor is placed on the substrate: a dielectric ^ is disposed between the first conductor layer and the substrate. The second conductor layer is disposed on the first conductor layer. The inter-gate dielectric layer is disposed between the second conductor layer and the first conductor layer, and an opening is provided in the inter-gate dielectric layer to make the second conductor layer and the first conductive layer! Sexual connection, where the opening is only in the bit line area. A plurality of bungee regions are placed in the base of the first side of the cell line. Each bungee zone is electrically connected to each of the bit lines. A plurality of source regions are respectively disposed on the second side of the memory cell row. The source line is attributed to the second substrate of the memory cell, extending in the direction and electrically connected to the source region. Multiple select gate lines extend ^ n to connect two select gate lines. These select gate extensions are only placed in the virtual bit line area. In the embodiment, the selected gate line extension plug is disposed on the active area of the virtual bit line zone. In one embodiment of the invention, the memory cell array is mirrored in a first direction. The adjacent two memory cell arrays share a drain region or a source region. 8 200840025 pi.ap/ό^ 2264 twf.doc/e In one embodiment of the present invention, the anti-gate type non-volatile memory further includes a plurality of selective gate line extension plugs, which are disposed in the common immersion The adjacent two of the regions are selected on the gate line and are located in the virtual bit line region. The above selected idle line extension plugs are disposed at corresponding positions of the same virtual bit line. In one embodiment of the present invention, the anti-gate non-volatile memory further includes a plurality of select gate extension plugs disposed on adjacent two select gate lines of the common source region and located in the virtual In the bit line area. The above selected gate line extension plugs are disposed at corresponding positions of different virtual bit lines. In an embodiment of the invention, the material of the dielectric layer comprises oxide oxide. In an embodiment of the invention, the material of the inter-gate dielectric layer comprises hafnium oxide/tantalum nitride/yttria. In the non-volatile memory of the present invention, since the opening is provided in the dielectric layer of the gate, the opening is only located in the bit line region, and is not formed in the dummy bit line region, so that the gate can be directly selected. The line extension plug is disposed in the virtual bit line area. The present invention does not require the provision of a large element isolation region for selecting the gate line extension plugs, thereby saving memory area and increasing component integration. Moreover, the present invention can be used as a virtual bit line area for the area formed by the time zone extension plug, so that it is not necessary to form a dummy bit line area for selecting a gate line extension plug, and the memory area can be saved. In addition, the component dielectric is further provided, and the idle dielectric layer is still disposed directly below the gate extension plug. Therefore, it is possible to solve the problem of selecting the gate extension plug and the main sub 9 200840025 puap/o^ 22641twf.doc/e The problem of poor reliability of memory components caused by direct connection of zones. The present invention proposes a method of manufacturing a reverse-type non-volatile memory, comprising the following steps. First, a substrate is provided which can be distinguished into a first zone and a second zone. The first zone and the second zone are arranged in parallel in the first direction. A plurality of element isolation structures are formed in the substrate to define active regions which are arranged in parallel in the second direction. A dielectric layer, a first conductor layer, an inter-gate dielectric layer and a second conductor layer are sequentially formed on the substrate. Patterning Γ the second conductor layer and the inter-gate dielectric layer to form at least: two f: in the inter-gate dielectric layer. This—the opening extends in the second direction and is formed only on the first region, the directions being staggered. A third conductor layer is formed on the substrate, and the body layer fills the two openings. The patterned gate dielectric layer H Guardian brother - ¥ body layer, gentleman 槿 is丨; 丨 ^ layer, to form a plurality of stacked gate structures extending in the second direction, and between the pole structure and the second selection Located in the second selection gate junction; two districts. A plurality of source regions are formed in the two opening portions and the plurality of immersed substrates: at least two are formed in the electric layer: the rear photoresist layer is patterned by using the patterned photoresist layer as a mask. Patterning a conductor layer and a gate in the embodiment of the invention, forming a pattern on the second conductor layer 10 200840025

After the step of the Pi.ap/^ 22641 tw/doc layer, the photoresist layer further includes a photoresist thermal reflow process to reduce the opening size of the patterned photoresist layer. In the embodiment of the present invention, the method of "reversing" the forwarding memory is further included on the substrate to form a plurality of bit lines and a plurality of dummy bits, and, bit lines and dummy bits. The meta wires are arranged in parallel in the first direction, and are in the first region and are electrically connected to the secret regions, and the virtual 3 wires are located in the second region. In the embodiment, the selected gate line extension plug of the gate type non-volatile memory is made of the material of the dielectric layer, and the material of the inter-gate dielectric layer is included on the substrate. A source line is formed. The source line extends in a second direction and is electrically connected to the source region. In an embodiment of the invention, it is also formed on the active area in the second zone in an embodiment of the invention. In one embodiment of the invention, yttria/tantalum nitride/yttria is included. In the method of manufacturing the gate-type non-volatile memory, in the step of forming an opening in the two-layer layer, a patterned mask (four) is used: when the dielectric layer is guided, by adjusting "eight + Niu first privately. Separate the conductor layer so that the opening of the conductor layer and the two electrical layers, and then the conductor layer; the thickness of the layer of the tender layer is formed and 'in the anti-gate type of the invention is not _ In the step of forming an opening in the dielectric layer of the gate, 200840025 22641twf.doc/e, the patterned photoresist layer is subjected to a photoresist thermal reflow process to make the patterned photoresist stop small. Then the patterned photoresist layer is used as a mask. Curtain, remove part of the 'body: and the dielectric layer with the gate to form a smaller opening. 曰

In the method for fabricating the anti-gate type non-volatile memory of the present invention, since the opening is formed in the inter-dielectric layer, the opening is only located in the bit line region, and is not formed in the dummy bit line region. Therefore, the pole line extension plug can be directly formed on the dummy age line area towel. The present invention requires a large component hidden region for selecting a gate line extension plug, thereby saving memory area and increasing component accumulation. Moreover, the present invention can use the area formed by the well extension plug as the virtual bit line area, so there is no need to form a virtual bit 70 line area dedicated to selecting the gate line extension plug, thereby saving memory area and improving components. In addition, the memory layer can be formed directly under the gate extension plug. The problem of deterioration. The above described features and advantages of the present invention will become more apparent from the following description. [Embodiment] Fig. 2A is a top view showing a non-volatile non-volatile memory of a preferred embodiment of the present invention. Fig. 2 is a cross-sectional view showing the structure taken along line A_A in Fig. 2A. 2C is a cross-sectional view showing the structure taken along line B-B of FIG. 2A. 2D is a cross-sectional view showing the structure taken along line C-C of FIG. 2A. 2A to 2D, the anti-gate type non-volatile record of the present invention 200840025 FuaF/〇*T 22641twf.doc/e The memory is composed of, for example, a plurality of memory cell arrays MAR. Each of the memory cell arrays MAR is provided, for example, on the substrate 200. The substrate 200 is, for example, a sapphire substrate. An element isolation structure 202 is provided, for example, in the substrate 200 to define an active region 2〇4. The element isolation structure 202 is, for example, a shallow trench isolation structure or a field oxide layer. The element isolation structures 2〇2 are arranged in parallel in the X direction and extend in the X direction. Each memory cell array MAR includes a plurality of bit lines BL1 BLBLn and a plurality of dummy bit lines DBL1 DBDBL8, a plurality of word lines WL1 WLWLx, two select gate lines SGS, SGD, and a plurality of drain regions D, A plurality of source regions s and source lines SL. The plurality of bit lines BL1 to BLn and the plurality of dummy bit lines DBL1 to 〇6!^8 (〇1111111^6忮〇1^) are disposed, for example, in parallel on the substrate 200 and extend in the X direction. The virtual dummy bit lines DBL1 to DBL8' Ν and Μ are set to positive integers every N bit lines BL1 to BLn. In the present embodiment, the number of virtual bit lines DBL1 to DBL8 is exemplified by eight (Μ=8). Of course, the number of virtual bit lines DBL1 to DBL8 may be less than eight or more than eight. The number of bit lines BL1 BLBLn may be 1 ( (N = 1000), and of course, the number of bit lines BL1 BLBLn may be less than 1000 or more than 1000. The N bit lines BL1 to BLn constitute the bit line area BA, and the eight dummy bit lines DBL1 to DBL8 constitute the virtual bit line area DBA. The plurality of word lines WL1 to WLx are, for example, arranged in parallel on the substrate 200, and Extending in the Y direction. The X direction is interlaced with the X direction. The intersection of each of the bit lines BL1 to BLn and all the word lines WL1 to WLx corresponds to the memory cell line. 200840025 ρι.αρ / 〇·^ 22641 twf.doc/e MR. All of the word lines WL1 WLWLx span the portion above the active area 2〇2 as a memory cell. Below the bit lines BL1 to BLn, a memory cell line MR composed of these memory cells is provided. As shown in FIG. 2B, each of the memory cells is sequentially formed by the substrate 200 as a dielectric layer 206, a floating gate 208, an inter-gate dielectric layer 21, a control gate 212, and a replacement region 214. The control gate 212 is provided, for example, on the substrate 200. Control gate 212

The material is, for example, a conductive material such as doped polysilicon, metal or metal telluride. Further, the control gate 212 may be composed of two or more layers of conductor material. In the present embodiment, the control gate 212 is composed of, for example, two layers of doped polysilicon.浮 The floating gate 208 is disposed, for example, between the control gate 212 and the substrate 2〇〇, and the material of the floating gate 208 includes a conductor material (such as doped polysilicon or the like). The dielectric layer 208 is disposed, for example, between the substrate 2 and the floating gate 2A, and is made of, for example, tantalum oxide. The inter-gate dielectric layer 21 is disposed, for example, between the gate 212 and the floating gate 2〇8. The inter-gate dielectric layer 21 is composed of, for example, a bottom oxide layer 210a, a nitride layer 210b, and a top oxide layer 21〇c. The material f of the coil = gate ^ electrical layer 2 丨 0 may also be oxygen cut, nitriding dream, nitrogen ^ stone eve or composite dielectric material such as oxidized stone eve / nitrite eve. The doped region 214 is disposed, for example, in the substrate 2 of the memory cell M_. These memory cells are connected in series by doping regions 214. = a secret zone D, for example, respectively disposed in the side of each memory cell, and these drain regions D are electrically connected, for example, by plugs 226. 200840025 pi.ap/o^t 22641twf.doc/e connection Yuan lines BL1 to BLn. The plurality of source regions 8 are respectively disposed, for example, in the substrate 2'' on the other side of each of the memory cell rows MR. For example, the source line SL is disposed on the substrate 200 on the source region s side of the memory cell row MR, and extends in the Y direction and is electrically connected to the source region $. The two selection gate lines SGD and SGS are respectively disposed on both sides of the word lines wu to WLx, for example. Further, the selection gate line SGD is disposed between 汲 D and each of the memory cell rows MR, and the selection gate line SGS is disposed between each of the source regions S and each of the memory cell rows MR. The intersection of each of the bit lines BL1 to B]J and the two selected gate lines SGD and SGS corresponds to one selection unit STD and STS, respectively. The second selection gate line SGD, SGS crosses the active area 202 as a selection unit STD, STS. As shown in FIG. 2B, the second selection gate lines std and STS are sequentially formed by the substrate 200 as a dielectric layer 216, a conductor layer 218, an inter-gate dielectric layer 220, and a conductor layer 222. The conductor layer 218 is provided, for example, on the substrate 2A. The material of the conductor layer 218 is, for example, doped polysilicon. The conductive layer 218 and the floating gate 208 of the memory cell can be fabricated in the same process. Therefore, the material of the conductor layer 218 is the same as that of the floating gate 208. Of course, the material of the conductive layer 218 and the floating gate 208 of the memory cell may also be different. The dielectric layer 216 is disposed, for example, between the conductor layer 218 and the substrate 200. The material of the dielectric layer 216 is, for example, ruthenium oxide. The dielectric layer 216 and the dielectric layer 206 of the memory cell μ can be fabricated in the same process, so that the dielectric layer 216 and the dielectric layer 206 can be made of the same material and thickness. Of course, the material or thickness of the dielectric layer 216 and the dielectric layer 206 may also be different. 15 200840025 pi.ap/o^ 22641twf.doc/e The conductor layer 222 is disposed, for example, on the conductor layer 218. The conductor layer 222 and the control gate 212 of the memory cell can be fabricated in the same process. Therefore, the material of the conductor layer 222 is the same as that of the control gate 212, and can be composed of two or more layers of conductor materials. Composition. Of course, the material of the control layer 212 of the conductor layer 222 and the memory cell IV may also be different. In the present embodiment, the ' body layer 222 is composed, for example, of two layers of doped polycrystalline stone. The inter-gate dielectric layer 220 is disposed, for example, between the conductor layer 222 and the conductor layer 218. An opening 224 is disposed in the inter-gate dielectric layer 220 to electrically connect the conductor layer 222 to the conductor layer 218. As shown in FIG. 2A, the opening 224 is only located in the bit line region. That is, in the dummy bit line region Ββα, the opening 224 is not provided in the inter-gate dielectric layer 220 (as shown in Figs. 2C and 2D). Moreover, as shown in FIG. 2B, in the conductor layer 222, the lower layer of the conductor layer also has an opening, and the upper layer of the conductor layer passes through the opening in the lower layer of the conductor layer and the opening 224 in the inter-gate dielectric layer 220, and The conductor layer 218 is electrically connected. As shown in FIG. 2A, FIG. 2C and FIG. 2D, the anti-gate type non-volatile memory of the present invention further includes a plurality of selective gate line extension plugs 228a, 228b, and 230a, which are electrically connected to the two selection gate lines. SGD, SGS. The selected gate line extension plugs 228a, 228b, 230a are disposed only in the dummy bit line area DBA. Moreover, the gate line extension plugs 228a, 228b, 23A are selected, for example, on the active area 204. As shown in Fig. 2A, the memory cell array MAR is mirrored, for example, in the X direction, and the adjacent two memory cell arrays MAR share the drain region D or the source region S. For example, the memory cell array MAR shares the drain region D with the adjacent memory cell array MAR on the selection gate line SGD side; the memory cell array 16 200840025 puap/〇-+ 22641twf.doc/e MAR is in the selection gate line The SGS side shares the source region S (and the source line) with the adjacent memory cell array MAR. n

The gate line extension plugs 228a, 228b are disposed, for example, on a common;; and adjacent select gate lines SGD of the pole region D, and are located in the dummy bit line region DBA. The gate line extension plugs 228a, 228b are, for example, disposed at corresponding positions of the same virtual bit lines DBL1 to DBL8. For example, the gate line extension plugs 228a, 228b are selected to be disposed on the dummy bit lines DBL4 to DBL5. The gate line extension plugs 230a, 230b are disposed, for example, on the adjacent selection gate line SGS of the common source region S, and are located in the dummy bit line region DBA. The selection gate line extension plugs 230a, 230b are disposed, for example, at corresponding positions of the different virtual bit lines DBL1 to DBL8 to prevent the selected gate line extension plugs 230a, 230b from interfering with each other. For example, the selection gate line extension plugs 230a are disposed at corresponding positions of the dummy bit lines DBL2 to DBL3; and the selection gate line extension plugs 230b are disposed at corresponding positions of the dummy bit lines DBL6 to DBL6. In the non-volatile memory of the present invention, since the opening 224 is provided in the inter-gate dielectric layer 220, the opening 224 is only located in the bit line area BA, and is not formed in the dummy bit line area DBA. The selection gate line extension plugs 228a, 228b, 230a, 230b can be directly disposed in the dummy bit line area DBA. The present invention does not require the provision of a large element isolation region for selecting a gate line extension plug, thereby saving memory area and increasing component accumulation. Moreover, the present invention can use the area formed by the well extension plug as the 17200840025 ρι.αρ / 〇*+ 2264 ltwf.doc/e virtual bit line area DBA, so there is no need to form the selective gate line extension plug 228a, The virtual bit line area DBA dedicated to 228b, 230a, and 230b can save memory area and increase component accumulation. In addition, the gate dielectric layer 220 is still disposed directly below the gate extension plug, so that the memory component reliability caused by the direct connection of the gate extension plug and the active region below the gate can be solved. The problem of deterioration. The above description of the anti-gate type non-volatile memory of the present invention, followed by the method of manufacturing the anti-gate type non-volatile memory of the present invention. 3A to 3E are cross-sectional views showing the manufacturing process of the anti-gate type non-volatile memory according to the preferred embodiment of the present invention. 4A through 4F are cross-sectional views showing the manufacturing process of the anti-gate type non-volatile memory of the preferred embodiment of the present invention. Fig. 4G is a cross-sectional view showing the structure of the anti-gate type non-volatile g-resonance of the preferred embodiment of the present invention. 3A to 3E are cross-sectional views showing the manufacturing flow along the line A-A' in Fig. 2A. 4A to 4F are cross-sectional views showing the manufacturing process along the line of Fig. 2A. 4G is a cross-sectional view taken along line CC of FIG. 2A ('. FIG. 3A and FIG. 4A, first providing a substrate 300, a substrate 300. For example, a germanium substrate. This substrate 300 can be distinguished, for example, as a bit line region 302. (pair • bit line area BA of Figure 2A) and virtual bit line area 304 (corresponding to virtual bit line area DBA of Figure 2B). Bit line area 302 and virtual bit line area 304 are shown in Figure 2A. A plurality of element isolation structures are formed in the substrate 300 to define an active region between adjacent element isolation structures. The element isolation structure is, for example, a shallow trench isolation structure or field oxygen 18 200840025 ρ ^αρ/ο^ 22641twf.doc/e layer. The shallow groove heterostructure or the formation method of the Weihua layer can be any conventional method. The element isolation structure is arranged in the square line shown in the figure. A dielectric layer 306 is formed on the substrate 300. The dielectric layer 3〇6 is yttrium oxide, and the formation layer of the dielectric layer 3.6 is formed as a layer of conductor layer 308 on the entire substrate. 308 For example, ί is replaced with polycrystalline spine, and the formation method of the conductor layer 3〇8 is, for example, sub-stallization After forming a layer of undoped polycrystalline yttrium by the emulsion phase deposition method, it is formed by using the squid 3; or the method of cultivating the thief field. Then, the conductor layer 3图案8 is patterned. The patterned conductor layer lithography is shown in FIG. 3B and FIG. 4B, and the pattern 310 is formed on the substrate, and the material of the gate dielectric layer 310 is covered with a stone. The gate dielectric is $31 (^m woven cut/ Oxidation-layer bottom oxidation == square = yes ^ thermal oxidation method Τ Γ Γ ,,; oxygen: nitrogen:: or mask Ϊ Sit ί 』: conductor? 3U and - layer pattern conductor layer 312 forming side" If it is, the heteropolycrystalline stone eve, this layer is not a lot of meteorites, 1 chemical vapor deposition method to form a eve of a material, into the child planting 19 200840025

Ptap/δΗ i2641twf.doc/e n is formed by chemical vapor deposition on the spot. The pattern? mask state has an opening S1. "This opening m is located at a region where the gate structure is subsequently formed. The opening 316 extends in the gamma direction shown in FIG. 2A and is formed only in the bit line region 302, and It is not formed in the dummy bit line region 304. The material of the patterned mask layer 314 is, for example, a photoresist material, which is formed by, for example, forming a photoresist layer on the substrate and then exposing and developing the layer. Then, the conductor layer 312 is removed to expose the inter-gate dielectric layer 31. After the partial conductor sound 312 is removed, a portion of the inter-gate dielectric layer 3/ is removed by using the conductor layer 312 as a mask. An opening 318 is formed in the inter-gate dielectric layer 310. The opening 318 extends from the direction of the figure and is formed only in the bit line region 3〇2, but does not form 31 (uT square, ΓΓί11 3 The removal of the conductor layer 312 and the inter-gate dielectric layer method includes a dry ion engraving method, for example, a reactive ion side method. := 3C and FIG. 4C 'Removal of the patterned mask layer 314. Remove the i-acoustic 3 m The method of item 314 is, for example, first patterning the hood with oxygen plasma ashing; then performing a wet cleaning process. Removing the patterned mask Layer 314, J, such as 疋^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The inter-gate dielectric layer 31 〇 20 200840025 pi.ap/^ 22641twf.doc/e Referring to FIG. 3D and FIG. 4D, the patterned conductor layer 32, the conductor layer 312, the inter-gate dielectric layer 310, and the conductor layer 308 are patterned. The dielectric layer 3〇6 has been formed into a plurality of stacked gate structures 322 and a plurality of selected gate structures 324. The most gate structures 322 are composed of a conductor layer 320a, a conductor layer 312a, a gate dielectric layer 31, and a conductor. The layer 308a and the dielectric layer 3〇6a are formed. The conductor layer 32〇a and the “conductor layer” serve as the control gate of the memory cell. The conductor layer 308a serves as the second floating gate of the cell. The dielectric layer 306a serves as the memory. The tunnel has a dielectric layer. The gate structure 324 is composed of a conductor layer 320b, a conductor layer 312b, an inter-gate dielectric layer 31, a conductor layer 308b, and a dielectric layer 306b. The conductor layer 32% and the germanium conductor layer 3 ^2b, the conductor layer 308b serves as a selection gate. The dielectric layer 3 〇 is selected as a gate dielectric layer. The plurality of stacked gate structures 322 and the plurality of selected idler structures 324 are in FIG. The gamma direction shown by A extends across the bit line region 3〇2 and the quasi-bit line region 304. The opening 318 is located within the select gate structure 324. The stacked gate structure 322 is located at two select gate structures 324. Thereafter, a doped region 326a, a source region 326b and a drain region 326c are formed in the substrate on both sides of the stacked gate structure 322 and the selective gate structure 324. The doped region 326a is formed, for example, on the stacked gate structure. 322 is between each other and between the stacking/interpole structure 322 and the selection gate structure 324. The source region 32A and the drain region 326C are respectively formed in the substrate 300• outside the selection gate structure 324. Then, an interlayer insulating layer 328 is formed on the substrate 3A. The material of the interlayer insulating layer 328 is, for example, ruthenium oxide, phosphorous iridium glass, borophosphon glass or other suitable dielectric material, and the formation method thereof is, for example, chemical vapor deposition. A source 21 200840025 puap / 〇 H 22641 twf. doc / e pole line 330 electrically connected to the source region 326b is then formed in the interlayer insulating layer 328. The source line 330 extends in the γ direction shown in FIG. 2A. The step of forming the source line 33A in the interlayer insulating layer 328 is as follows. A portion of the interlayer insulating layer 328 is first removed to form a trench that exposes the source regions. A layer of conductor material filling the trench is then formed on the substrate 300. Thereafter, the chemical frequency grinding method is used to transfer the conductor material layer until the interlayer insulating layer 328 is exposed. Among them, the method of forming the ditch is, for example, a technique of engraving. Referring to FIG. 3E and FIG. 4E, another interlayer insulating layer 332 is formed on the substrate 300. The material of the interlayer insulating layer 332 is, for example, oxidized stone, stone dance glass, borophosphon glass or other suitable dielectric material, and its formation method is, for example, chemical vapor deposition. Then, a plurality of plugs 334 which are connected to the other portions and the polar regions 326c are formed in the interlayer insulating layer 332 of the bit line region 3〇2. The step of forming the plug 334 in the interlayer insulating layer 332 is as follows. A portion of the interlayer insulating layer 332 and the interlayer insulating layer 328 are first removed to form a plurality of openings exposing the drain regions 326c, respectively. Next, a layer of conductor material filled with openings is formed on the substrate 3A. Thereafter, a portion of the conductor material layer is removed by chemical mechanical polishing or money recovery until the interlayer insulating layer 332 is exposed. The method of forming the opening is, for example, a lithography technique. Thereafter, a plurality of bit lines 336a and a plurality of dummy bit lines 336b are formed on the substrate 300. A plurality of bit lines 336a are formed in the bit line region 3〇2, and are electrically connected to the drain region 326c by the plug 334. A plurality of dummy bit lines 336b are formed in the dummy bit line area 304. The method of forming the plurality of bit lines 336a and the plurality of dummy bit lines 336b is formed, for example, by forming a layer of a conductor material on the substrate 300 and performing a photolithography process. The plurality of bit lines 22 200840025 ρι.αρ / 22641twf.doc/e 336a and the plurality of dummy bit lines 336b are, for example, located above the active area and are arranged in parallel in the X direction shown in FIG. 2A. Next, referring to Fig. 4F and Fig. 4G, a forming process for selecting the gate line extension plugs 338a, 338b will be described. Since the gate line extension plugs 338a, 338b are formed in the dummy bit line area 304, only the dummy bit line area 304 will be described in the following description. 4F and 4G are continued from Fig. 4E, except that Fig. 4F is a cross-sectional view taken along line B-B of Fig. 2A. Figure 4G is a cross-sectional view taken along line C-C' of Figure 2A. As shown in FIGS. 4F and 4G, a portion of the dummy bit line 336b, the interlayer insulating layer 332, and the interlayer insulating layer 328 are removed to form a plurality of openings that respectively expose the selected gate structure 324. Then, a selective closed-pole extension plug 338&, a rib is electrically connected to the selection gate structure 324 in the opening. The gate line extension plug is selected, and the 3 channel is, for example, located at a corresponding position of three different virtual bit lines, and can be formed on the active area. Subsequent completion of the non-volatile record process is known to those skilled in the art and is described in this section. In the manufacturing method of the reverse and the symmetry (4) of the present invention, in the step of forming the opening 318 in the layer 310, the patterning mask is used to remove the portion of the conductor layer 312 and the idle layer 310. By adjusting the money, the conductor layer 312 is divided into a part of the conductor layer 312, and then the conductor layer is used as the opening of the inter-cover dielectric layer 31G, and then the part of the inter-gate dielectric is privately separated by #ηππ++. Layer 310. Therefore, it is possible to use the station laser as the opening 318 having a small degree of vaporization in the dielectric layer 31 of the gate. For example, the patterned photoresist layer can not be used to expose the light source, and the line width of 100 nm or less can be formed, and it is impossible to produce a photoresist layer directly from 200840025 puap/o^ z!2641twf.doc/e An opening 318 having a width of less than 1 nanometer. However, by using the above method, the width of the opening 318 in the dielectric layer of the gate can be about 7 nanometers. In the method of fabricating the anti-gate type non-volatile memory of the present invention, • since the opening 318 is formed in the inter-gate dielectric layer 310, the opening 318 is only in the bit line region 3〇2, but not The dummy bit line region 304 is formed, so that the selected gate line extension plugs 338a, 338b can be formed directly in the dummy bit line region 304. The present invention does not require the formation of a large element isolation region for selecting a gate line extension interposer, thereby saving memory area and increasing component accumulation. Moreover, the present invention can use the area formed by the well extension plug as the dummy bit line area 304, so that it is not necessary to form the virtual bit line area 304 dedicated to the selected gate line extension plugs 338a, 338b, thereby saving memory. Area 'Tinan component accumulation. In addition, the gate dielectric layer 310 is formed directly under the gate extension plug, so that the reliability of the memory component caused by the direct connection between the gate extension plug and the active region below the G can be solved. Poor question. Figure 5A to Figure 5D are cross-sectional views showing the manufacturing process of the opposite-gate non-volatile memory of another preferred embodiment of the present invention. 5A to 5D are cross-sectional views showing the manufacturing flow along the line A-A' in Fig. 2A. 5A to 5D, the same components as those in Figs. 4A to 4E are given the same reference numerals, and detailed description thereof will be omitted. Please refer to FIG. 5A, which is shown in FIG. 4A. Formed on the substrate 300 24 200840025 pu.ap / o ^ 22641twf.doc / e a layer of dielectric layer 306 and a layer of conductor layer 3 〇 8 , after the United States gas fossil eve / oxygen cut. The dielectric layer of the gate is formed by a thermal oxidation method to form a layer of oxygen-cut layer traces, followed by a phase-forming method to form a layer of nitride layer, followed by a layer of nitride layer: top, top Emulsified enamel layer 31〇c. Of course, the inter-gate dielectric layer 31 may be oxygen cut, oxygen cut/a nitrogen cut or other dielectric material. Then, a conductive layer 312 and a photoresist layer 340 are formed on the substrate 300. The patterned photoresist layer has an opening 3仏. Second: the location where the port and 342a are located is the area where the gate structure is subsequently formed. The port 342a extends in the γ direction shown in Fig. 2A and is formed only in the bit line region, and the sub is not formed in the virtual bit line region 3〇4. The method of forming the patterned photoresist layer is formed, for example, by forming a photoresist layer on a substrate and then exposing and developing the photoresist layer. Then, the patterned photoresist layer is subjected to a photoresist thermal reflow process to form a patterned photoresist layer 34A. The patterned photoresist layer 340a has an opening 342b. Here, the width of the opening 342b is small = the width cU of the opening 342a. That is, the photoresist thermal reflow process can reduce the opening size of the patterned photoresist layer. Next, the patterned photoresist layer 34 is increased by $, and a portion of the conductor layer 312 and the inter-gate dielectric layer 31G are removed to form an opening 344 in the inter-intermediate dielectric layer 310. The opening 344 extends in the meandering direction shown in Fig. 2A and is formed only in the bit line region 302, and the bit line region is deleted. The hetero conductor layer 312 and the inter-gate dielectric layer include a dry rhyme method, such as a reactive ion engraving method. Referring to FIG. 5B, the patterned photoresist layer 34A is removed. Remove patterning 25

200840025 pt.ap/d^ 22641twf.doc/e 3: The VS-to-method is, for example, a patterned wet photoresist layer with oxygen plasma ashing. After the patterned photoresist layer 340a is removed, a germanium is formed on the substrate 300 as a t i layer 3. The in-situ line region 302 and the bite j are in contact with the conductor layer 308 by the opening 344. Month: ..., Fig. 5C, the patterned conductor layer 32, the conductor layer anode, the gate 31G, the conductor layer, and the dielectric layer are formed to form a plurality of stack structures 322 and a plurality of select gate structures 324. The stacked gate structure 322 is composed of a conductor layer 320a, a conductor layer 312a, an inter-gate dielectric layer 31, a conductor layer 3, and a dielectric layer 306a. The gate structure 324 is selected from the conductor layer 320b, the body layer 312b, the inter-gate dielectric layer 31, the conductor layer 308b, and the dielectric layer 306b. Opening 344 is located within select gate structure 324. The stacked gate structure 322 is located between the two select gate structures 324. A doped region 326a, a source region 326b, and a drain region 326c are then formed in the substrate on both sides of the stacked gate structure 322 and the select gate structure 324. An interlayer insulating layer 328 is then formed on the substrate 300, and a source line 33A electrically connected to the source region 326b is formed in the interlayer insulating layer 328. Referring to FIG. 5D, another interlayer insulating layer 332 is formed on the substrate 300. Then, a plurality of plugs 334 electrically connected to the drain regions 326c, respectively, are formed in the interlayer insulating layer 332 of the bit line region 3〇2. Thereafter, a plurality of bit lines 336a and a plurality of dummy bit lines 336b are formed on the substrate 300. A plurality of bit lines 336a are formed in the bit line region 302, and are electrically connected to the drain region 326c by the plug 334. A plurality of dummy bit lines 336b are formed in the dummy bit line area 304. The subsequent process of completing the non-volatile memory is well known to those skilled in the art and will not be described here. 26

200840025 jpL.ap / 纠 22641twf.doc/e In the step of forming the σ 344 in the dielectric layer training of the gate between the anti-gate type non-volatile memory of the present invention, The photoresist thermal reflow process is such that the opening of the patterned photoresist layer 340 is small &gt; patterned into a photoresist layer 340a. The portion of the conductor layer 312 and the free dielectric layer 31 开口 opening 344 are then removed by patterning the light. For example, using a krypton laser as an exposure light source known as a micro-shadow, the patterned light produced is a line width of (10) nanometer or less, and cannot directly utilize an open σ 344 with a patterning fineness of less than 100 nm. . However, by using the above-mentioned square t, the width of the opening 344 in the dielectric layer 31 can be made approximately 7 〇 not water. Moreover, this method is relatively simple and can reduce component manufacturing costs. In summary, the non-volatile memory of the present invention has an opening in the dielectric layer of the gate, and the opening is only located in the positional area, and the virtual bit line area is not formed, so The offline extension plug is selected to be set to the virtual bit line zone towel. The present invention does not require the provision of a large element isolation region for selecting the interpole extension plug, so that the memory area can be saved&apos; to increase the component accumulation. Moreover, the present invention can use the area formed by the well extension plug as the virtual bit line area, so that it is not necessary to form a virtual bit line area dedicated to selecting the gate line extension plug, thereby saving memory area and improving component accumulation. degree. ... In addition, the gate dielectric layer is still provided directly below the gate extension plug, so that the gate extension plug can be directly connected to the main 27 22641twf.d〇c/e 200840025 moving area below it. The resulting reliability of the memory component is degraded. In the method of manufacturing the anti-gate type non-volatile memory of the present invention, in the step of forming an opening in the dielectric layer between the gates, a patterned mask layer is used as the layer </ br> In the electric layer, the conductor layer towel has an opening exposing the closed layer of the crucible by adjusting the core layer, and then removing a part of the inter-gate layer by using the conductor layer as a mask. It is thus possible to form openings having a smaller width in the dielectric layer. %, in the step of forming an opening in the dielectric layer of the gate-type non-volatile memory of the present invention, it is also possible to directly perform a photoresist thermal reflow process on the patterned first resist layer. The patterned photoresist layer is used as a mask for the small Lx® film layer, and the conductor of the age portion is formed as a dielectric layer of the gate to form a small opening. 9 In the anti-gate type non-volatile memory of the present invention In the manufacturing method, the opening σ is formed in the dielectric layer, and the opening is only located in the bit line area 2 and is not in the dummy area, so that the selection can be directly used in the virtual bit line area. The invention does not need to form a large component isolation region for the gate selection gate extension plug, so that the body area can be saved and the component accumulation degree can be improved. The production zone can be used to extend the plug. The formed area is used as the line area, so there is no need to form a 70-line area for selecting the gate line extension plug special degree, and the memory area can be saved, and the component accumulation band sound can be improved, and the idle line extension plug is directly selected. The gate dielectric layer is still formed, so the gate can be solved The pole extension plug and the main 28 below it are 200840025 yi.ay / 〇*+ 22641tWf.d〇C/e The direct axis of the moving zone is defined by the domain of the radiant domain = the rr embodiment is disclosed. Those who have the usual knowledge, in the absence of the invention, may make some changes and refinements. The stagnation of 濩粑 视 视 视 后 后 后 后 后 后 后 后 后 后 后 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【

Fig. 1A is a top view showing the structure of a conventional anti-gate type non-volatile memory. Figure m is a cross-sectional view showing the structure taken along line A-A in Figure 1A. 1C is a cross-sectional view showing the structure taken along line B-B of FIG. 1A.

Figure 2A is a top plan view of a non-volatile non-volatile memory in accordance with a preferred embodiment of the present invention. X Figure 2B is a cross-sectional view showing the structure taken along line A-A of Figure 2A. 2C is a cross-sectional view showing the structure taken along line B-B of FIG. 2A. 2D is a cross-sectional view showing the structure of the line along c_c in FIG. 2A. 3A to 3E are cross-sectional views showing a manufacturing process of an anti-gate type non-volatile memory according to a preferred embodiment of the present invention. 4A through 4F are cross-sectional views showing the manufacturing process of the anti-gate type non-volatile memory of the preferred embodiment of the present invention. Fig. 4G is a cross-sectional view showing the structure of an anti-gate type non-volatile memory according to a preferred embodiment of the present invention. 5A to 5D are cross-sectional views showing a manufacturing process of an anti-gate type non-volatile memory according to another preferred embodiment of the present invention. 29 200840025 pt.ap / ο-τ 2264 ltwf.doc/e [Description of main component symbols] 100, 200, 300: substrate 102, 202: element isolation structure 104, 204: active region 106: tunneling dielectric layer 108, 208: floating gates 110, 210, 220, 310: inter-gate dielectric layers 112, 212: control gates 114, 206, 216, 306: dielectric layers 116, 120, 218, 222, 308, 308, 308a , 308b, 312, 312a, 312b, 320, 320a, 320b: conductor layers 122, 228a, 228b, 230a, 230b, 338a, 338b: select gate line extension plugs 124: regions 214, 326a: doped regions 210a, 310a · bottom oxide layer 210b, 310b: nitride layer 210c, 310c: top oxide layer 226, 334: plug 224, 316, 318, 342a, 342b, 344: opening 302, BA: bit line region 304, DBA Virtual bit line areas 336a, BL, BL1 to BLn: bit line 336b, DBL1 to DBL8: virtual bit line 30 22641twf.doc/e 200840025 326c, D: no-pole area 326b, S: source area 330, SL: source line 314: patterned mask layer 322: stacked gate structure 324: selective gate structure 328, 334: interlayer insulating layer 340, 340a: patterned photoresist layer dl, d2: width DA :Virtual area Μ : Memory cell ΜΑ : Memory cell array area MAR · · Memory cell array MR : Memory cell line SG, SGS, SGD : Select gate line T: Select unit WL, WL1 WLWLx · Character line 31

Claims (1)

200840025 X. Patent application scope: 1. A reverse-type non-volatile memory, comprising a plurality of memory cell arrays, each of the memory cell arrays comprising: an element isolation structure, arranged in parallel in a substrate to define Out - an active area, the element isolation structures extend in a first direction; • a plurality of bit lines and a plurality of dummy bit lines are disposed in parallel on the substrate and extend in the first direction, wherein each 1^The bit lines are set to Γ: M of the virtual bit lines, N, Μ are positive integers, and N of these bits f select line 'set on both sides of the word line, each of the memory lines; the line constitutes a bit line area, and M of the virtual bit lines constitute a think bit, s^ and The red selection gate line should be selected - the selection unit, each of the two, the release gate line includes: a conductor layer 'on the substrate; a gate dielectric layer, set In the evening and the pole regions, respectively, an electric layer is disposed between the first conductor layer and the substrate; a second conductor layer is disposed on the first conductor layer; and the second conductor layer is disposed on the first conductor layer An opening is disposed in the guiding layer to connect the second guiding portion, wherein the opening is located only in the 32 200840025 22641 twf.doc/e substrate of the first side of the memory cell row, and the bucking regions respectively Electrically connecting the bit lines; a plurality of source regions respectively disposed in the substrate on a second side of the memory cell row; a source, a line, and the second side disposed on the second side of the memory cell row Substrate. And extending to the second direction and electrically connecting the source regions; and • a remote gate line extending plug electrically connected to the two selected gate lines, and the selected gate lines are extended The plug is only placed in the virtual bit line area. 2. The anti-gate type non-volatile memory according to claim 1, wherein the selected gate line extension plugs are placed on the active area in the virtual bit line area. 3. The anti-gate type non-volatile memory according to the invention of claim 2, wherein the memory cell arrays are mirrored in the first direction, and the adjacent two memory cell arrays share the 汲Polar regions or the source regions. 4. The anti-gate type non-volatile recording body described in claim 3 of the patent application, further comprising a plurality of selective gate line extension plugs, which are disposed in the common (/and the adjacent areas of the polar regions) Selecting the gate line and located in the virtual bit line area. '5. 5, as described in claim 4, the anti-valve type non-volatile memory, the body, wherein the selection gate line extension The plug is disposed at the corresponding position of the same virtual bit line. The anti-gate type non-volatile L-body described in item 3 of the patent application scope further includes a plurality of selective gate line extension plugs. The plug is disposed on the phase 5 —-selected blue line sharing the original polar region, and is located in the virtual bit line region 33 -2641twf.d〇c/e 200840025 〇7· as claimed in the sixth item And the gate-type non-selective memory, wherein the selected gate line extension plugs are disposed at different corresponding positions of the imaginary bit line. μ 二虚8· The anti-gate type described in the item is non-floating, wherein the material of the dielectric layer includes oxidized stone eve. Please refer to the scope of the patent item: the non-volatile type of the gate type, wherein the material of the inter-gate dielectric layer includes a method of manufacturing an oxygen cut/nitrogen cut/oxidant, including: = the substrate can be distinguished as - - a zone and a second zone, wherein the brother-zone and the second zone are arranged in parallel in the - direction - the substrate is cut into a component isolation structure, and the element isolation structure is in the Forming a matrix on the substrate: a row arrangement, an intermediate dielectric layer and a second conductor layer; t a first conductor layer, a patterned second conductor layer and at least two openings in the electrical layer π, 1 electric layer, for the interface between the gate, and only formed on the first region, the opening of the second plant opening in a second direction; the second direction of the younger brother intersects the first direction and the first The three-conductor layer forms a third guide on the substrate to fill the two openings in the inter-gate dielectric layer. The first-conductor layer and the dielectric layer, the conductor layer, the inter-gate dielectric layer, θ ^ into a plurality of stacked gate structures and to pattern the third conductor layer, the 34th 22641 twf.doc/e 200840025 xx Structure St: the gate structure and the second selection pole structure extend in the direction of the brother-in-law, and there is no second region across the spine-first region, and the opening of the second section is mixed with the axis of the two-selection pole, which is in the second selection The lake has a knot shape @; 才,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The two selections and structures are divided into a plurality of gate lines extending into the base, and the selected gate line extension plugs are disposed only in the second area. The method for patterning the second conductor layer and the dielectric layer according to the method of claim 1G, wherein: forming a pattern on the second conductor layer And the X0 wood photoresist layer is a mask, and the second conductor layer and the inter-gate dielectric layer are patterned. ^ I2. The method for manufacturing a reverse-type non-volatile memory according to claim n, wherein the step of forming the photoresist layer on the second conductor layer further comprises performing a step The photoresist is thermally reflowed to reduce the opening size of the patterned photoresist layer. The method for manufacturing the anti-gate type non-volatile memory according to the first aspect of the patent application, further comprising: forming a plurality of bit lines and a plurality of dummy bit lines on the substrate, the bits The 兀 line and the imaginary bit lines are arranged in parallel in the first direction, wherein the bit lines are located in the first area, and are respectively electrically connected to the non-polar regions, wherein the virtual bit lines are located In the second zone. 35 200840025 22641twf.doc/e 14. The method for manufacturing a reverse-type non-volatile memory according to the above-mentioned patent application, further comprising: forming a source line on the substrate, the source line being The second direction extends and electrically connects the source regions. The method of manufacturing a reverse-type non-volatile read and body according to claim 14 of the invention, wherein the selected gate line extends into the active region in the second region. , The opposite of the memory and the _ volatility 17. For example, the electric layer (4) includes the oxidized stone eve. Memory of the memory of the memory _ nature of the nitride stone ^ the gate (four) electrical material including the oxidized stone eve / 36