KR100609236B1 - Method of forming dual gate - Google Patents

Method of forming dual gate Download PDF

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KR100609236B1
KR100609236B1 KR1020030101187A KR20030101187A KR100609236B1 KR 100609236 B1 KR100609236 B1 KR 100609236B1 KR 1020030101187 A KR1020030101187 A KR 1020030101187A KR 20030101187 A KR20030101187 A KR 20030101187A KR 100609236 B1 KR100609236 B1 KR 100609236B1
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gate
gate oxide
forming
substrate
oxide film
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KR20050069228A (en
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이상기
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동부일렉트로닉스 주식회사
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Priority to KR1020030101187A priority Critical patent/KR100609236B1/en
Priority to US11/017,762 priority patent/US7026203B2/en
Priority to DE102004063578A priority patent/DE102004063578B4/en
Priority to JP2005000230A priority patent/JP4440119B2/en
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Abstract

본 발명은 듀얼 게이트 형성 방법에 관한 것으로, 보다 자세하게는 다마신 게이트 시모스 공정을 적용한 듀얼 게이트 형성시 얇은 게이트 영역은 순수한 산화물로 두꺼운 게이트 산화물 영역은 질화된 게이트 산화물로 형성하는 듀얼 게이트 형성 방법에 관한 것이다.The present invention relates to a dual gate formation method, and more particularly, to a dual gate formation method of forming a thin gate region as a pure oxide and a thick gate oxide region as a nitrided gate oxide when forming a dual gate using a damascene gate CMOS process. will be.

본 발명의 듀얼 게이트 형성 방법은 반도체 기판상에 소자분리막을 형성하는 단계; 상기 기판에 제1게이트 산화막을 형성하는 단계; 상기 기판을 질소 분위기에서 열처리하는 단계; 상기 제1게이트 산화막을 패터닝하는 단계; 상기 기판에 제2게이트 산화막을 형성하여 두꺼운 게이트 산화물과 얇은 게이트 산화물을 형성하는 단계; 상기 기판에 폴리를 증착하고 패터닝하여 게이트를 형성하는 단계; 상기 게이트의 측벽에 사이드월 스페이서를 형성하는 단계; 상기 게이트 양측 하부에 소스/드레인 영역을 형성하는 단계; 상기 폴리를 제거하는 단계; 상기 얇은 게이트 산화물을 제거하는 단계; 상기 기판을 산화하여 제3게이트 산화막을 형성하는 단계; 및 상기 기판에 폴리를 증착하는 단계로 이루어짐에 기술적 특징이 있다.The dual gate forming method of the present invention comprises the steps of forming an isolation layer on a semiconductor substrate; Forming a first gate oxide film on the substrate; Heat treating the substrate in a nitrogen atmosphere; Patterning the first gate oxide film; Forming a thick gate oxide and a thin gate oxide by forming a second gate oxide film on the substrate; Depositing and patterning poly on the substrate to form a gate; Forming sidewall spacers on sidewalls of the gate; Forming source / drain regions on both sides of the gate; Removing the poly; Removing the thin gate oxide; Oxidizing the substrate to form a third gate oxide film; And a step of depositing poly on the substrate.

따라서, 본 발명의 듀얼 게이트 형성 방법은 다마신 게이트 공정에서 듀얼 게이트 산화물을 형성하는 방법으로, 두꺼운 게이트 산화물 영역에 산질화막을 형성시켜 캐리어의 특성을 개선시키고, 얇은 게이트 산화물 부분은 순수한 게이트 산화물로 성장시켜 트랜지스터의 성능을 개선하는 효과가 있다.Therefore, the dual gate forming method of the present invention is a method of forming a dual gate oxide in the damascene gate process, to form an oxynitride film in the thick gate oxide region to improve the characteristics of the carrier, the thin gate oxide portion of the pure gate oxide There is an effect of improving the performance of the transistor by growing.

다마신 게이트, 듀얼 게이트Damascene gate, dual gate

Description

듀얼 게이트 형성 방법{Method of forming dual gate} Method of forming dual gate             

도 1은 종래기술에 의한 듀얼 게이트 형성 방법의 공정 단면도이다.1 is a process sectional view of a dual gate forming method according to the prior art.

도 2내지 도 12는 본 발명에 따른 듀얼 게이트 형성 방법의 공정 단면도이다.2 to 12 are cross-sectional views of a method of forming a dual gate according to the present invention.

<도면의 주요부분에 대한 부호의 설명>         <Description of the symbols for the main parts of the drawings>

150. 소자분리막 160. 사이드월          150. Device isolation layer 160. Sidewall

180. 두꺼운 게이트 산화물 190. 얇은 게이트 산화물         180. Thick Gate Oxide 190. Thin Gate Oxide

본 발명은 듀얼 게이트 형성 방법에 관한 것으로, 보다 자세하게는 다마신 게이트 시모스(Damascene gate CMOSFETs) 공정을 적용한 듀얼 게이트 형성시 얇은 게이트 영역은 순수한 산화물로 두꺼운 게이트 산화물 영역은 질화된 게이트 산화물로 형성하는 듀얼 게이트 형성 방법에 관한 것이다.The present invention relates to a dual gate formation method. More specifically, in the dual gate formation using the damascene gate CMOSFETs process, a thin gate region is formed of pure oxide and a thick gate oxide region is formed of nitrided gate oxide. It relates to a gate forming method.

종래에는 두꺼운 게이트 산화물(Thick gate oxide)과 얇은 게이트 산화물(Thin gate oxide) 영역이 질화된 게이트 산화물(Nitrided gate oxide) 공정으로 진행 되고 있으며, 이렇게 진행 될 경우 얇은 게이트 산화물 영역에 많은 질화물이 함유되게 된다. 또한 얇은 게이트 산화물 부분의 질화물 농도를 낮게 조절할 경우 두꺼운 부분의 질소 농도가 낮아지게 된다. Conventionally, a thick gate oxide and a thin gate oxide region are progressed through a nitrided gate oxide process, and in this case, a large amount of nitride is contained in the thin gate oxide region. do. In addition, when the nitride concentration of the thin gate oxide portion is adjusted low, the nitrogen concentration of the thick portion is lowered.

도 1은 종래기술에 의한 듀얼 게이트 형성 방법의 공정 단면도이다.1 is a process sectional view of a dual gate forming method according to the prior art.

먼저, 소자분리막(STI: Shallow trench isolation)(170)과 반도체 기판(100)을 형성한다. 듀얼 게이트 산화물인 두꺼운 게이트 산화물(180)과 얇은 게이트 산화물(190)을 증착한 후 더미 폴리(Dummy poly)를 증착한다. 이후 게이트 패터닝을 현상한 후 더미 게이트 폴리(120) 식각을 한 후 NMOS와 PMOS의 저도핑 드레인(LDD: Lightly doped drain) 이온주입을(130) 실시한다. 그리고 질화물(Nitride)을 원하는 두께만큼 증착 시킨 후 식각하여 사이드월(Sidewall)을(160) 제작한다. First, a shallow trench isolation (STI) 170 and a semiconductor substrate 100 are formed. After depositing a thick gate oxide 180 and a thin gate oxide 190 which are dual gate oxides, dummy poly is deposited. After the gate patterning is developed, the dummy gate poly 120 is etched, and then lightly doped drain (LDD) ion implantation of NMOS and PMOS is performed. The nitride is deposited to a desired thickness and then etched to produce a sidewall 160.

사이드월(160) 형성 후 소스/드레인(Source/drain) 영역(140)을 형성하기 위하여 페터닝(Patterning)을 진행한 후 이온주입을 실시한다. 다마신 공정(Damascene process)으로 평탄화 후 더미 폴리를 제거하고, 다시 폴리 게이트(120)를 증착하고 평탄화 후 실리사이드(Silicide)(170)를 게이트 상부와 소스/드레인 영역(140)에 형성하게 된다.After the sidewalls 160 are formed, patterning is performed to form the source / drain region 140, followed by ion implantation. After the planarization, the dummy poly is removed by the damascene process, the poly gate 120 is deposited again, and after planarization, the silicide 170 is formed on the gate and the source / drain region 140.

종래기술인 대한민국 공개특허 제2003-0061791호를 살펴보면, 다마신 듀얼 게이트형 트랜지스터 및 관련 제조 방법에 있어서, 완전 평면 다마신 듀얼 게이트형 트랜지스터(Completly planar, damascene double gated transistor)의 구조는 신규한 자기 정렬식 초계단 레트로그레이드 보디(Self-aligned, hyper-abrupt retrograde body) 및 제로-기생 엔드월 게이트 보디 접속(Zero-parasitic, endwall gate-body connection)을 갖는다. 상기 구조는 집적도의 증가를 제공하며 초저전력을 이용할 수 있게 한다. 상기 방법으로는 또한 4단자 및 동적 임계치(Dynamic threshold) MOSFET 장치를 동시에 제조할 수 있는 다마신 듀얼 게이트형 트랜지스터 및 관련 제조 방법에 관한 것이다.Referring to Korean Patent Laid-Open Publication No. 2003-0061791, in the damascene dual gate transistor and related manufacturing method, the structure of a fully planar damascene dual gate transistor (Completly planar, damascene double gated transistor) is a novel self-alignment Self-aligned, hyper-abrupt retrograde body and zero-parasitic, endwall gate-body connection. The structure provides an increase in density and makes it possible to utilize ultra low power. The method also relates to a damascene dual gate transistor and related manufacturing method capable of simultaneously fabricating a four-terminal and dynamic threshold MOSFET device.

그러나, 상기와 같은 종래의 기술은 다마신 게이트 공정에서 듀얼 게이트 산화물 공정을 두껍고 얇은 부분을 분리하여 질소와 순수한 부분으로 만드는 것에 어려운 문제점이 있다.However, the conventional technique as described above has a problem in that the dual gate oxide process in the damascene gate process is difficult to separate the thick and thin portions into nitrogen and the pure portion.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 다마신 게이트 시모스 공정에서 두꺼운 게이트는 질화된 게이트 산화물로 얇은 게이트 영역은 순수한 게이트 산화물로 하여 두꺼운 게이트 산화물 영역에 질소를 형성시켜 캐리어(Carrier)의 특성을 개선시키고, 얇은 게이트 산화물 부분은 순수한 게이트 산화물(Pure gate oxide)로 성장시켜 트랜지스터(Transistor)의 성능을 개선되도록 하는 듀얼 게이트 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, in the damascene gate CMOS process, the thick gate is a nitrided gate oxide, the thin gate region is a pure gate oxide, nitrogen in the thick gate oxide region The purpose of the present invention is to provide a method of forming a dual gate to improve the characteristics of the carrier (carrier) by forming a thin film, the thin gate oxide portion is grown to pure gate oxide to improve the performance of the transistor (Transistor) There is this.

본 발명의 상기 목적은 반도체 기판상에 소자분리막을 형성하는 단계; 상기 기판에 제1게이트 산화막을 형성하는 단계; 상기 기판을 질소 분위기에서 열처리하는 단계; 상기 제1게이트 산화막을 패터닝하는 단계; 상기 기판에 제2게이트 산화막을 형성하여 두꺼운 게이트 산화물과 얇은 게이트 산화물을 형성하는 단계; 상기 기판에 폴리를 증착하고 패터닝하여 게이트를 형성하는 단계; 상기 게이트의 측벽에 사이드월 스페이서를 형성하는 단계; 상기 게이트 양측 하부에 소스/드레인 영역을 형성하는 단계; 상기 폴리를 제거하는 단계; 상기 얇은 게이트 산화물을 제거하는 단계; 상기 기판을 산화하여 제3게이트 산화막을 형성하는 단계; 및 상기 기판에 폴리를 증착하는 단계로 이루어진 듀얼 게이트 형성 방법에 의해 달성된다.The object of the present invention is to form a device isolation film on a semiconductor substrate; Forming a first gate oxide film on the substrate; Heat treating the substrate in a nitrogen atmosphere; Patterning the first gate oxide film; Forming a thick gate oxide and a thin gate oxide by forming a second gate oxide film on the substrate; Depositing and patterning poly on the substrate to form a gate; Forming sidewall spacers on sidewalls of the gate; Forming source / drain regions on both sides of the gate; Removing the poly; Removing the thin gate oxide; Oxidizing the substrate to form a third gate oxide film; And depositing poly on the substrate.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

먼저, 도 2는 본 발명에 따른 듀얼 게이트 형성 방법의 제 1공정을 나타내는 단면도이다. 소자분리막(220)과 웰(Well)을 형성한 후 두꺼운 게이트 산화물인 제1게이트(200)을 산화시킨 후 질소 분위기에서 열처리를 실시하여 게이트 산화물 영역에 질화물을 주입시킨다.First, Figure 2 is a cross-sectional view showing a first step of the dual gate forming method according to the present invention. After forming the device isolation layer 220 and the well, the first gate 200, which is a thick gate oxide, is oxidized, and heat treatment is performed in a nitrogen atmosphere to inject nitride into the gate oxide region.

다음, 도 3은 본 발명에 따른 듀얼 게이트 형성 방법의 제 2공정을 나타내는 단면도이다. 두꺼운 게이트 산화물 영역인 제1게이트(200)을 포토 레지스트(PR: Photo resist)로 패터닝한 후 얇은 게이트 산화물인 제2게이트(210) 영역의 산화물이 제거된 것을 나타내고 있다.3 is a cross-sectional view showing a second step of the dual gate forming method according to the present invention. After the first gate 200, which is a thick gate oxide region, is patterned with a photo resist (PR), the oxide of the region of the second gate 210, which is a thin gate oxide, is removed.

다음, 도 4는 본 발명에 따른 듀얼 게이트 형성 방법의 제 3공정을 나타내는 단면도이다. 두꺼운 게이트 산화물인 제1게이트(200) 영역의 포토 레지스트를 제거한 후 얇은 게이트 산화물인 제2게이트(210)을 산화시킴으로 인하여 듀얼 게이트 산화물을 형성하게 된다.Next, Figure 4 is a cross-sectional view showing a third process of the dual gate forming method according to the present invention. After removing the photoresist in the region of the first gate 200, which is a thick gate oxide, the dual gate oxide is formed by oxidizing the second gate 210, which is a thin gate oxide.

다음, 도 5는 본 발명에 따른 듀얼 게이트 형성 방법의 제 4공정을 나타내는 단면도이다. 폴리(300)를 증착하고 게이트 패터닝을 하여 게이트 이외의 영역은 식각한다. 5 is a cross-sectional view showing a fourth step of the dual gate forming method according to the present invention. The poly 300 is deposited and gate patterned to etch regions other than the gate.

다음, 도 6은 본 발명에 따른 듀얼게이트 형성 방법의 제 5공정을 나타내는 단면도이다. 상기 식각 후 저도핑 드레인(420) 이온주입(Ion implation)을 하고, 사이드월(Sidewall)(400)을 형성하며, 소스/드레인(410)과 정션(Deep junction)은 이온주입과 급속 열처리(RTA: Rapid thermal anneal)에 의해서 형성된다. 이 정션영역은 더미 게이트에 의해서 정의되고, 불순물(Dopant)의 확산을 억제하기 위해서 바람직하게는 800℃ 정도로 급속 열처리를 한다 6 is a cross-sectional view showing a fifth step of the method for forming a dual gate according to the present invention. After the etching, the low doping drain 420 is implanted (Ion implation), the sidewall (Sidewall) 400 is formed, the source / drain 410 and the junction (Deep junction) is ion implantation and rapid heat treatment (RTA) It is formed by rapid thermal anneal. This junction region is defined by a dummy gate, and is preferably subjected to rapid heat treatment at about 800 ° C. in order to suppress diffusion of impurities.

다음, 도 7은 본 발명에 따른 듀얼 게이트 형성 방법의 제 6공정을 나타내는 단면도이다. 상기 제 6공정에서는 폴리(300)를 제거한다.Next, Figure 7 is a cross-sectional view showing a sixth step of the dual gate forming method according to the present invention. In the sixth step, the poly 300 is removed.

다음, 도 8은 본 발명에 따른 듀얼 게이트 형성 방법의 제 7공정을 나타내는 단면도이다. 얇은 게이트 산화물을 타겟으로 제3게이트(600) 산화물을 제거하면 두꺼운 게이트 산화물 영역은 다 제거되지 않고 일정한 양이 남아 있게 된다.8 is a cross-sectional view illustrating a seventh step of the dual gate forming method according to the present invention. When the third gate 600 oxide is removed by using the thin gate oxide as a target, the thick gate oxide region is not removed and a certain amount remains.

다음, 도 9는 본 발명에 따른 듀얼 게이트 형성 방법의 제 8공정을 나타내는 단면도이다. 상기 8공정을 통해 기판 표면에 남아 있는 불순물을 제거된 것을 알 수 있다.9 is a cross-sectional view showing an eighth step of the dual gate forming method according to the present invention. It can be seen that the impurities remaining on the surface of the substrate are removed through the eight steps.

다음, 도 10은 본 발명에 따른 듀얼 게이트 형성 방법의 제 9공정을 나타내는 단면도이다. 채널(Channel)영역을 산화시켜 두꺼운 게이트 산화물 영역과 얇은 게이트 산화물 영역의 두께를 맞추게 되어 형성된다.10 is a cross-sectional view showing a ninth step of the dual gate forming method according to the present invention. The channel region is oxidized to match the thickness of the thick gate oxide region and the thin gate oxide region.

다음, 도 11은 본 발명에 따른 듀얼 게이트 형성 방법의 제 10공정을 나타내는 단면도이다. 폴리-실리콘 게이트((Poly-Silicon gate)(600)를 증착하고 라이너(Liner) 질화물(620)을 증착한 후 더미-프리메탈 유전체(Dummy pre metal dielectric)(610)를 증착하여 화학기계적 연마(CMP: Chemical mechanical planarization) 공정을 거쳐서 평탄화 한다. 이때 평탄화 두께는 사이드월(Sidewall)(400) 상부가 드러날 때까지 실시하게 된다.Next, FIG. 11 is a sectional view showing the tenth step of the dual gate forming method according to the present invention. After depositing a poly-silicon gate (600), a liner nitride (620), a dummy pre metal dielectric (610) to deposit a chemical mechanical polishing ( Planarization is performed through a chemical mechanical planarization (CMP) process, where the planarization thickness is performed until the upper sidewall 400 is exposed.

다음, 도 12는 본 발명에 따른 듀얼 게이트 형성 방법의 제 11공정을 나타내는 단면도이다. 평탄화 후 실리사이드(Silicide) 공정을 거쳐서 완성된 듀얼 게이트 산화물 공정의 단면도이다. 도 12까지의 공정을 거쳐 두꺼운 게이트 산화물 영역의 트랜지스터는 질화물이 주입된 게이트 산화물을 형성하고, 얇은 게이트 산화물 영역의 트랜지스터는 질화물이 주입되지 않은 순수한 산화물을 형성하게 된다.Next, FIG. 12 is a cross-sectional view showing an eleventh step of the dual gate forming method according to the present invention. A cross-sectional view of a dual gate oxide process completed through a silicide process after planarization. Through the process up to FIG. 12, the transistor in the thick gate oxide region forms a gate oxide implanted with nitride, and the transistor in the thin gate oxide region forms pure oxide in which nitride is not implanted.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 듀얼 게이트 형성 방법은 다마신 게이트 공정에서 듀얼 게이트 산화물을 형성하는 방법으로, 두꺼운 게이트 산화물 영역에 산질화막를 형성시켜 캐리어(Carrier)의 특성을 개선시키는 장점이 있고, 얇은 게이트 산화물 부분은 순수한 게이트 산화물(Pure gate oxide)로 성장시켜 트랜지스터의 성능을 개선하는 효과가 있다.Therefore, the dual gate forming method of the present invention is a method of forming a dual gate oxide in the damascene gate process, and has the advantage of improving the characteristics of the carrier by forming an oxynitride film in the thick gate oxide region, thin gate oxide portion The growth of pure gate oxide (Pure gate oxide) has the effect of improving the performance of the transistor.

Claims (4)

듀얼 게이트 형성 방법에 있어서,In the dual gate forming method, 반도체 기판상에 소자분리막을 형성하는 단계;Forming an isolation layer on the semiconductor substrate; 상기 기판에 산화막을 형성하는 단계;Forming an oxide film on the substrate; 상기 기판을 질소 분위기에서 열처리하여 상기 산화막에 질소를 주입시키는 단계;Heat-treating the substrate in a nitrogen atmosphere to inject nitrogen into the oxide film ; 상기 기판의 제1영역에 상기 산화막을 패터닝하여 질소가 주입된 제1게이트 산화막을 형성하는 단계;Patterning the oxide film in the first region of the substrate to form a first gate oxide film implanted with nitrogen ; 상기 기판의 제2영역에 상기 제1게이트 산화막에 비하여 얇은 제2게이트 산화막을 형성하는 단계;Forming a second gate oxide film thinner than the first gate oxide film in a second region of the substrate; 상기 기판에 폴리를 증착하고 패터닝하여 상기 제1영역의 소정 영역에 제1더미 게이트를 형성하고, 상기 제2영역의 소정 영역에 제2더미 게이트를 형성하는 단계;Depositing and patterning poly on the substrate to form a first dummy gate in a predetermined region of the first region, and forming a second dummy gate in a predetermined region of the second region ; 상기 제1더미 게이트 및 제2더미 게이트의 측벽에 사이드월 스페이서를 형성하는 단계;Forming sidewall spacers on sidewalls of the first and second dummy gates; 상기 제1더미 게이트 및 제2더미 게이트 양측 하부에 소스/드레인 영역을 형성하는 단계;Forming source / drain regions on both sides of the first dummy gate and the second dummy gate; 상기 제1더미 게이트 및 제2더미 게이트를 제거하여 상기 제1게이트 산화막 및 제2게이트 산화막을 노출시키는 단계; Exposing the first gate oxide layer and the second gate oxide layer by removing the first dummy gate and the second dummy gate ; 상기 결과물에 대한 식각을 수행하여, 상기 제1게이트 산화막은 소정의 두께로 식각된 제3게이트 산화막으로 형성하고 상기 제2게이트 산화막은 모두 제거하는 단계;Etching the resultant to form the first gate oxide layer as a third gate oxide layer etched to a predetermined thickness and removing all of the second gate oxide layer; 상기 기판을 산화하여 상기 제2게이트 산화막이 제거된 영역에 상기 제3게이트 산화막에 비하여 얇은 제4게이트 산화막을 형성하는 단계; 및 Oxidizing the substrate to form a thinner fourth gate oxide film than the third gate oxide film in a region where the second gate oxide film is removed ; And 상기 기판에 게이트 형성을 위한 폴리를 증착하는 단계; 를 포함하며, Depositing poly to form a gate on the substrate; Including and 상기 제3게이트 산화막은 질소가 포함된 산화막이며, 상기 제4게이트 산화막은 상기 제3게이트 산화막에 비하여 얇게 형성된 순수 산화막인 것을 특징으로 하는 듀얼 게이트 형성 방법. And the third gate oxide film is an oxide film containing nitrogen, and the fourth gate oxide film is a pure oxide film thinner than the third gate oxide film . 삭제delete 삭제delete 삭제delete
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KR20020051283A (en) * 2000-12-22 2002-06-28 박종섭 Method for fabricating dual gate-oxide
KR20030047556A (en) * 2001-12-11 2003-06-18 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
KR20030050680A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method of fabricating semiconductor device with dual gate oxide
KR20030093713A (en) * 2002-06-05 2003-12-11 주식회사 하이닉스반도체 Method for forming dual gate oxide

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KR20020051283A (en) * 2000-12-22 2002-06-28 박종섭 Method for fabricating dual gate-oxide
KR20030047556A (en) * 2001-12-11 2003-06-18 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
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