KR20030093713A - Method for forming dual gate oxide - Google Patents
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Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 듀얼 게이트산화막 (Dual gate oxide)을 구비한 CMOS의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a CMOS having a dual gate oxide.
일반적으로 반도체소자의 게이트산화막으로 열(Thermally) 또는 급속열처리(Rapid thermally)에 의해 성장된 SiO2를 사용하고 있다. 최근에 반도체소자의 디자인룰이 감소함에 따라 게이트산화막의 두께는 SiO2의 터널링한계가 되는 25∼30Å이하로 줄어드는 추세에 있으며, 0.1㎛급 소자에서의 게이트산화막으로는 25∼30Å두께가 예상된다.Generally, SiO 2 grown by thermally or rapid thermally is used as a gate oxide film of a semiconductor device. As the design rules of semiconductor devices decrease in recent years, the thickness of gate oxide films has tended to decrease below 25-30 kHz, which is the tunneling limit of SiO 2 , and a thickness of 25-30 kHz is expected as a gate oxide film in 0.1 占 퐉 devices. .
특히, 게이트산화막의 전기적 두께가 30Å 이하일 경우에는 낮은 전압에서도 동작속도 및 구동전류가 매우 높아서 로직소자에 적용가능성이 높으나, DRAM의 셀트랜지스터의 경우에는 직접 터널링(direct tunneling)에 의한 누설전류가 커져서 리프레시 및 GOI(Gate Oxide Integrity), TDDB(Time-Dependent-Dielectric Breakdown), 문턱전압의 불안정성, 이동도 열화, 높은 대기전류 등의 문제가 발생된다.Particularly, when the gate oxide film has an electrical thickness of 30 μm or less, the operation speed and driving current are very high even at a low voltage, and thus it is highly applicable to logic devices. However, in the case of DRAM cell transistors, leakage current due to direct tunneling increases. Refreshing, gate oxide integrity (GOI), time-dependent-dielectric breakdown (TDDB), threshold voltage instability, mobility deterioration, and high quiescent current are generated.
따라서 셀트랜지스터에는 30Å 이상의 두꺼운 게이트산화막을 사용해야 신뢰성있는 DRAM 동작이 가능하다.Therefore, cell transistors must use a gate oxide thicker than 30Å for reliable DRAM operation.
이와 같이 셀영역의 트랜지스터 특성을 향상시키기 위해서는 셀영역의 트랜지스터의 게이트산화막의 두께를 증가시킬 필요가 있는데 이를 위해 제안된 것이 CMOS 공정에 의한 듀얼 게이트산화막(Dual gate dielectric)의 제조 방법이다. 즉, 셀영역의 소자는 두꺼운 게이트산화막을 형성하고 주변회로영역의 소자는 얇은 게이트산화막을 형성한다.In order to improve the transistor characteristics of the cell region, it is necessary to increase the thickness of the gate oxide layer of the transistor in the cell region. A proposed method for manufacturing the dual gate dielectric layer by the CMOS process is proposed. That is, the device in the cell region forms a thick gate oxide film and the device in the peripheral circuit region forms a thin gate oxide film.
이러한 듀얼 게이트산화막의 종래기술로는 식각방식에 의해 듀얼게이트산화막을 형성하는 제1 방법과 불순물 이온주입에 의한 산화속도 차이를 이용하여 듀얼게이트산화막을 형성하는 제2 방법이 있다.Conventional technologies for such a dual gate oxide film include a first method of forming a dual gate oxide film by an etching method and a second method of forming a dual gate oxide film by using an oxidation rate difference due to impurity ion implantation.
먼저 제1 방법은 1차 산화공정을 통해 얇은 게이트산화막을 성장시키고 주변회로영역의 게이트산화막을 일부 또는 전체를 식각한 후, 2차 산화공정을 통해 게이트산화막이 잔류하던 셀영역에는 두꺼운 게이트산화막을 형성하고, 식각에 의해 게이트산화막이 제거된 주변회로영역에는 얇은 게이트산화막을 형성한다.In the first method, a thin gate oxide film is grown through a first oxidation process, a part or all of the gate oxide film in the peripheral circuit region is etched, and a thick gate oxide film is formed in a cell region where the gate oxide film remains through a second oxidation process. A thin gate oxide film is formed in the peripheral circuit region from which the gate oxide film is removed by etching.
그러나, 제1 방법은 1차 산화공정에 의해 형성된 주변회로영역의 게이트산화막을 제거하기 위한 마스크 공정이 수행되기 때문에 감광막 잔류물에 의해 셀영역의 게이트산화막의 특성이 열화되는 문제가 있다.However, in the first method, since a mask process for removing the gate oxide film in the peripheral circuit region formed by the primary oxidation process is performed, there is a problem in that the characteristics of the gate oxide film in the cell region are degraded by the photoresist residue.
다음으로, 제2 방법은 주변회로영역에 저에너지의 질소를 주입한 후 산화공정을 통해 주변회로영역에는 얇은 게이트산화막을 형성하고, 셀영역에는 두꺼운 게이트산화막을 형성한다. 이때, 질소가 주입된 부분에서의 성장속도가 주입되지 않은 부분에서의 성장속도보다 상대적으로 느리다.Next, in the second method, after injecting low energy nitrogen into the peripheral circuit region, a thin gate oxide film is formed in the peripheral circuit region and a thick gate oxide film is formed in the cell region through an oxidation process. At this time, the growth rate in the portion injected with nitrogen is relatively slower than the growth rate in the portion not injected.
전술한 제2 방법은 공정이 단순한 이점이 있으나, 게이트산화막간 일정 두께 차이를 발생시키기 위해서 질소 주입량을 증가시킬 경우, 주변회로영역의 게이트산화막의 GOI 및 TDDB 특성이 열화되는 문제가 있다.The second method described above has a simple process, but when the nitrogen injection amount is increased to generate a certain thickness difference between the gate oxide films, there is a problem in that the GOI and TDDB characteristics of the gate oxide films in the peripheral circuit region are deteriorated.
따라서, 제1 방법을 적용할 때의 셀영역의 게이트산화막의 열화와 제2 방법을 적용할 때의 주변회로영역의 게이트산화막의 열화를 방지하기 위한 듀얼 게이트산화막 공정이 요구되고 있다.Therefore, a dual gate oxide film process is required to prevent deterioration of the gate oxide film in the cell region when the first method is applied and deterioration of the gate oxide film in the peripheral circuit region when the second method is applied.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 셀영역 및 주변회로영역에서의 게이트산화막의 열화를 방지하는데 적합한 듀얼 게이트산화막을 구비한 반도체소자의 제조 방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device having a dual gate oxide film suitable for preventing deterioration of the gate oxide film in a cell region and a peripheral circuit region. have.
도 1a내지 도 1e는 본 발명의 제1 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도,1A to 1E are cross-sectional views illustrating a method of forming a dual gate oxide film according to a first embodiment of the present invention;
도 2a내지 도 2e는 본 발명의 제2 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도,2A to 2E are cross-sectional views illustrating a method of forming a dual gate oxide film according to a second embodiment of the present invention;
도 3a내지 도 3d는 본 발명의 제3 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도,3A to 3D are cross-sectional views illustrating a method of forming a dual gate oxide film according to a third embodiment of the present invention;
도 4a내지 도 4d는 본 발명의 제4 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도,4A to 4D are cross-sectional views illustrating a method of forming a dual gate oxide film according to a fourth embodiment of the present invention;
도 5는 본 발명에 따른 듀얼 게이트산화막을 갖는 CMOS 소자를 도시한 도면.5 shows a CMOS device having a dual gate oxide film according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 반도체기판 12 : SiO2막11 semiconductor substrate 12 SiO 2 film
13 : SiON막 14 : 감광막패턴13 SiON film 14 Photosensitive film pattern
15 : 후막 게이트산화막 16 : 박막 게이트산화막15 thick film gate oxide film 16 thin film gate oxide film
상기 목적을 달성하기 위한 본 발명의 듀얼 게이트산화막의 형성 방법은 셀영역과 주변회로영역이 정의된 반도체기판상에 옥시나이트라이드막을 형성하는 단계, 상기 옥시나이트라이드막중에서 상기 셀영역상에 형성된 부분을 제거하는 단계, 및 산화 공정을 실시하여 상기 셀영역상에 후막 게이트산화막을 형성함과 동시에 상기 주변회로영역상에 박막 게이트산화막을 형성하는 단계를 포함함을 특징으로 하며, 상기 옥시나이트라이드막을 형성하는 단계는 상기 반도체기판상에 실리콘산화막을 형성하는 단계, 및 상기 실리콘산화막을 상기 옥시나이트라이드막으로 개질시키는 단계를 포함함을 특징으로 하고, 상기 실리콘산화막을 상기 옥시나이트라이드막으로 개질시키는 단계는 NO 가스 분위기의 열처리를 통해 이루어지되, 상기열처리는 500℃∼1000℃의 온도에서 20초∼1시간동안 상기 NO 가스를 5sccm∼10000sccm의 유량으로 흘려주면서 실시하거나, 디커플드플라즈마질화처리하여 이루어짐을 특징으로 한다.A method of forming a dual gate oxide film of the present invention for achieving the above object comprises forming an oxynitride film on a semiconductor substrate having a cell region and a peripheral circuit region defined therein; a portion formed on the cell region of the oxynitride film. And forming a thick gate oxide film on the cell region by performing an oxidation process and simultaneously forming a thin film gate oxide film on the peripheral circuit region, wherein the oxynitride film is formed. The forming may include forming a silicon oxide film on the semiconductor substrate, and modifying the silicon oxide film into the oxynitride film, and modifying the silicon oxide film into the oxynitride film. The step is carried out through a heat treatment of NO gas atmosphere, the heat treatment is 500 ℃ Performed while flowing the NO gas for 20-1 seconds at a temperature of 1000 ℃ at a flow rate of 5sccm~10000sccm or decoupled features a de plasma yirueojim by nitriding.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1a내지 도 1e는 본 발명의 제1 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a dual gate oxide film according to a first embodiment of the present invention.
도 1a에 도시된 바와 같이, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 정의된 반도체기판(11)상에 1차 산화공정을 통해 게이트산화막으로서 SiO2막(12)을 3Å∼30Å의 두께로 형성한다.As shown in FIG. 1A, the SiO 2 film 12 is formed as a gate oxide film on the semiconductor substrate 11 having the cell region I and the peripheral circuit region II defined therein through a first oxidation process. Form to thickness.
도 1b에 도시된 바와 같이, NO 가스 분위기에서 열처리하여 SiO2막(12)을 옥시나이트라이드막(Oxynitride) 즉, SiON막(13)으로 개질시킨다. 이때, NO 가스 분위기의 열처리는, 500℃∼1000℃의 온도에서 20초∼1시간동안 NO 가스를 5sccm∼10000sccm의 유량으로 흘려주면서 실시한다.As shown in FIG. 1B, the SiO 2 film 12 is modified to an oxynitride film, that is, a SiON film 13 by heat treatment in an NO gas atmosphere. At this time, the heat treatment of the NO gas atmosphere is performed while flowing NO gas at a flow rate of 5 sccm to 10000 sccm at a temperature of 500 ° C. to 1000 ° C. for 20 seconds to 1 hour.
도 1c에 도시된 바와 같이, SiON막(13)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변회로영역(Ⅱ)은 덮고 셀영역(Ⅰ)은 노출시키는 감광막패턴(14)을 형성한다. 한편, 감광막 현상후 셀영역내 SiON막(13)상에 잔류하는 감광막 잔류물을 제거하기 위해 산소 플라즈마를 이용하여 5초∼60초동안 플라즈마처리한다.As shown in FIG. 1C, a photosensitive film is coated on the SiON film 13 and patterned by exposure and development to form a photosensitive film pattern 14 covering the peripheral circuit region II and exposing the cell region I. On the other hand, after removing the photoresist film, plasma treatment is performed for 5 seconds to 60 seconds using oxygen plasma to remove the photoresist residue remaining on the SiON film 13 in the cell region.
다음으로, 감광막패턴(14)에 의해 드러나는 셀영역(Ⅰ)내에 SiON막(13)을 습식식각한다. 이때, 습식식각은 BOE(Buffered Oxide Etchant)나 희석된 불산(HF)를 이용한다.Next, the SiON film 13 is wet-etched in the cell region I exposed by the photosensitive film pattern 14. At this time, the wet etching uses BOE (Buffered Oxide Etchant) or diluted hydrofluoric acid (HF).
도 1d에 도시된 바와 같이, 감광막패턴(14)을 스트립한 후 습식세정을 통해 감광막 잔류물을 제거한다. 이때, 습식세정은 피라나(H2SO4+H2O2), SC-1(NH4OH) 용액을 이용한다.As shown in FIG. 1D, the photoresist pattern 14 is stripped, and then the photoresist residue is removed by wet cleaning. At this time, the wet cleaning uses a Pirana (H 2 SO 4 + H 2 O 2 ), SC-1 (NH 4 OH) solution.
도 1e에 도시된 바와 같이, 습식 산화공정을 실시하여 셀영역(Ⅰ)에 후막(thick film) 게이트산화막(15)을 형성하고, 주변회로영역(Ⅱ)에 후막 게이트산화막(15)보다 상대적으로 얇은 박막(thin film) 게이트산화막(16)을 형성하여 듀얼 게이트산화막 공정을 완료한다.As shown in FIG. 1E, a wet oxidation process is performed to form a thick film gate oxide film 15 in the cell region I, and relatively thick film gate oxide film 15 in the peripheral circuit region II. A thin film gate oxide film 16 is formed to complete the dual gate oxide film process.
이와 같이 후막 게이트산화막(15)과 박막 게이트산화막(16)의 두께가 차이가 나는 이유는, 전술한 바와같이 박막 게이트산화막(16)이 형성될 부분에는 산화를 억제하는 질소(N)가 함유된 SiON막(13)이 미리 형성되어 있어 습식 산화공정시 후막 게이트산화막(15)에 비해 산화속도가 느리기 때문이다. 결국, 주변회로영역(Ⅱ)에 형성되는 박막 게이트산화막(16)은 질소를 함유하고 있다.The reason why the thicknesses of the thick gate oxide film 15 and the thin film gate oxide film 16 are different from each other is that, as described above, the portion where the thin film gate oxide film 16 is to be formed contains nitrogen (N) that inhibits oxidation. This is because the SiON film 13 is formed in advance and the oxidation rate is slower than that of the thick film gate oxide film 15 during the wet oxidation process. As a result, the thin film gate oxide film 16 formed in the peripheral circuit region II contains nitrogen.
도 2a내지 도 2e는 본 발명의 제2 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a dual gate oxide film according to a second embodiment of the present invention.
도 2a에 도시된 바와 같이, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 정의된 반도체기판(21)상에 1차 산화공정을 통해 게이트산화막으로서 SiO2막(22)을 3Å∼30Å의 두께로 형성한다.As shown in FIG. 2A, the SiO 2 film 22 as a gate oxide film is formed on the semiconductor substrate 21 on which the cell region I and the peripheral circuit region II are defined through a first oxidation process. Form to thickness.
도 2b에 도시된 바와 같이, 바이어스파워(bias power)를 인가하지 않는 디커플드플라즈마질화처리(Decoupled Plasma nitridation; DPN)를 수행하여 SiO2막(22)을 옥시나이트라이드막인 SiON막(23)으로 개질시킨다.As shown in FIG. 2B, the SiO 2 film 22 is an oxynitride film SiON film 23 by performing decoupled plasma nitridation (DPN) without applying bias power. ).
여기서, 디커플드플라즈마질화처리시 SiON막(23)을 형성하기 위해 N2, N2O, NO, NF3및 NH3로 이루어진 그룹중에서 선택되는 질소함유 가스 또는 이들 가스들의 혼합가스와 산소(O2), 오존(O3) 등의 산소함유 가스를 혼합하여 플라즈마 소스가스로 사용한다.Here, in order to form the SiON film 23 during the decoupled plasma nitriding treatment, a nitrogen-containing gas selected from the group consisting of N 2 , N 2 O, NO, NF 3, and NH 3 or a mixed gas and oxygen of these gases ( Oxygen-containing gases such as O 2 ) and ozone (O 3 ) are mixed and used as a plasma source gas.
예컨대, 디커플드플라즈마질화처리는, 플라즈마 소스가스를 5sccm∼500sccm의 유량으로 주입시키고, 5mtorr∼50mtorr의 진공도를 유지한 상태에서 기판온도는 0℃∼600℃을 유지하며, 100W∼1000W의 소스파워를 인가하면서 5초∼500초동안 진행된다.For example, in the decoupled plasma nitriding treatment, the plasma source gas is injected at a flow rate of 5 sccm to 500 sccm, and the substrate temperature is maintained at 0 ° C. to 600 ° C. while maintaining a vacuum degree of 5 mtorr to 50 mtorr, and a source of 100 W to 1000 W. It proceeds for 5 to 500 seconds while applying power.
한편, 플라즈마 소스가스는 질소(N)를 함유하고 있는데, 질소(N)는 산화공정시 산화속도를 감소시키는 것으로 알려져 있으며, 디커플드플라즈마질화처리(DPN)에 의한 질소주입은 이온주입방식에 비해 기판 손상을 적게 준다.On the other hand, the plasma source gas contains nitrogen (N), which is known to reduce the oxidation rate during the oxidation process, and the nitrogen injection by the decoupled plasma nitriding treatment (DPN) is performed by ion implantation. Less damage to the substrate.
도 2c에 도시된 바와 같이, SiON막(23)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변회로영역(Ⅱ)은 덮고 셀영역(Ⅰ)은 노출시키는 감광막패턴(24)을 형성한다. 한편, 감광막 현상후 셀영역(Ⅰ)내 SiON막(23)상에 잔류하는 감광막 잔류물을 제거하기 위해 산소 플라즈마를 이용하여 5초∼60초동안 플라즈마처리한다.As shown in FIG. 2C, a photosensitive film is coated on the SiON film 23 and patterned by exposure and development to form a photosensitive film pattern 24 covering the peripheral circuit region II and exposing the cell region I. On the other hand, in order to remove the photoresist residue remaining on the SiON film 23 in the cell region I after the photoresist development, plasma treatment is performed for 5 seconds to 60 seconds using oxygen plasma.
다음으로, 감광막패턴(24)에 의해 드러나는 셀영역(Ⅰ)내에 SiON막(23)을 습식식각한다. 이때, 습식식각은 BOE나 희석된 불산(HF)를 이용한다.Next, the SiON film 23 is wet-etched in the cell region I exposed by the photosensitive film pattern 24. At this time, the wet etching uses BOE or diluted hydrofluoric acid (HF).
도 2d에 도시된 바와 같이, 감광막패턴(24)을 스트립한 후 습식세정을 통해 감광막 잔류물을 제거한다. 이때, 습식세정은 피라나(H2SO4+H2O2), SC-1(NH4OH) 용액을 이용한다.As shown in FIG. 2D, the photoresist pattern 24 is stripped, and then the photoresist residue is removed by wet cleaning. At this time, the wet cleaning uses a Pirana (H 2 SO 4 + H 2 O 2 ), SC-1 (NH 4 OH) solution.
도 2e에 도시된 바와 같이, 습식 산화공정을 실시하여 셀영역(Ⅰ)에 후막 게이트산화막(25)을 형성하고, 주변회로영역(Ⅱ)에 후막 게이트산화막(25)보다 상대적으로 얇은 박막 게이트산화막(26)을 형성하여 듀얼 게이트산화막 공정을 완료한다.As shown in FIG. 2E, a wet oxide process is performed to form a thick film gate oxide film 25 in the cell region I, and a thin film gate oxide film relatively thinner than the thick film gate oxide film 25 in the peripheral circuit region II. (26) is formed to complete the dual gate oxide film process.
이와 같이 후막 게이트산화막(25)과 박막 게이트산화막(26)의 두께가 차이가 나는 이유는, 전술한 바와같이 박막 게이트산화막(26)이 형성될 부분에는 산화를 억제하는 질소(N)가 함유된 SiON막(23)이 미리 형성되어 있어 습식 산화공정시 후막 게이트산화막(25)에 비해 산화속도가 느리기 때문이다. 결국, 주변회로영역(Ⅱ)에 형성되는 박막 게이트산화막(26)은 질소를 함유하고 있다.The reason why the thicknesses of the thick gate oxide film 25 and the thin film gate oxide film 26 are different from each other is that, as described above, the portion where the thin film gate oxide film 26 is to be formed contains nitrogen (N) that inhibits oxidation. This is because the SiON film 23 is formed in advance so that the oxidation rate is slower than that of the thick film gate oxide film 25 in the wet oxidation process. As a result, the thin film gate oxide film 26 formed in the peripheral circuit region II contains nitrogen.
도 3a 내지 도 3d는 본 발명의 제3실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of forming a dual gate oxide film according to a third embodiment of the present invention.
도 3a에 도시된 바와 같이, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 정의된 반도체기판(31)상에 NO 또는 N2O 가스 분위기의 열처리를 통해 옥시나이트라이드막인 SiON막(32)을 형성한다. 이때, NO 가스 분위기의 열처리는, 500℃∼1000℃의 온도에서 20초∼1시간동안 NO 또는 N2O 가스를 5sccm∼10000sccm의 유량으로 흘려주면서 실시한다.As shown in FIG. 3A, the SiON film 32, which is an oxynitride film, is subjected to a heat treatment in a NO or N 2 O gas atmosphere on the semiconductor substrate 31 on which the cell region I and the peripheral circuit region II are defined. ). At this time, the heat treatment of the NO gas atmosphere is performed while flowing NO or N 2 O gas at a flow rate of 5 sccm to 10000 sccm at a temperature of 500 ° C. to 1000 ° C. for 20 seconds to 1 hour.
도 3b에 도시된 바와 같이, SiON막(32)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변회로영역(Ⅱ)은 덮고 셀영역(Ⅰ)은 노출시키는 감광막패턴(33)을 형성한다. 한편, 감광막 현상후 셀영역(Ⅰ)내 SiON막(32)상에 잔류하는 감광막 잔류물을 제거하기 위해 산소 플라즈마를 이용하여 5초∼60초동안 플라즈마처리한다.As shown in FIG. 3B, a photosensitive film is coated on the SiON film 32 and patterned by exposure and development to form a photosensitive film pattern 33 covering the peripheral circuit region II and exposing the cell region I. On the other hand, plasma treatment is performed for 5 to 60 seconds using oxygen plasma to remove the photoresist residue remaining on the SiON film 32 in the cell region I after the photoresist development.
다음으로, 감광막패턴(33)에 의해 드러나는 셀영역(Ⅰ)내에 SiON막(32)을 습식식각한다. 이때, 습식식각은 BOE나 희석된 불산(HF)를 이용한다.Next, the SiON film 32 is wet-etched in the cell region I exposed by the photosensitive film pattern 33. At this time, the wet etching uses BOE or diluted hydrofluoric acid (HF).
도 3c에 도시된 바와 같이, 감광막패턴(33)을 스트립한 후 습식세정을 통해 감광막 잔류물을 제거한다. 이때, 습식세정은 피라나(H2SO4+H2O2), SC-1(NH4OH) 용액을 이용한다.As shown in FIG. 3C, the photoresist pattern 33 is stripped, and then the photoresist residue is removed by wet cleaning. At this time, the wet cleaning uses a Pirana (H 2 SO 4 + H 2 O 2 ), SC-1 (NH 4 OH) solution.
도 3d에 도시된 바와 같이, 습식 2차 산화공정을 실시하여 셀영역(Ⅰ)에 후막 게이트산화막(34)을 형성하고, 주변회로영역(Ⅱ)에 후막 게이트산화막(34)보다 상대적으로 얇은 박막 게이트산화막(35)을 형성하여 듀얼 게이트산화막 공정을 완료한다.As shown in FIG. 3D, a wet secondary oxidation process is performed to form a thick film gate oxide film 34 in the cell region I, and a thin film relatively thinner than the thick film gate oxide film 34 in the peripheral circuit region II. The gate oxide film 35 is formed to complete the dual gate oxide film process.
이와 같이 후막 게이트산화막(34)과 박막 게이트산화막(35)의 두께가 차이가 나는 이유는, 전술한 바와같이 박막 게이트산화막(35)이 형성될 부분에는 산화를 억제하는 질소(N)가 함유된 SiON막(32)이 미리 형성되어 있어 습식 산화공정시 후막 게이트산화막(34)에 비해 산화속도가 느리기 때문이다. 결국, 주변회로영역(Ⅱ)에 형성되는 박막 게이트산화막(35)은 질소를 함유하고 있다.The reason why the thicknesses of the thick gate oxide film 34 and the thin film gate oxide film 35 are different from each other is that, as described above, the portion where the thin film gate oxide film 35 is to be formed contains nitrogen (N) that inhibits oxidation. This is because the SiON film 32 is formed in advance and the oxidation rate is slower than that of the thick film gate oxide film 34 in the wet oxidation process. As a result, the thin film gate oxide film 35 formed in the peripheral circuit region II contains nitrogen.
도 4a 내지 도 4d는 본 발명의 제4 실시예에 따른 듀얼 게이트산화막의 형성방법을 도시한 공정 단면도이다.4A to 4D are cross-sectional views illustrating a method of forming a dual gate oxide film according to a fourth embodiment of the present invention.
도 4a에 도시된 바와 같이, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 정의된 반도체기판(41)을 직접 디커플드플라즈마질화처리(DPN)하여 반도체기판(41)상에 옥시나이트라이드막인 SiON막(42)을 형성한다.As shown in FIG. 4A, the semiconductor substrate 41 in which the cell region I and the peripheral circuit region II are defined is directly decoupled plasma nitrided (DPN) to oxynitride on the semiconductor substrate 41. A SiON film 42 as a film is formed.
여기서, 직접 디커플드플라즈마질화처리시 SiON막(42)을 형성하기 위해 NO, N2O를 플라즈마 소스가스로 사용하거나, N2, N2O, NO, NF3및 NH3로 이루어진 그룹중에서 선택되는 질소함유 가스와 산소(O2), 오존(O3) 등의 산소함유 가스를 혼합하여 플라즈마 소스가스로 사용한다.Here, in order to form the SiON film 42 during direct decoupled plasma nitriding treatment, NO, N 2 O is used as the plasma source gas, or N 2 , N 2 O, NO, NF 3 and NH 3 The selected nitrogen-containing gas and oxygen-containing gas such as oxygen (O 2 ) and ozone (O 3 ) are mixed and used as the plasma source gas.
예컨대, 디커플드플라즈마질화처리는, 플라즈마 소스가스를 5sccm∼500sccm의 유량으로 주입시키고, 5mtorr∼50mtorr의 진공도를 유지한 상태에서 기판온도는 0℃∼600℃을 유지하며, 100W∼1000W의 소스파워를 인가하면서 5초∼500초동안 진행된다.For example, in the decoupled plasma nitriding treatment, the plasma source gas is injected at a flow rate of 5 sccm to 500 sccm, and the substrate temperature is maintained at 0 ° C. to 600 ° C. while maintaining a vacuum degree of 5 mtorr to 50 mtorr, and a source of 100 W to 1000 W. It proceeds for 5 to 500 seconds while applying power.
한편, 플라즈마 소스가스는 질소(N)를 함유하고 있는데, 질소(N)는 산화공정시 산화속도를 감소시키는 것으로 알려져 있으며, 디커플드플라즈마질화처리(DPN)에 의한 질소주입은 이온주입방식에 비해 기판 손상을 적게 준다.On the other hand, the plasma source gas contains nitrogen (N), which is known to reduce the oxidation rate during the oxidation process, and the nitrogen injection by the decoupled plasma nitriding treatment (DPN) is performed by ion implantation. Less damage to the substrate.
도 4b에 도시된 바와 같이, SiON막(42)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변회로영역(Ⅱ)은 덮고 셀영역(Ⅰ)은 노출시키는 감광막패턴(43)을 형성한다. 한편, 감광막 현상후 셀영역(Ⅰ)내 SiON막(42)상에 잔류하는 감광막 잔류물을 제거하기 위해 산소 플라즈마를 이용하여 5초∼60초동안 플라즈마처리한다.As shown in FIG. 4B, a photosensitive film is coated on the SiON film 42 and patterned by exposure and development to form a photosensitive film pattern 43 covering the peripheral circuit region II and exposing the cell region I. On the other hand, in order to remove the photoresist residue remaining on the SiON film 42 in the cell region I after the photoresist development, plasma treatment is performed for 5 seconds to 60 seconds using oxygen plasma.
다음으로, 감광막패턴(43)에 의해 드러나는 셀영역(Ⅰ)내에 SiON막(42)을 습식식각한다. 이때, 습식식각은 BOE(Buffered Oxide Etchant)나 희석된 불산(HF)를 이용한다.Next, the SiON film 42 is wet-etched in the cell region I exposed by the photosensitive film pattern 43. At this time, the wet etching uses BOE (Buffered Oxide Etchant) or diluted hydrofluoric acid (HF).
도 4c에 도시된 바와 같이, 감광막패턴(43)을 스트립한 후 습식세정을 통해 감광막 잔류물을 제거한다. 이때, 습식세정은 피라나(H2SO4+H2O2), SC-1(NH4OH) 용액을 이용한다.As shown in FIG. 4C, the photoresist pattern 43 is stripped, and then the photoresist residue is removed by wet cleaning. At this time, the wet cleaning uses a Pirana (H 2 SO 4 + H 2 O 2 ), SC-1 (NH 4 OH) solution.
도 4d에 도시된 바와 같이, 습식 산화공정을 실시하여 셀영역(Ⅰ)에 후막 게이트산화막(44)을 형성하고, 주변회로영역에 후막 게이트산화막(44)보다 상대적으로 얇은 박막 게이트산화막(45)을 형성하여 듀얼 게이트산화막 공정을 완료한다.As shown in FIG. 4D, the wet oxide process is performed to form the thick gate oxide film 44 in the cell region I, and the thin film gate oxide film 45 that is relatively thinner than the thick gate oxide film 44 in the peripheral circuit region. To form a dual gate oxide film process.
이와 같이 후막 게이트산화막(44)과 박막 게이트산화막(45)의 두께가 차이가 나는 이유는, 전술한 바와같이 박막 게이트산화막(45)이 형성될 부분에는 산화를억제하는 질소(N)가 함유된 SiON막(42)이 미리 형성되어 있어 습식 산화공정시 후막 게이트산화막(44)에 비해 산화속도가 느리기 때문이다. 결국, 주변회로영역(Ⅱ)에 형성되는 박막 게이트산화막(45)은 질소를 함유하고 있다.The reason why the thicknesses of the thick gate oxide film 44 and the thin film gate oxide film 45 are different from each other is that, as described above, the portion where the thin film gate oxide film 45 is to be formed contains nitrogen (N) that inhibits oxidation. This is because the SiON film 42 is formed in advance so that the oxidation rate is slower than that of the thick film gate oxide film 44 during the wet oxidation process. As a result, the thin film gate oxide film 45 formed in the peripheral circuit region II contains nitrogen.
전술한 바와 같은 제1 실시예 내지 제4 실시예에 따르면, 주변회로영역(Ⅱ)에 형성되는 박막 게이트산화막의 경우, 질소가 함유됨에 따라 GOI, TDDB 측면에서는 열화가 다소 있을 수 있으나, 후속 재산화(Reoxidation) 공정을 거치면 옥시나이트라이드막에 비해 질소 농도가 줄어들기 때문에 상대적으로 덜 열화된 특성을 갖는다. 특히, 옥시나이트라이드막은 질소 이온주입에 의한 게이트산화막보다 훨씬 좋은 TDDB 특성을 보인다.According to the first to fourth embodiments as described above, in the case of the thin film gate oxide film formed in the peripheral circuit region (II), deterioration may occur somewhat in terms of GOI and TDDB as nitrogen is contained, but subsequent properties Reoxidation process is relatively less deteriorated because nitrogen concentration is reduced compared to oxynitride film. In particular, the oxynitride film shows much better TDDB characteristics than the gate oxide film by nitrogen ion implantation.
전술한 본 발명의 실시예에서 설명한 바와 같이, 주변회로영역(Ⅱ)에 질소이온주입을 실시하지 않고도 박막 게이트산화막을 형성하므로 GOI, TDDB 특성 열화를 방지하고, 아울러 감광막패턴을 형성하기 위한 마스크 공정이 주변회로영역(Ⅱ)에서만 이루어지기 때문에 셀영역(Ⅰ)에서 형성되는 후막 게이트산화막의 특성 열화가 방지된다.As described in the above-described embodiment of the present invention, the thin film gate oxide film is formed without performing nitrogen ion implantation in the peripheral circuit region (II), thereby preventing GOI and TDDB characteristics from deteriorating and forming a photoresist pattern. Since this is made only in the peripheral circuit region II, the deterioration of the characteristics of the thick film gate oxide film formed in the cell region I is prevented.
전술한 본 발명은 듀얼 게이트산화막뿐만 아니라, 트리플(triple) 게이트산화막을 구비하는 반도체소자에도 적용 가능하고, 다마신 공정을 적용하는 반도체소자에도 적용 가능하다.The present invention described above is applicable not only to a dual gate oxide film but also to a semiconductor device having a triple gate oxide film, and to a semiconductor device to which a damascene process is applied.
또한, 본 발명은 임베디드형(embedded type)의 메모리소자(DRAM, SRAM, FLASH)와 로직소자를 결합한 시스템온칩(System On Chip;SOC)과 같은 소자에서 로직소자영역과 메모리소자의 주변회로영역에서는 얇은 게이트산화막을 형성하고, 메모리소자의 셀영역에서는 두꺼운 게이트산화막을 형성하는 방법에도 적용 가능하다.In addition, the present invention is in the logic device area and the peripheral circuit area of the memory device in a device such as a system on chip (SOC) combined with embedded memory devices (DRAM, SRAM, FLASH) and logic devices It is also applicable to the method of forming a thin gate oxide film and forming a thick gate oxide film in the cell region of the memory device.
도 5는 본 발명에 따른 듀얼 게이트산화막을 갖는 CMOS 소자를 도시한 도면이다.5 is a diagram illustrating a CMOS device having a dual gate oxide film according to the present invention.
도 5를 참조하면, 반도체기판(51)의 셀영역(Ⅰ)상에 후막 게이트산화막(52)이 형성되고, 반도체기판(51)의 주변회로영역(Ⅱ)상에 질소가 함유된 박막 게이트산화막(53)이 형성되며, 후막 게이트산화막(52)과 박막 게이트산화막(53)상에 게이트전극을 이루는 폴리실리콘막(54)과 질화금속막(55)이 형성된다. 여기서, 폴리실리콘막(54)은 셀영역의 nMOSFET 및 주변회로영역의 nMOSFET의 게이트전극으로 이용되는 경우에는 4.1eV∼4.2eV 정도의 일함수(work function)를 갖는 n+-폴리실리콘막을 사용하며, 주변회로영역의 pMOSFET의 게이트전극으로 이용되는 경우에는 4.9eV∼5.1eV 정도의 일함수를 갖는 p+-폴리실리콘막을 사용한다. 그리고, 질화금속막(55)은 TaN, TaSiN, TiN, TiAlN, TiSiN, RuTaN, WN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN 및 IrTiN로 이루어진 그룹중에서 선택되는 하나를 이용한다. 그리고, 폴리실리콘막(54) 및 질화금속막(55)의 총 두께는 10Å∼2000Å이다.Referring to FIG. 5, a thick gate oxide film 52 is formed on the cell region I of the semiconductor substrate 51, and a thin film gate oxide film containing nitrogen on the peripheral circuit region II of the semiconductor substrate 51. A 53 is formed, and a polysilicon film 54 and a metal nitride film 55 forming a gate electrode are formed on the thick gate oxide film 52 and the thin film gate oxide film 53. Here, the polysilicon film 54 uses an n + -polysilicon film having a work function of about 4.1 eV to 4.2 eV when used as a gate electrode of the nMOSFET in the cell region and the nMOSFET in the peripheral circuit region. When used as a gate electrode of a pMOSFET in the peripheral circuit region, a p + -polysilicon film having a work function of about 4.9 eV to 5.1 eV is used. The metal nitride film 55 uses one selected from the group consisting of TaN, TaSiN, TiN, TiAlN, TiSiN, RuTaN, WN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN, and IrTiN. The total thickness of the polysilicon film 54 and the metal nitride film 55 is 10 kPa to 2000 kPa.
한편, 게이트전극은 전술한 폴리실리콘/질화금속막의 적층구조외에 폴리실리콘 단독구조, 질화금속막의 단독구조, 폴리실리콘/질화금속/실리사이드의 적층구조, 폴리실리콘/질화금속/텅스텐의 적층구조도 가능하다.On the other hand, in addition to the above-described lamination structure of the polysilicon / metal nitride film, the gate electrode may be made of a polysilicon alone structure, a metal nitride film alone structure, a polysilicon / metal nitride / silicide lamination structure, and a polysilicon / metal nitride / tungsten lamination structure. Do.
이 때, 실리사이드 또는 텅스텐은 게이트전극의 저항을 낮추기 위해 적용된 물질로, 50Å∼2000Å 두께로 증착된다. 실리사이드로는 텅스텐실리사이드(W-silicide), 코발트실리사이드(Co-silicide), 티타늄실리사이드(Ti-silicide), 몰리브덴실리사이드(Mo-silicide), 탄탈륨실리사이드(Ta-silicide), 니오비윰실리사이드(Nb-silicide)를 이용한다.In this case, silicide or tungsten is a material applied to lower the resistance of the gate electrode, and is deposited to have a thickness of 50 kPa to 2000 kPa. The silicides include tungsten silicide (W-silicide), cobalt silicide (Co-silicide), titanium silicide (Ti-silicide), molybdenum silicide (Mo-silicide), tantalum silicide (Ta-silicide) and niobium silicide (Nb- silicide).
다음으로, 게이트전극의 에지에 정렬되어 LDD(Lightly Doped Drain) 영역(56)이 형성되고, 게이트전극의 양측벽에 스페이서(57)가 형성되며, LDD 영역(56)에 접하여 반도체기판(51)내에 소스/드레인영역(58)이 형성된다.Next, an LDD (Lightly Doped Drain) region 56 is formed in alignment with the edge of the gate electrode, spacers 57 are formed on both sidewalls of the gate electrode, and the semiconductor substrate 51 is in contact with the LDD region 56. Source / drain regions 58 are formed therein.
상술한 바와 같은 CMOS 소자에서, 박막 게이트산화막(53)과 후막 게이트산화막(52)의 듀얼 게이트산화막은 제1 실시예 내지 제4 실시예에 의해 형성된 것으로, 셀영역(Ⅰ)에 형성된 후막 게이트산화막(52)의 두께를 주변회로영역(Ⅱ)에 형성된 박막 게이트산화막(53)보다 작게는 2Å 크게는 10Å 이상 두껍게 형성할 수 있다. 따라서, 셀영역(Ⅰ)의 트랜지스터에 높은 전압을 인가해도 충분한 게이트산화막의 두께를 확보할 수 있다.In the CMOS device as described above, the dual gate oxide films of the thin film gate oxide film 53 and the thick film gate oxide film 52 are formed by the first to fourth embodiments, and are formed in the cell region I. The thickness of 52 can be formed to be 2 Å or more and 10 Å or more thicker than the thin film gate oxide film 53 formed in the peripheral circuit region II. Therefore, even if a high voltage is applied to the transistor of the cell region I, a sufficient gate oxide film thickness can be ensured.
한편, 상술한 본 발명에 따른 질소가 함유된 게이트산화막을 MOSFET에 적용하는 경우, 핫캐리어(hot carrier)의 수명(life time)이 상대적으로 증가되는 효과를 얻을 수 있다.On the other hand, when the gate oxide film containing nitrogen according to the present invention as described above is applied to the MOSFET, it is possible to obtain an effect that the life time of the hot carrier is relatively increased.
또한, 본 발명에 따른 게이트산화막을 표면채널 pMOSFET 소자에 적용하는 경우, pMOSFET를 구현하기 위해 p형 폴리실리콘막을 게이트전극으로 사용하는 경우 p형 폴리실리콘막으로부터 반도체기판으로의 보론침투(boron penetration)에 의한문턱전압 이동(shift) 및 문턱전압 변이(fluctuation)을 억제할 수 있다.In addition, when the gate oxide film according to the present invention is applied to a surface channel pMOSFET device, when a p-type polysilicon film is used as a gate electrode to implement a pMOSFET, boron penetration from the p-type polysilicon film to the semiconductor substrate is performed. Threshold voltage shift and threshold voltage fluctuation due to this can be suppressed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 셀영역과 주변회로영역 두영역에서 게이트산화막의 GOI, TDDB 특성 열화를 방지하므로써 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the reliability of the device by preventing GOI and TDDB characteristics of the gate oxide film from deteriorating in both the cell region and the peripheral circuit region.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609236B1 (en) * | 2003-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming dual gate |
| KR100611784B1 (en) * | 2004-12-29 | 2006-08-10 | 주식회사 하이닉스반도체 | Semiconductor device with multi-gate dielectric and method for manufacturing the same |
| US7776761B2 (en) | 2005-11-28 | 2010-08-17 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having multiple gate insulating layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609236B1 (en) * | 2003-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming dual gate |
| KR100611784B1 (en) * | 2004-12-29 | 2006-08-10 | 주식회사 하이닉스반도체 | Semiconductor device with multi-gate dielectric and method for manufacturing the same |
| US7563726B2 (en) | 2004-12-29 | 2009-07-21 | Hynix Semiconductor Inc. | Semiconductor device with multiple gate dielectric layers and method for fabricating the same |
| US7776761B2 (en) | 2005-11-28 | 2010-08-17 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having multiple gate insulating layer |
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