TW432638B - Manufacturing method for MOS transistor - Google Patents
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- TW432638B TW432638B TW89101468A TW89101468A TW432638B TW 432638 B TW432638 B TW 432638B TW 89101468 A TW89101468 A TW 89101468A TW 89101468 A TW89101468 A TW 89101468A TW 432638 B TW432638 B TW 432638B
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;^ 4 32 6 3 8 五、發明說明(1) 丨 發明之領域 - 本發明提供一種製作金屬氧化半導體 (roetal-oxide-semiconductor,MOS)電晶體的方法,尤指 一種製作P型金屬氧化半導體電晶體(PM0S)的方法。 背景說明 | 隨著半導體積集度的增加,具有低耗能優點的互補式 金屬氧化半導艘(complementary metal-oxide-semi conduct or, CMOS)電晶體已逐漸地取代 I 了 N型金屬氧化半導體(NMOS)的地位。CMOS電晶體是由兩 |種相互補的PM0S電晶體與NM0S電晶體所組.成的另一種基本 I :電子元件。P Μ 0 S電晶體主要包含有一閘極.(gate)、—半導 i體電性為P型之源極與沒極(source and drain)以及一與 丨; '源極與沒極電性相反之麥基底(silic〇n substrate)。 ! ]^ 4 32 6 3 8 V. Description of the invention (1) 丨 Field of invention-The present invention provides a method for manufacturing a metal oxide semiconductor (MOS) transistor, especially a method for manufacturing a P-type metal oxide semiconductor Transistor (PM0S) method. Background note | With the increase of semiconductor accumulation, complementary metal-oxide-semi conduct or (CMOS) transistors with the advantage of low energy consumption have gradually replaced I-type N-type metal oxide semiconductors (NMOS) status. CMOS transistor is another basic I composed of two complementary PM0S transistors and NM0S transistors. I: electronic components. The P Μ 0 S transistor mainly includes a gate. The semiconducting body is P-type source and drain and source and drain; and the source and non-polarity Opposite wheaton substrate. !]
I |. 習知製作pM〇S電晶體的方法是以硼原子作為摻質 ! (d 〇 p a η 1:)進行重捧雜沒極(heavily doped drain', HDD)以 I i及源極與沒極的摻雜(doping)。由於硼原子的體積小,因| 此容易產生外擴散(out diffusion)現象。當半導體製程 I 的線寬小於0.1 8微米甚至0.1 5微米以下時,硼原子的外擴 散現象將嚴重影響PM0S電晶體的電性。此外,習知製作 PM0S電晶體的方法以一二氧化矽層作為側壁子(spacer)形I |. The conventional method for making pM〇S transistor is to use boron atom as dopant! (d 〇 p a η 1 :) Heavily doped drain '(HDD) is doped with I i and source and non-electrode. Due to the small volume of the boron atom, an out diffusion phenomenon is prone to occur. When the line width of semiconductor process I is less than 0.1 8 microns or even less than 0.1 5 microns, the external diffusion of boron atoms will seriously affect the electrical properties of the PMOS transistor. In addition, the conventional method for making a PM0S transistor uses a silicon dioxide layer as a spacer shape.
第4頁 -432638 I 1 1 ** ~· - — — · _ · 一 ~~ _ ·- ——. — - __Page 4 -432638 I 1 1 ** ~ ·-— — · _ · One ~~ _ ·-——. —-__
I五、發明說明(2) I I成時的‘触刻停止層,會在離子佈植製程中產生氧強化擴散 i | (oxide-enhanced di f fusion, OED)現象,而二氧化石夕層 丨 |更會進一步加速删離子的外擴散,使HDD内的硼離子漢度 | 丨下降。因此需要改善習知製程,以提高產品的品質。 | '^ , ! j 清參閱圖一至圖四,圖一至圖四即為習知於一半導體 I晶片10表面製作一 PMOS (P-type metal-oxide-semiconductor)電晶體30的方法示意圖。如 圖一所示,半導體晶片10包含有一矽基底(silicon substrate)12,一由兩個淺溝(shallow trench)l 4所隔離 之N型井(N we U ) 11設於矽基底1 2表面,以及一閘極 (gate) 22設於N型井11之表面。閘極22包含有一由二氧化 矽(silicon dioxide, SiO 2)所構成之介電層2 0設於N型井 11之上,用來做為PM0S電晶體30的閘極氧化層(gate | oxide),以及一摻雜多晶矽層21設於介電層20表面,用來 丨作為PM0S電晶體30的閘極導電層(gate electrode) » ! j 如圖二所示,習知方法是先於半導體晶片10表面均勻 | 地形成一由二氧化矽所構成的襯氧化(1 iner oxide)層 i 1 6 ’並覆蓋於閘極2 2表面。接著進行一較輕摻雜(p -)離子 佈植製程’於閑極22兩侧的矽基底1 2表面形成PM0S電晶體 j 3 0的重摻雜渡極(heavily doped drain, HDD)23。P離子 佈植製程中所使用的硼離子劑量約為lx 1 〇 !笙5x 1 〇 is atoms/cm2’能量約為ι〇至15 Kev。接著在襯氧化層16表I. 5. Description of the invention (2) The "contact stop layer" at the time of II will produce an oxygen-enhanced diffusion i | (oxide-enhanced di f fusion, OED) phenomenon in the ion implantation process, and the dioxide layer | It will further accelerate the external diffusion of deleted ions, making the boron ions in the HDD | 丨 decrease. Therefore, it is necessary to improve the conventional process to improve the quality of products. '^,! j Refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of a method for manufacturing a PMOS (P-type metal-oxide-semiconductor) transistor 30 on the surface of a semiconductor I wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12, and an N-type well (N we U) 11 separated by two shallow trenches 14 is provided on the surface of the silicon substrate 12. A gate 22 is provided on the surface of the N-type well 11. The gate electrode 22 includes a dielectric layer 20 made of silicon dioxide (SiO 2), which is disposed on the N-type well 11 and serves as a gate oxide layer of the PM0S transistor 30. ), And a doped polycrystalline silicon layer 21 is provided on the surface of the dielectric layer 20 and serves as a gate electrode of the PM0S transistor 30 »! As shown in Figure 2, the conventional method is prior to the semiconductor The surface of the wafer 10 is uniformly formed with a 1 iner oxide layer i 1 6 ′ composed of silicon dioxide and covers the surface of the gate electrode 2 2. Next, a lightly doped (p-) ion implantation process is performed to form a heavily doped drain (HDD) 23 of a PM0S transistor j 3 0 on the surface of the silicon substrate 12 on both sides of the free electrode 22. The dose of boron ions used in the P ion implantation process is about 1 × 10! 5 × 10 is atoms / cm2, and the energy is about ι0 to 15 Kev. Next in the lining oxide layer 16
第5頁 _________________________ _______ 五、發明說明(3) 面均勻地形成一氮矽(silicon nitride)層18。- 形成襯氧化層1 6的主要目的是於後續形成氮化妙側壁 丨子時作為蝕刻停止層(stop layer),並作為氮化矽層的熱 |應力緩衝層(buf f er 1 ayer)。然而’由於硼原子有向襯氧 f層16擴散的趨勢,造成HDD 23中的硼原子濃度不易控 |制°此外襯氧化層1 6亦會造成在P雜子佈植過程中劑量"損 |失(dosage loss)的問題以及氧強化擴散(〇ED)現象。氧強 | j氧原子的’小j | 如圖三所不,再進行一回蝕刻(etching back)製程,| |向下去除氮矽層1 8直至襯氧化層1 6的表面,並使殘留於閘 | |極2 2兩側之襯氧化層1 6表面的氮矽層1 8形.成兩侧壁子 丨 |(spacer)19。然後進行一較重摻雜(p +)離子佈植製程,於 |Page 5 _________________________ _______ V. Description of the Invention (3) A silicon nitride layer 18 is uniformly formed on the surface. -The main purpose of forming the liner oxide layer 16 is to serve as an etch stop layer and a thermal stress buffer layer (buf f er 1 ayer) for the silicon nitride layer when the nitrided sidewalls are subsequently formed. However, 'due to the tendency of the boron atoms to diffuse to the oxygen-lined f-layer 16, the concentration of boron atoms in HDD 23 is not easy to control. In addition, the oxide-lined layer 16 will also cause a dose " damage during the implantation of P heterozygotes. The problem of loss loss and the phenomenon of oxygen-enhanced diffusion (〇ED). Oxygen strength | 'small j' of the oxygen atom | As shown in Figure 3, another etching back process is performed, | | The nitrogen silicon layer 1 8 is removed down to the surface of the oxide layer 16 and left behind At the gate | | the nitrogen silicon layer 18 on the surface of the lining oxide layer 16 on both sides of the pole 2 2 is shaped into two side walls 19 (spacer) 19. Then perform a heavier doped (p +) ion implantation process.
|閘極22兩側的矽基底1 2上形成pm〇S電晶體30的源極與汲極| | 24。P離子佈植製程中所用的摻質為硼原子或氟化硼 I | (boron fluoride ion,BFZ+)離子,其植入能量約為 1() | 丨 Kev’ 劑量(dosage)介於 2x iQi6at〇ms/cm^ 丨 間。在完成P離子佈植製程之後,需再進行一回衣 (annealing)製程,利用1〇〇〇至1〇5〇它的高溫,使植入的| 棚離子藉由擴散(diffusion),形成所要之濃度分佈 | (profile),同時修補在離子佈植製程中受損之矽基底丨2 | 表面的晶格結構。 丨The source and the drain of the pMOS transistor 30 are formed on the silicon substrate 12 on both sides of the gate 22 || 24. The dopant used in the P ion implantation process is boron atom or boron fluoride I | (boron fluoride ion (BFZ +) ion), and its implantation energy is about 1 () | 丨 Kev 'dosage is between 2x iQi6at. ms / cm ^. After the P ion implantation process is completed, another annealing process is required. Using its high temperature of 1000 to 1050, the implanted | shed ions are formed by diffusion to form the desired Concentration profile | (profile), while repairing the silicon substrate damaged in the ion implantation process | 2 | surface lattice structure.丨
p ^432638 ___ I .- | | — _>_一 · _ — · ~··» — - . —* — '· I五、發明說明(4) ί 如圖四所示,接著進行一乾蝕刻’去除閘極2 2頂部以 i及矽基底1 2表面未被侧壁子1 9覆蓋的襯氧化層1 6。接下 I來,進行一自行對準金屬矽化物(self-aligned 丨si 1 icide,簡稱sal ί cide:)製程,先於半導體晶片10表面 I形成一金屬層(未顯示),並覆蓋於閘極2 2表面。隨後進行 丨一熱處理製程,使金屬層與源極與汲極2 4以及閘極2 2頂部 |表面反應形成一金屬矽化物層2 6。然後利用一濕蝕刻製程 |去除未反應成矽化物之金屬層’完成PMOS電晶體30的製 作。 在P雞子佈植製程中,襯氧化層16可以防止佈植離子 發生隧穿(channel)效應或破壞碎基底12表面的晶格結 構。然而襯氧化層1 6亦會造成較大的劑量.損失,使HDD 23 中的硼離子濃度的控制較為不易。而為了克服襯氧化層16 |所造成的能量損失,就必須使用能量較高的棚離子進行P_ |離子佈植。以較高能量的離子進行佈植’將會造成較深的 界面深度(junction depth)以及氧強化擴散(〇ED)現象’ 並且容易產生短通道效應(short channel effect)’降低 I PMOS電晶體30的電性表現。此外’硼原子向襯氧作層1 6外 I擴散的趨勢,亦造成HDD 23中的硼原子濃度下降β ’ | I. 發明概述p ^ 432638 ___ I .- | | — _ > _ 一 · _ — · ~ ·· »—-. — * — '· V. Description of the invention (4) ί As shown in Figure 4, followed by a dry etching' The oxide layer 16 is removed from the top of the gate electrode 2 2 with i and the surface of the silicon substrate 12 not covered by the side wall member 19. Following I, a self-aligned metal silicide (sal ide :) process is performed. A metal layer (not shown) is formed before the surface I of the semiconductor wafer 10, and the gate is covered. Pole 2 2 surface. Subsequently, a heat treatment process is performed to make the metal layer react with the source and drain electrodes 24 and the top of the gate electrode 2 2 to form a metal silicide layer 26. Then, a wet etching process is used to remove the unreacted silicide metal layer 'to complete the fabrication of the PMOS transistor 30. In the P-chicken-planting process, the lining oxide layer 16 can prevent the channeling effect of the implanted ions or damage the lattice structure on the surface of the broken substrate 12. However, the lining oxide layer 16 will also cause a large dose loss, which makes it difficult to control the boron ion concentration in HDD 23. In order to overcome the energy loss caused by the lining oxide layer 16 |, it is necessary to use a higher energy shed ion for P_ | ion implantation. Implanting with higher energy ions' will cause deeper junction depth and oxygen-enhanced diffusion (OED) phenomena 'and will easily produce short channel effects' reducing I PMOS transistors 30 Electrical performance. In addition, the tendency of ’boron atoms to diffuse to the outside of the oxygen-lining layer 16 outside I also causes the concentration of boron atoms in HDD 23 to decrease β ′ | I. Summary of the Invention
I 本發明之主要目的在於提供一種於一半導體晶片表面I The main object of the present invention is to provide a semiconductor wafer surface
第7頁 * Βί/i ^ o c ^ 〇 __ ______, ^ I r - _. _ — · . —-· , ~·· ' — — — · ........ 丨五、發明說明¢5) ! i製作一 MOS電晶體的方法,以解決上述之問題。 —Page 7 * Βί / i ^ oc ^ 〇__ ______, ^ I r-_. _ — ·. — — ·, ~ ·· '— — — · ........ 丨 V. Description of the invention ¢ 5)! I Method of making a MOS transistor to solve the above problems. —
I 該半導體晶片包含有一矽基底。本發明之製作方法先 於該矽基底表面之一預定區域形成一閘極。接著進行一第 一離子佈植製程,於該閘極兩側之矽基底上各形成一摻雜 區,用來做為該M0S電晶體之重摻雜汲極(HDD)。於該半導 體晶片表面形成一厚度均勻且不含氧的介電層,覆蓋於該 矽基底以及該閘極的表面。再於該閘極兩側周圍之介電層 表面各形成一側壁子。最後進行一第二離子佈植製程,於 該閘極兩側之側壁子外緣的矽基底上分別形成一源極以及 汲極,完成該M0S電晶體的製程。I The semiconductor chip includes a silicon substrate. The manufacturing method of the present invention first forms a gate electrode on a predetermined region of the surface of the silicon substrate. Then, a first ion implantation process is performed, and a doped region is formed on the silicon substrate on both sides of the gate, which is used as a heavily doped drain (HDD) of the MOS transistor. A dielectric layer with a uniform thickness and no oxygen is formed on the surface of the semiconductor wafer, covering the surface of the silicon substrate and the gate. A sidewall is formed on the surface of the dielectric layer on both sides of the gate. Finally, a second ion implantation process is performed, and a source electrode and a drain electrode are respectively formed on the silicon substrate on the outer edges of the sidewalls on both sides of the gate electrode to complete the process of the MOS transistor.
I ! 由於本發明之方法形成HDD時,佈植的離子不需經過I! When the HDD is formed by the method of the present invention, the implanted ions do not need to pass through
I |襯氧化層,因此可以使用較小能量的離子進行離子佈植, 丨並形成較淺的介面深度,同時也解決了習知方法中所產生 I ' 丨的劑量損失問題。其次,利用一不含氧的介電層覆蓋於矽 I I基底以及閘極的表面,可避免使用植入離子所造成的氧強i 丨化擴散(0ED)現象。此外,介電層亦可以避免因植入的硼 i離子外擴散所產生的HDD植入離子濃度下降問題,、使HDD中I | lined with an oxide layer, so ions with lower energy can be used for ion implantation, and a shallower interface depth can be formed. At the same time, the problem of I '丨 dose loss caused by the conventional method is also solved. Secondly, using a dielectric layer containing no oxygen to cover the surface of the silicon substrate and the gate can avoid the phenomenon of strong oxygen diffusion (0ED) caused by implanted ions. In addition, the dielectric layer can also avoid the problem of HDD implantation ion concentration reduction caused by the external diffusion of implanted boron ions,
I 丨的離子濃度更加精確與穩定地控制。 i i | 發明之詳細說明The ion concentration of I 丨 is controlled more accurately and stably. i i | Detailed description of the invention
I ! j ί 請參閱圖五至圖八,圖五至圖八為本發明於一半導體I! J ί Please refer to FIG. 5 to FIG. 8, and FIG. 5 to FIG.
第8頁 14326 3 8 C - . . _— >.— ».—. , —一----—-----,------------—-------------------------------------------- . ________*----—------- I五、發明說明(6) 晶片40表面製作一 MOS電晶體60的方法示意圖。在本實施 例中’ MOS電晶體60為一 P型MOS電晶體。如圖五所示,半 導體晶片40包含有一矽基底42、一由兩個淺溝4 4所隔離之 N型井4卜本發明方法是先於N型井41表面之一預定區域形 成一閘極52。閘極52包含有一由二氧化矽(SiO 2)所構成之 閘極絕緣層5 0設於矽基底4 2表面之N型井41之上,用來做 為M0S電晶體60的閘極氧化層,以及一已摻雜多晶矽層51 設於閘極絕緣層50之上,用來作為M0S電晶體的閘極導電 層。接著進行一硼離子佈植製程,於閘極5 2兩侧之矽基底 42上各形成一 M0S電晶體60的重摻雜汲極(HDD)53。 如圖六所示’接下來於半導體晶片40表面均勻地形成 —厚度均勻的氮矽(SiN)層46,覆蓋於矽基底42以及閘極 !: 5 2的表面"氮矽層46的厚度係介於4 0〜10,〇 &的範圍之 | 間。接著於氮石夕層4 6表面均勻地形成一梦氧層48。 |Page 8 14326 3 8 C-.. _— > .— ».—., ——----------------, ----------------- -----------------------------------------. ________ * --------- ------ I. V. Description of the invention (6) A method of manufacturing a MOS transistor 60 on the surface of the wafer 40. In this embodiment, the 'MOS transistor 60 is a P-type MOS transistor. As shown in FIG. 5, the semiconductor wafer 40 includes a silicon substrate 42 and an N-type well 4 isolated by two shallow trenches 44. The method of the present invention is to form a gate electrode in a predetermined area on the surface of the N-type well 41 52. The gate 52 includes a gate insulating layer 50 composed of silicon dioxide (SiO 2), which is disposed on the N-type well 41 on the surface of the silicon substrate 4 2 and is used as a gate oxide layer of the M0S transistor 60. And a doped polycrystalline silicon layer 51 is disposed on the gate insulating layer 50 and is used as a gate conductive layer of the MOS transistor. Next, a boron ion implantation process is performed, and a heavily doped drain (HDD) 53 of a MOS transistor 60 is formed on the silicon substrate 42 on both sides of the gate 5 2. As shown in FIG. 6 ', the surface of the semiconductor wafer 40 is then uniformly formed—a silicon nitride (SiN) layer 46 having a uniform thickness, covering the silicon substrate 42 and the gate electrode! : 5 The thickness of the surface " nitrogen silicon layer 46 is in the range of 40 ~ 10, 〇 &. Then, a dream oxygen layer 48 is formed uniformly on the surface of the azite layer 46. |
I 如圖七所示,接著利用一非等向性乾蝕刻 | (anisotropic dry etching)製程,均勻向下去除矽氧層 | 4 8以及览矽層4 6直至矽基底4 2表面’並使殘留於閘極5 2兩 垂直側壁周圍的矽氧層4 8以及氮矽層4 6形成側壁子4 9 »然 後進行一 P離子佈植製程’於閘極5 2兩側之側壁子4 9外緣 的矽基底4 2上分別形成一源極以及汲極5 4。p雠子佈植製 程中所用的摻質為硼原子或氟化硼(BF 2+)離子,所使用的 離子植入能量約為1至1 〇 Kev ’劑量約為ΐχ 1 〇 I隻1 〇 15I As shown in FIG. 7, an anisotropic dry etching (anisotropic dry etching) process is used to uniformly remove the silicon oxide layer | 4 8 and the silicon layer 4 6 up to the surface of the silicon substrate 4 2 and leave the residue. The silicon oxide layer 4 8 and the nitrogen silicon layer 4 6 around the two vertical sidewalls of the gate 5 2 form a sidewall 4 9 »Then a P ion implantation process is performed on the outer edges of the sidewalls 4 9 on both sides of the gate 5 2 A source electrode and a drain electrode 5 4 are formed on the silicon substrate 4 2. The dopants used in the process of p. chinensis cloth implantation are boron atoms or boron fluoride (BF 2+) ions, and the ion implantation energy used is about 1 to 10 keev 'The dose is about ΐχ 1 〇I only 1 〇 15
第9頁 Μ 32638 五、發明說明(7) a t oms/cm 法右 〇 在完成P雔子佈植製程之後,需再進行一回火 (annealing)製程,利用1〇〇〇至105 0°C的高溫,使植入的 硼離子藉由擴散產生趨入(driving in),形成所要之濃度 分佈’同時修補在離子佈植製程中受損之石夕基底42表面的 晶格結構。 如圖八所示,接下來進行一自行對準金屬矽化物 (sa 1 i c i de )製程,以降低M0S電晶趙6 0之閘極5 2以及没極 與源極54表面接觸電阻。先於半導體晶片40表面形成_鶴 (tungsten, W)金屬層(未顯示),並覆蓋於閘極52以及汲^ 極與源極5 4的表面。隨後進行一熱處理製.程,使鴿金屬層 | 與源極與汲極54以及閘極52頂部表面反應形成一金屬ί夕化 鎢(tungsten s i 1 i c i de,WSi χ)層56 ’最後利用一濕蝕刻 |製程去除未反應成矽化物之鎢金屬層。其中金屬矽化鎮層 丨5 6亦可由石夕化始((:〇53115丨11(:1(16,€〇$12)或碎化鈦 | | (tit an ium si licide,TiSi2)或錮(Molybdenum silicide, MoSi 2)金屬所取代。 \Page 9 M 32638 V. Description of the invention (7) at oms / cm method right 〇 After completing the P. zizi planting process, an annealing process is needed, using 1000 to 1050 ° C The high temperature causes the implanted boron ions to drive in by diffusion to form the desired concentration distribution. At the same time, it repairs the lattice structure on the surface of Shi Xi substrate 42 damaged during the ion implantation process. As shown in FIG. 8, a self-aligned metal silicide (sa 1 i c i de) process is performed next to reduce the gate electrode 5 2 of the M0S transistor Zhao 60 and the surface contact resistance between the non-electrode and the source 54. A tungsten (W) metal layer (not shown) is formed before the surface of the semiconductor wafer 40 and covers the surfaces of the gate electrode 52 and the drain and source electrodes 54. Subsequently, a heat treatment process is performed to make the pigeon metal layer | react with the source and drain 54 and the top surfaces of the gate 52 to form a metal tungsten si 1 ici de (WSi χ) layer 56 'Finally, a Wet etching | The process removes the tungsten metal layer that has not reacted into silicide. Among them, the metal silicified layer 丨 5 6 can also be started by Shi Xihua ((: 〇53115 丨 11 (: 1 (16, € ¥ 12)) or broken titanium | | (tit an ium si licide, TiSi2) or 锢 (Molybdenum silicide, MoSi 2) metal.
.I 本發明之方法是先進行硼離子佈植,以於閘極5 2兩側 +丨 之矽基底42上各形成重摻雜汲極(HDD) 53,接著於半導體 晶片40表面形成厚度約60A之氮矽層46,再於閘極52兩側 周圍之氮矽層46表面各形成側壁子49,最後再進行P離子.I The method of the present invention is to first perform boron ion implantation to form a heavily doped drain (HDD) 53 on the silicon substrate 42 on both sides of the gate 5 2 +, and then form a thickness of about 500 Å on the surface of the semiconductor wafer 40. Nitrogen silicon layer 46 of 60A, and sidewalls 49 are formed on the surface of the nitrogen silicon layer 46 around the sides of the gate 52, and finally P ion is performed.
第10頁Page 10
f M3263 Q 丨. _____...._—_______________.....—――—〜 I五、發明說明(8) - Ιϊϊΐΐ二於閑極52兩側之側壁子49外緣的碎基底42上 ! y “、 以及歧極54。由於氮石夕層4 6為一不含氧之介 ^ ^因此可以避免習知方法中所產生的氧強化擴散 丨 ^*象。此外,由於HDD 53中硼離子不易擴散進入氮 結果’亦避免了習知方法中所產生的:離子外擴 相較於習知製作pM〇S電晶體的方法,本 JHDD 53’因此可用較小能量的離子進行佈植月 ^的^面深度。同時’由於形成HDD 53時佈植離子不需崾 ^氧化屠,因此沒㈣4損失_。其次,_氮= ,蓋於梦基底42以及閘極52的表面可以避免植入離子所 f的氡強化擴散(OED)現象以及硼離子的外擴散問題, 依iDD 5 3中的離子濃度能更加精確與穩定地被控制。因此 本發明方法所形成的M〇s電晶體6〇具有較佳的電性表 0 | 以上所述僅為本發明之較佳實施例,凡 本發 寻利SS湛1 & ’ T ”月 祀圍所做之均等變化與修飾,皆應屬本發明專利 丨盍範圍。 、〜峨f M3263 Q 丨. _____...._________________.....———————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————— V. INTRODUCTION (8) Up! Y ", and the disparity 54. Since the nitrogen stone layer 46 is an oxygen-free medium ^ ^, the oxygen-enhanced diffusion generated in the conventional method can be avoided. In addition, due to the HDD 53 Boron ions are not easy to diffuse into nitrogen. As a result, the conventional method is also avoided: compared with the conventional method for making pMOS transistors, the JHDD 53 'can be implanted with ions of lower energy. At the same time, the surface depth of the surface is also reduced. Because the implanted ions do not need to be oxidized when forming the HDD 53, there is no loss of _. Second, _ nitrogen =, covering the surface of the dream substrate 42 and the gate 52 can avoid planting. The ion-enhanced diffusion (OED) phenomenon of the ion and the external diffusion of boron ions can be controlled more accurately and stably according to the ion concentration in iDD 53. Therefore, the Mos transistor 6 formed by the method of the present invention 6 〇 Has a better electrical meter 0 | The above is only a preferred embodiment of the present invention, where Lee SS seeking Zhan 1 & 'T "Si month around the modifications and alterations do, also belong to the scope of the present invention Shuhe Pat. , ~ E
F4 32 6 3 8, I —.— *—一 ,·—_ — —〜·—.——“ — —* ——— * -—――·— * — —** *—·"— ——— ——·—· — · -_. . . ~* · 丨圖式簡單說明 I圖示之簡單說明 j 圖一至圖四為習知於一半導體晶片表面製作一 PMOS電 晶體的方法示意圖。 圖五至圖八為本發明於一半導體晶片表面製作一 MOS 電晶體的方法示意圖。 圖示之符號說明 i 10 半導體晶片 11 N型井 12 矽基底 14 淺溝 16 襯氧化層 18 氮矽層 19 侧壁子 20 介電層 21 摻雜多晶矽層 22 閘極. 23 HDD 24 源極與汲極 26 金屬矽物化層 30 PMOS電晶體 40 半導體晶片 41 N型井 42 石夕基底 44 淺溝 46 氮矽層 48 矽氧層 49 側壁子 50 閘極絕緣層 51 已摻雜多晶矽層 52 閘極 53 HDD 54 源極與汲極 56 金屬矽化鎢層 60 MOS電晶體F4 32 6 3 8, I —. — * — 一, · —_ — — ~ · —.—— “— — * ——— * -——— · — * — — ** * — · " — ——— —— · — · — · -_... ~ * · 丨 Simple illustration of the diagram I Brief description of the diagram j Figures 1 to 4 are schematic diagrams of a method for making a PMOS transistor on the surface of a semiconductor wafer. Figures 5 to 8 are schematic diagrams of a method for fabricating a MOS transistor on the surface of a semiconductor wafer according to the present invention. The symbols in the figure illustrate i 10 semiconductor wafer 11 N-type well 12 silicon substrate 14 shallow trench 16 lined with oxide layer 18 nitrogen silicon layer 19 Side wall 20 Dielectric layer 21 Doped polycrystalline silicon layer 22 Gate. 23 HDD 24 Source and drain 26 Metal silicon layer 30 PMOS transistor 40 Semiconductor wafer 41 N-well 42 Shi Xi substrate 44 Shallow trench 46 Nitrogen Silicon layer 48 Silicon oxide layer 49 Side wall 50 Gate insulating layer 51 Doped polycrystalline silicon layer 52 Gate 53 HDD 54 Source and drain 56 Metal tungsten silicide layer 60 MOS transistor
第12頁Page 12
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