TW432638B - Manufacturing method for MOS transistor - Google Patents

Abstract

The present invention provides a manufacturing method for MOS transistor on a semiconductor chip surface. The semiconductor chip comprises a silicon substrate. The inventive manufacturing method is firstly forming a gate in a predetermined region on the silicon substrate surface; next, conducting an ion implantation; forming a doped region respectively on the silicon substrate at both sides of the gate which is used as heavily doped drain (HDD) of the MOS transistor; and, forming a uniform-thickness dielectric containing no oxygen on the semiconductor chip surface to cover the silicon substrate and the gate surface; forming spacers on the dielectric surface around both sides of the gate; finally, conducting an ion implantation and forming a source and a drain respectively on the silicon substrate at the outer edge of the spacer on both sides of the gate to complete the process of the MOS transistor.

Description

^ 4 32 6 3 8 V. Description of the invention (1) 丨 Field of invention-The present invention provides a method for manufacturing a metal oxide semiconductor (MOS) transistor, especially a method for manufacturing a P-type metal oxide semiconductor Transistor (PM0S) method. Background note | With the increase of semiconductor accumulation, complementary metal-oxide-semi conduct or (CMOS) transistors with the advantage of low energy consumption have gradually replaced I-type N-type metal oxide semiconductors (NMOS) status. CMOS transistor is another basic I composed of two complementary PM0S transistors and NM0S transistors. I: electronic components. The P Μ 0 S transistor mainly includes a gate. The semiconducting body is P-type source and drain and source and drain; and the source and non-polarity Opposite wheaton substrate. !]

I |. The conventional method for making pM〇S transistor is to use boron atom as dopant! (d 〇 p a η 1 :) Heavily doped drain '(HDD) is doped with I i and source and non-electrode. Due to the small volume of the boron atom, an out diffusion phenomenon is prone to occur. When the line width of semiconductor process I is less than 0.1 8 microns or even less than 0.1 5 microns, the external diffusion of boron atoms will seriously affect the electrical properties of the PMOS transistor. In addition, the conventional method for making a PM0S transistor uses a silicon dioxide layer as a spacer shape.

Page 4 -432638 I 1 1 ** ~ ·-— — · _ · One ~~ _ ·-——. —-__

I. 5. Description of the invention (2) The "contact stop layer" at the time of II will produce an oxygen-enhanced diffusion i | (oxide-enhanced di f fusion, OED) phenomenon in the ion implantation process, and the dioxide layer | It will further accelerate the external diffusion of deleted ions, making the boron ions in the HDD | 丨 decrease. Therefore, it is necessary to improve the conventional process to improve the quality of products. '^,! j Refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of a method for manufacturing a PMOS (P-type metal-oxide-semiconductor) transistor 30 on the surface of a semiconductor I wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12, and an N-type well (N we U) 11 separated by two shallow trenches 14 is provided on the surface of the silicon substrate 12. A gate 22 is provided on the surface of the N-type well 11. The gate electrode 22 includes a dielectric layer 20 made of silicon dioxide (SiO 2), which is disposed on the N-type well 11 and serves as a gate oxide layer of the PM0S transistor 30. ), And a doped polycrystalline silicon layer 21 is provided on the surface of the dielectric layer 20 and serves as a gate electrode of the PM0S transistor 30 »! As shown in Figure 2, the conventional method is prior to the semiconductor The surface of the wafer 10 is uniformly formed with a 1 iner oxide layer i 1 6 ′ composed of silicon dioxide and covers the surface of the gate electrode 2 2. Next, a lightly doped (p-) ion implantation process is performed to form a heavily doped drain (HDD) 23 of a PM0S transistor j 3 0 on the surface of the silicon substrate 12 on both sides of the free electrode 22. The dose of boron ions used in the P ion implantation process is about 1 × 10! 5 × 10 is atoms / cm2, and the energy is about ι0 to 15 Kev. Next in the lining oxide layer 16

Page 5 _________________________ _______ V. Description of the Invention (3) A silicon nitride layer 18 is uniformly formed on the surface. -The main purpose of forming the liner oxide layer 16 is to serve as an etch stop layer and a thermal stress buffer layer (buf f er 1 ayer) for the silicon nitride layer when the nitrided sidewalls are subsequently formed. However, 'due to the tendency of the boron atoms to diffuse to the oxygen-lined f-layer 16, the concentration of boron atoms in HDD 23 is not easy to control. In addition, the oxide-lined layer 16 will also cause a dose " damage during the implantation of P heterozygotes. The problem of loss loss and the phenomenon of oxygen-enhanced diffusion (〇ED). Oxygen strength | 'small j' of the oxygen atom | As shown in Figure 3, another etching back process is performed, | | The nitrogen silicon layer 1 8 is removed down to the surface of the oxide layer 16 and left behind At the gate | | the nitrogen silicon layer 18 on the surface of the lining oxide layer 16 on both sides of the pole 2 2 is shaped into two side walls 19 (spacer) 19. Then perform a heavier doped (p +) ion implantation process.

The source and the drain of the pMOS transistor 30 are formed on the silicon substrate 12 on both sides of the gate 22 || 24. The dopant used in the P ion implantation process is boron atom or boron fluoride I | (boron fluoride ion (BFZ +) ion), and its implantation energy is about 1 () | 丨 Kev 'dosage is between 2x iQi6at. ms / cm ^. After the P ion implantation process is completed, another annealing process is required. Using its high temperature of 1000 to 1050, the implanted | shed ions are formed by diffusion to form the desired Concentration profile | (profile), while repairing the silicon substrate damaged in the ion implantation process | 2 | surface lattice structure.丨

p ^ 432638 ___ I .- | | — _ > _ 一 · _ — · ~ ·· »—-. — * — '· V. Description of the invention (4) ί As shown in Figure 4, followed by a dry etching' The oxide layer 16 is removed from the top of the gate electrode 2 2 with i and the surface of the silicon substrate 12 not covered by the side wall member 19. Following I, a self-aligned metal silicide (sal ide :) process is performed. A metal layer (not shown) is formed before the surface I of the semiconductor wafer 10, and the gate is covered. Pole 2 2 surface. Subsequently, a heat treatment process is performed to make the metal layer react with the source and drain electrodes 24 and the top of the gate electrode 2 2 to form a metal silicide layer 26. Then, a wet etching process is used to remove the unreacted silicide metal layer 'to complete the fabrication of the PMOS transistor 30. In the P-chicken-planting process, the lining oxide layer 16 can prevent the channeling effect of the implanted ions or damage the lattice structure on the surface of the broken substrate 12. However, the lining oxide layer 16 will also cause a large dose loss, which makes it difficult to control the boron ion concentration in HDD 23. In order to overcome the energy loss caused by the lining oxide layer 16 |, it is necessary to use a higher energy shed ion for P_ | ion implantation. Implanting with higher energy ions' will cause deeper junction depth and oxygen-enhanced diffusion (OED) phenomena 'and will easily produce short channel effects' reducing I PMOS transistors 30 Electrical performance. In addition, the tendency of ’boron atoms to diffuse to the outside of the oxygen-lining layer 16 outside I also causes the concentration of boron atoms in HDD 23 to decrease β ′ | I. Summary of the Invention

I The main object of the present invention is to provide a semiconductor wafer surface

Page 7 * Βί / i ^ oc ^ 〇__ ______, ^ I r-_. _ — ·. — — ·, ~ ·· '— — — · ........ 丨 V. Description of the invention ¢ 5)! I Method of making a MOS transistor to solve the above problems. —

I The semiconductor chip includes a silicon substrate. The manufacturing method of the present invention first forms a gate electrode on a predetermined region of the surface of the silicon substrate. Then, a first ion implantation process is performed, and a doped region is formed on the silicon substrate on both sides of the gate, which is used as a heavily doped drain (HDD) of the MOS transistor. A dielectric layer with a uniform thickness and no oxygen is formed on the surface of the semiconductor wafer, covering the surface of the silicon substrate and the gate. A sidewall is formed on the surface of the dielectric layer on both sides of the gate. Finally, a second ion implantation process is performed, and a source electrode and a drain electrode are respectively formed on the silicon substrate on the outer edges of the sidewalls on both sides of the gate electrode to complete the process of the MOS transistor.

I! When the HDD is formed by the method of the present invention, the implanted ions do not need to pass through

I | lined with an oxide layer, so ions with lower energy can be used for ion implantation, and a shallower interface depth can be formed. At the same time, the problem of I '丨 dose loss caused by the conventional method is also solved. Secondly, using a dielectric layer containing no oxygen to cover the surface of the silicon substrate and the gate can avoid the phenomenon of strong oxygen diffusion (0ED) caused by implanted ions. In addition, the dielectric layer can also avoid the problem of HDD implantation ion concentration reduction caused by the external diffusion of implanted boron ions,

The ion concentration of I 丨 is controlled more accurately and stably. i i | Detailed description of the invention

I! J ί Please refer to FIG. 5 to FIG. 8, and FIG. 5 to FIG.

Page 8 14326 3 8 C-.. _— > .— ».—., ——----------------, ----------------- -----------------------------------------. ________ * --------- ------ I. V. Description of the invention (6) A method of manufacturing a MOS transistor 60 on the surface of the wafer 40. In this embodiment, the 'MOS transistor 60 is a P-type MOS transistor. As shown in FIG. 5, the semiconductor wafer 40 includes a silicon substrate 42 and an N-type well 4 isolated by two shallow trenches 44. The method of the present invention is to form a gate electrode in a predetermined area on the surface of the N-type well 41 52. The gate 52 includes a gate insulating layer 50 composed of silicon dioxide (SiO 2), which is disposed on the N-type well 41 on the surface of the silicon substrate 4 2 and is used as a gate oxide layer of the M0S transistor 60. And a doped polycrystalline silicon layer 51 is disposed on the gate insulating layer 50 and is used as a gate conductive layer of the MOS transistor. Next, a boron ion implantation process is performed, and a heavily doped drain (HDD) 53 of a MOS transistor 60 is formed on the silicon substrate 42 on both sides of the gate 5 2. As shown in FIG. 6 ', the surface of the semiconductor wafer 40 is then uniformly formed—a silicon nitride (SiN) layer 46 having a uniform thickness, covering the silicon substrate 42 and the gate electrode! : 5 The thickness of the surface " nitrogen silicon layer 46 is in the range of 40 ~ 10, 〇 &. Then, a dream oxygen layer 48 is formed uniformly on the surface of the azite layer 46. |

I As shown in FIG. 7, an anisotropic dry etching (anisotropic dry etching) process is used to uniformly remove the silicon oxide layer | 4 8 and the silicon layer 4 6 up to the surface of the silicon substrate 4 2 and leave the residue. The silicon oxide layer 4 8 and the nitrogen silicon layer 4 6 around the two vertical sidewalls of the gate 5 2 form a sidewall 4 9 »Then a P ion implantation process is performed on the outer edges of the sidewalls 4 9 on both sides of the gate 5 2 A source electrode and a drain electrode 5 4 are formed on the silicon substrate 4 2. The dopants used in the process of p. chinensis cloth implantation are boron atoms or boron fluoride (BF 2+) ions, and the ion implantation energy used is about 1 to 10 keev 'The dose is about ΐχ 1 〇I only 1 〇 15

Page 9 M 32638 V. Description of the invention (7) at oms / cm method right 〇 After completing the P. zizi planting process, an annealing process is needed, using 1000 to 1050 ° C The high temperature causes the implanted boron ions to drive in by diffusion to form the desired concentration distribution. At the same time, it repairs the lattice structure on the surface of Shi Xi substrate 42 damaged during the ion implantation process. As shown in FIG. 8, a self-aligned metal silicide (sa 1 i c i de) process is performed next to reduce the gate electrode 5 2 of the M0S transistor Zhao 60 and the surface contact resistance between the non-electrode and the source 54. A tungsten (W) metal layer (not shown) is formed before the surface of the semiconductor wafer 40 and covers the surfaces of the gate electrode 52 and the drain and source electrodes 54. Subsequently, a heat treatment process is performed to make the pigeon metal layer | react with the source and drain 54 and the top surfaces of the gate 52 to form a metal tungsten si 1 ici de (WSi χ) layer 56 'Finally, a Wet etching | The process removes the tungsten metal layer that has not reacted into silicide. Among them, the metal silicified layer 丨 5 6 can also be started by Shi Xihua ((: 〇53115 丨 11 (: 1 (16, € ￥ 12)) or broken titanium | | (tit an ium si licide, TiSi2) or 锢 (Molybdenum silicide, MoSi 2) metal.

.I The method of the present invention is to first perform boron ion implantation to form a heavily doped drain (HDD) 53 on the silicon substrate 42 on both sides of the gate 5 2 +, and then form a thickness of about 500 Å on the surface of the semiconductor wafer 40. Nitrogen silicon layer 46 of 60A, and sidewalls 49 are formed on the surface of the nitrogen silicon layer 46 around the sides of the gate 52, and finally P ion is performed.

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f M3263 Q 丨. _____...._________________.....———————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————— V. INTRODUCTION (8) Up! Y ", and the disparity 54. Since the nitrogen stone layer 46 is an oxygen-free medium ^ ^, the oxygen-enhanced diffusion generated in the conventional method can be avoided. In addition, due to the HDD 53 Boron ions are not easy to diffuse into nitrogen. As a result, the conventional method is also avoided: compared with the conventional method for making pMOS transistors, the JHDD 53 'can be implanted with ions of lower energy. At the same time, the surface depth of the surface is also reduced. Because the implanted ions do not need to be oxidized when forming the HDD 53, there is no loss of _. Second, _ nitrogen =, covering the surface of the dream substrate 42 and the gate 52 can avoid planting. The ion-enhanced diffusion (OED) phenomenon of the ion and the external diffusion of boron ions can be controlled more accurately and stably according to the ion concentration in iDD 53. Therefore, the Mos transistor 6 formed by the method of the present invention 6 〇 Has a better electrical meter 0 | The above is only a preferred embodiment of the present invention, where Lee SS seeking Zhan 1 & 'T "Si month around the modifications and alterations do, also belong to the scope of the present invention Shuhe Pat. , ~ E

F4 32 6 3 8, I —. — * — 一, · —_ — — ~ · —.—— “— — * ——— * -——— · — * — — ** * — · " — ——— —— · — · — · -_... ~ * · 丨 Simple illustration of the diagram I Brief description of the diagram j Figures 1 to 4 are schematic diagrams of a method for making a PMOS transistor on the surface of a semiconductor wafer. Figures 5 to 8 are schematic diagrams of a method for fabricating a MOS transistor on the surface of a semiconductor wafer according to the present invention. The symbols in the figure illustrate i 10 semiconductor wafer 11 N-type well 12 silicon substrate 14 shallow trench 16 lined with oxide layer 18 nitrogen silicon layer 19 Side wall 20 Dielectric layer 21 Doped polycrystalline silicon layer 22 Gate. 23 HDD 24 Source and drain 26 Metal silicon layer 30 PMOS transistor 40 Semiconductor wafer 41 N-well 42 Shi Xi substrate 44 Shallow trench 46 Nitrogen Silicon layer 48 Silicon oxide layer 49 Side wall 50 Gate insulating layer 51 Doped polycrystalline silicon layer 52 Gate 53 HDD 54 Source and drain 56 Metal tungsten silicide layer 60 MOS transistor

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Claims (1)

酽 4 326 3 8 —. · ~ — ---------------------------------------— .—— ————————————————————————————————————————————————————————————————————————————————————————————————————————————————————— I. Application for Patent | A transistor method, the semiconductor wafer surface includes a silicon substrate, the manufacturing method includes the following steps: forming a gate on a predetermined area of the surface of the silicon substrate; 丨 performing a first Ion implantation process, forming a doped region on the silicon substrate on both sides of the gate 1 for the heavily doped drain (HDD) of the MOS transistor; j forming a uniform thickness and oxygen-free dielectric | layer on the surface of the semiconductor semiconductor chip, covering the silicon substrate and the surface of the gate; I forming one on each surface of the dielectric layer on both sides of the gate; Side wall | (spacer); and | A second ion implantation process is performed on the gate. A source (sour) and a drain are formed on the stone bases on the outer edges of the two sides of the side walls. Udrain) The complete M0S transistor manufacturing process. I 2. The method according to item 1 of the patent application scope, wherein the gate electrode comprises a gate insulating layer provided on the surface of the silicon substrate, and a gate conductive layer I provided on the gate insulating layer. on. ', I ί 3. The method according to the second item of the patent application, wherein the gate insulating layer is composed of silicon dioxide (SiO 2), and is used as the gate oxide layer of the MOS transistor. (Gate oxide). Page 13 9 Δ f;? Q_ VI. Patent application scope 4. The method of the second patent application scope, wherein the gate conductive layer is composed of doped poly-silicon. 5. The method according to item 1 of the patent application, wherein the dielectric layer is composed of silicon nitride (SiN), and its thickness ranges from 40 to 100 angstroms (angstrom, A). The method of item 1 of the patent, wherein the sidewalls are composed of silicon oxide, and the manufacturing method includes the following steps: uniformly forming a silicon oxide layer on the surface of the dielectric layer; and performing a silicon oxide layer; An isotropic dry etching process is used to uniformly remove the silicon oxide layer downward, and the silicon oxide layer located around the vertical sidewall of the gate electrode forms the sidewall. 7. If the method of claim 6 is applied, the anisotropic dry etching process will also etch the dielectric layer under the silicon oxide layer up to the surface of the silicon substrate. 8. The method according to item 1 of the scope of patent application, wherein the dopant used in the first ion implantation process is boron (B) ions. 9. If the method of applying for the item 1 of the patent scope further includes a self-alignment silicide (salicide) process, Page 14 M 3 2 6 3 Bt. The scope of the patent application is implemented after the second ion cloth is implanted, and is used to form a metal lithoxide (si) on the surface of the gate, source and light electrode of the MOS transistor (si 1 pesticide) layer to reduce the contact resistance of each surface. 10. The method according to item 9 of the scope of patent application, wherein the metal silicide layer is composed of tungsten silicide (WSix), TiSi2, MoSi2, or CoSi2. 11. A method for fabricating a P-type metal oxide semiconductor (PM0S) transistor on the surface of a silicon substrate of a semiconductor wafer. The surface of the silicon substrate includes an N-type well (N-we 1 1). The manufacturing method includes the following steps: Forming a gate at a predetermined area on the surface of the N-type well; performing a boron (B) ion implantation process, forming a doped region on the silicon substrate on both sides of the gate, for the purpose of The heavily doped drain (HDD) of the PM0S transistor; a silicon nitride (SiN) layer with a uniform thickness is formed on the surface of the semiconductor wafer, covering the silicon substrate and the surface of the gate; A sidewall is formed on each surface of the nitrogen silicon layer; and a second ion implantation process is performed to form a source and a drain on the silicon substrate on the outer edges of the sidewalls on both sides of the gate, respectively, to complete the PM0S transistor. Process. 12. For the method according to item 11 of the patent application, wherein the gate system includes Page 15 r 霡 4 32a 3 q VI. Scope of patent application A silicon dioxide (Si02) layer is provided on the N-type well, which is used as the gate oxide layer of the PMOS transistor, and a doped polycrystalline silicon layer is provided. On top of the silicon dioxide layer, it is used as a gate conductive layer of the PMOS transistor. 13. The method according to item 11 of the patent application range, wherein the thickness of the silicon nitride layer is in a range of 40 to 100 angstroms (A). 14. The method according to item 11 of the patent application, wherein the side wall is composed of a silicon oxide compound, and the manufacturing method includes the following steps: uniformly forming a silicon oxide layer on the surface of the nitrogen silicon layer; and performing a silicon oxide layer; An anisotropic dry etching process is used to uniformly remove the silicon oxide layer downward, and the silicon oxide layer located around the vertical sidewall of the gate electrode forms the sidewall. 15. If the method of the scope of patent application No. 14, wherein the anisotropic dry etching process will also etch the nitrogen silicon layer under the silicon oxide layer up to the surface of the silicon substrate. 16. The method of scope of the patent application No. 11 It also includes a self-aligned silicide process, which is implemented after the second ion cloth is implanted to form a metal silicide layer on the surface of the gate, source and drain of the PMOS transistor. To reduce the contact resistance of each surface. 17. The method according to item 16 of the scope of patent application, wherein the metal silicide layer is made of WSix, TiSi2 ,! ^ 1〇3 "or (: 〇5". Page 16