TW442919B - Method to form source/drain extension junction by using borosilicate glass in manufacturing CMOS transistor - Google Patents

Abstract

The present invention relates to a method of manufacturing CMOS transistor, which comprises the steps of: at first, providing a p-type semiconductor substrate and an n-type well region; then forming a shallow trench isolation on p-substrate and n-well region to form a plurality of active regions; forming a channel in p-substrate and n-well region; then, forming a p-type gate pattern of CMOS and an n-type gate pattern of CMOS in p-substrate and n-well region; forming the first defined photoresist layer on n-well region; then, implanting n-type dopant into the p-substrate to form a lightly doped source/drain; then, removing the first defined photoresist layer; depositing a dielectric layer on p-substrate and n-well region; forming the second defined photoresist layer on the dielectric layer; then etching part of the dielectric layer on n-well region for the first time; then forming a offset spacer on n-well region during the etching step of part of the dielectric layer; then, removing the second defined photoresist layer; depositing a borosilicate glass layer in n-well region and the dielectric layer; then etching part of the borosilicate glass layer and etching part of the dielectric layer for the second time to form the first borosilicate glass spacer and the second borosilicate glass spacer; then forming an n-type heavily doped source/drain in p-substrate; and forming a p-type heavily doped source/drain in n-well region; finally, annealing the first borosilicate glass spacer, and diffusing boron atoms in the lower region of the first borosilicate glass spacer to form a source/drain extension junction.

Description

; -4 4 429 Ί 9 ____Ca Qing 0 2 _ ___________ (V. Description of the invention (1) 5 _ 1 Field of invention: The present invention relates to a method for manufacturing complementary metal-oxide-semiconductor half field-effect CMOS) The method 'is particularly related to the manufacture of a complementary gold transistor using a cut-out glass to form a source / electrode extension interface. Background from 5-2: Recently, due to the huge Urge integration (ULS) I) The semiconductor technology is formed on the semiconductor substrate, so that the integrated circuit density on a single wafer 'results in the size of individual components' and the high-resolution lithography technology's innovation is significant. However, ‘the future needs to be higher and the demand for electronic components is a metal oxide half field effect transistor (m0sfet). Generally speaking, ′-rather thin free U- undoped polycrystalline silicon silicide (p〇lycide)

PolysUicon) materials, which are used to make gold-oxide effects, are crystalline silicidated metal or polycrystalline silicon materials, and thin-plate solar cells are used in Japan ’s Japanese electric crystal (milk half field effect) method. As a result of the increase in the density of integrated circuits, the density of component groups is increased. .Recent etching technology, and other semiconductors to achieve the reduction in component size, additional requirements on semiconductor process technology. Scale noticeable increase. This reduction, and anisotropic progress, circuit density, In order to achieve the process is the public, put (. Completed more, 4 42 9 1 9-cable number 88〗 彳 _ year month day _ correction _ V. Description of the invention (2) implanting a doped impurity material, On the gate conductor and source / drain region. If an impurity-doped material is used to form an n-type source / drain region, the resulting metal-oxide half-field effect transistor is called an n-type metal-oxide half-field effect Transistor element (η channel). In contrast, if a doped impurity material is used to form a P-type source / drain region, the resulting metal-oxide-semiconductor field-effect transistor is called a P-type metal-oxide half-field effect. Transistor element Channel). Using lithography technology (ph 0t ο 1 i 1; h 〇graphytechnique) to form the gate conductor and the adjacent source / drain region. Through a thick field oxide layer, the gate conductor and source appear in the window The electrode / drain region. The windows that form the transistor are called the active region. Therefore, the range of the active region is between the field oxide layer. Above the field oxide layer, metal interconnects are arranged. The polysilicon gate conductor and the source / drain region are connected to form a complete circuit structure. The integrated circuit uses an η channel element, a ρ channel element, or both components on a single substrate. When forming both In the case of a type element, basically the element must be implanted with different doped source / drain regions. Implanted n-type impurities in the source / drain region to form an n-channel element, and in the source / drain region Implanting a p-type impurity to form a p-channel element, the only problem is related to each element. Such an increase in density will make the problem worse. The component is found to be bad, and the process parameters and process steps can be adjusted. In most cases, the process of the η channel is different from the process of the ρ channel due to the unity of each type of component. The process of the η channel is discussed first, and then the process of the ρ channel is discussed.

Page 6 V. Explanation of the invention (3) -ES__88116902 Modification Channel elements are particularly sensitive to the so-called short channel e f f ec t. The distance between the source and non-polar regions is usually based on the actual channel length (phySicai channel length). However, after the ion implantation and diffusion processes, the distance between the source and the drain region becomes smaller than the actual channel length. This is called the effective channel length. In the ultra-large integrated circuit t 4 ', the actual channel becomes shorter, making the short channel effect a more obvious problem. In general, the short-circuit voltage of a short element ((sub-thresho1d is short, the source and drain terminals will produce a practical shortage, for the gate voltage, the gate charge 'goes to reverse the concept relative to the threshold voltage. Even When the current is present in the electrical channel effect, the current will be in the opposite channel area. There is no effect on the operation of the device with a short influence, thereby reducing the volt age) and increasing the subcritical current like the effective channel length becomes very empty. The area can extend forward to another. As a result, some channels will be partially empty.逭 As a result, the channel of the transistor requiring a lower effective channel length is reduced, and the flow rate of the critical current should also have a gate voltage lower than the critical amount. The source and drain crystals have a relatively short effective channel length. . However, the two main reasons for increasing the sub-critical current are punch through and drain-induced barrier lowering. The result of the penetration is derived from the wide drain empty region when a reverse bias is applied to the drain well diode. The drain field may run through the source

4429 1 9 --- 1S_88H6902_year, month, day, revision_ five. Description of the invention (4) Pole region ’is used to reduce the potential barrier at the interface from the source to the substrate. The through current and the substrate material are connected below the substrate surface. Compared to the through current, the drain causes the barrier to drop and causes the current to occur almost on the substrate surface. The application of a drain voltage may cause the surface potential of the substrate to drop. As a result, there is a lower potential barrier on the substrate surface, which will cause the subcritical current of the silicon-silicon dioxide surface near the channel to increase. A method for controlling the short channel effect is to increase the impurity concentration of the element substrate. Unfortunately, the addition of substrate impurities is detrimental to ensuring the component's puppet energy gradient. Increasing the potential energy gradient creates an additional effect, which is called the hot carrier effect. The phenomenon of heat carrier effect is to increase the kinetic energy of the carrier (electron or hole), accelerate through a large potential energy gradient, and then become a defect in the gate oxide layer. The maximum potential energy gradient is usually based on the maximum electric field, which occurs during near-saturation operation. In particular, the effect of the electric field is more pronounced at the lateral junction near the channel pole. Taking an n-channel element as an example, the electric field generates electron kinetic energy at the drain, causing the channel electrons to enter the gate. The kinetic energy between electrons and electrons is randomly scattered, making the electrons very "hot". These hot electrons have enough energy to generate an electron-hole pair, which will affect the ionization of silicon atoms. When the holes flow into the substrate Generate a substrate current in the element, and add the flow of channel electrons, which will affect the ionization to generate electrons. In the element, the substrate current creates the heat carrier for the first time. Take the ρ channel element as an example, except for holes and electrons. Apart from the opposite roles, the basic manufacturing process has the same essence.

442919 _ Case No. 88116902 Amendment V. Description of the invention (5) The heat carrier effect occurs when some heat carriers are injected into the gate oxide layer near the drain junction, the heat carrier will destroy the gate oxide layer and cause defects. Gate oxide. Defects in the gate oxide layer generally become electron defects, even if these electron defects are initially filled with holes. The accumulated time of the defect charge will affect the positive critical drift of the η-channel element and the ρ-channel element. To our knowledge, the mobility of hot electrons far exceeds that of thermo holes. Among the n-channel element and the p-channel element, the heat carrier effect causes a huge critical slope. Therefore, a p-channel element will experience a negative critical slope. In addition to modifying the structure of the transistor, the problems of subcritical current and critical drift will cause the short channel effect and heat carrier effect to remain intact. To overcome these problems, one must choose to use either a double-diffused drain (D D D) or a lightly doped non-drain (L D D). The two types of structures mentioned above have the same purpose, that is, to absorb some potential energy in the drain to reduce the maximum electric field. The popularity of double-diffused drain structures has given way to lightly doped drain structures because double-diffused drains can cause unacceptable deep junctions and harmful junction capacitances. A conventional lightly doped electrode is self-aligned to the gate electrode by a low-concentration impurity, and then is aligned to the gate electrode by a higher impurity above the two formed sidewall spacers. The channel near the gate edge, the use of the first implant dose produces a slightly doped cross-section in the source and; regions. The space for the second implant dose is a distance from the channel by the thickness of the side wall gap. As a result of the first and second implants, an impurity gradient occurs at the junction between the source and the channel, and occurs

4 429 1 9 Case No. 88116902 Amendment V. Description of the Invention (6) The junction between the drain and the channel is the same. The lightly doped drain structure must have a minimum thermal chirp. , Xiangtai can enroll Maolin 66,: JS 扬 /: ¾ for thunder. In addition " " " _ carrier effect, but can not lose additional source / drain resistance. In addition, a lightly doped drain is implanted near the channel, which unfortunately adds an electrical source / drain path. The added resistance is generally referred to as parasitic resistance. The parasitic resistance has many harmful effects. First, parasitic resistance may reduce saturation current. Secondly, the parasitic resistance may reduce the speed of the entire transistor. Appropriately designing a lightly doped source / drain to overcome the above-mentioned problems ′ can be applied to n-channel transistors and p-channel transistors. However, a method will be used in the manufacturing process of complementary metal-oxide-semiconductor field-effect transistor (CMOS). Use existing process technology to manufacture complementary metal-oxide-semiconductor half-field-effect transistors. Based on many existing process technologies, the complementary metal-oxide-semiconductor half-effect transistor is improved to achieve the desired complementary metal-oxide-semiconductor half-effect transistor with low resistance (100wresistance) and ultra shallow junction 5- 3 Object and Summary of the Invention: In the background of the present invention, a method for forming a complementary metal-oxide-semiconductor half-field-effect transistor (CMOS) with low resistance and ultra shallow junction is provided. In addition, the structure of a typical complementary metal-oxide-semiconductor field-effect transistor includes a p-type complementary metal-oxide-semiconductor field-effect transistor.

Page 10 Λ 4429 1 9 ----- Case No. 88116902_Year Month and Day Amendment_ V. Description of the invention (7) Transistor (p-we 丨 i CMOS) 'η-type complementary metal-oxide half field effect transistor (p-well CMOS), and dual-well complementary metal-oxide-semiconductor field-effect transistor (twi η-we 1 1 c M 0 S). However, in this embodiment, only the n-type complementary metal-oxide-semiconductor field-effect transistor is described in detail. As for the structures of the other two complementary metal-oxide-semiconductor half-field-effect transistors, it is also included therein. In this embodiment, the steps of this manufacturing method are as follows. First, a region of a complementary metal-oxide-semiconductor field-effect transistor is provided on or in a single crystal silicon substrate of a P-type impurity. Then, an n-well region is formed in a p-type semiconductor substrate. Then, a relatively deep shallow trench isolation (STI) is formed in the p-type semiconductor substrate and a part of the n-type well region, thereby forming a p-type metal-oxide-semiconductor field-effect transistor active region (PMOSFET active regi ο η). ) And an n-type metal-oxide-semiconductor half-field-effect transistor active region (NMOSFET active region). A channel is formed in the active region of the p-type metal-oxide half-field effect transistor and the active region of the n-type metal-oxide half-field effect transistor. After that, a gate oxide layer (gate ox i de 1 ay er) is formed on the active region of the p-type metal-oxide-semiconductor field-effect transistor and the active region of the n-type metal-oxide-semiconductor field-effect transistor. Then on top of the gate oxide layer, a polycrystalline stone gate (po 1 y s i 1 i con gat e) is deposited. Next, the polysilicon gate and gate oxide layers are etched to form a p-type metal-oxide-semiconductor half-field-effect transistor gate pattern (PMOSFET gate pattern) over the active region of the p-type metal-oxide-semiconductor half-field effect transistor and an n-type metal-oxide half-field The NMOSFET gate pattern is above the active area of the n-type MOSFET. A first defined photoresist layer is formed above the active region of the p-type metal-oxide-semiconductor field-effect transistor and a portion of the shallow trench. After that, an n-type impurity is implanted in the active region of the n-type metal-oxide-semiconductor field-effect transistor to form a lightly doped

Page II Λ429 1 9 _Case No. 88116902_ Year and month Amendment_ V. Explanation of the invention (8) Lightly doped source / drain. Then, the first defined photoresist layer is removed. In shallow trench isolation, n-type metal-oxide-semiconductor field-effect transistor gate pattern, p-type metal-oxide-semiconductor field-effect transistor gate pattern, n-type metal-oxide-semiconductor field-effect transistor active region, and p-type metal-oxide semi-effect transistor active region Above the area, a dielectric layer is deposited. A second defined photoresist layer is formed on the dielectric layer. After that, a part of the dielectric layer is etched for the first time on the active region of the p-type metal-oxide-semiconductor half field effect transistor and a part of the shallow trench isolation. Then, during a part of the dielectric layer etching step, a compensation gap (0 f f s e t s p a c e r) is formed over the active region of the p-type metal-oxide half field effect transistor. Then, the second defined photoresist layer is removed. On a part of the shallow trench isolation, the active region of the p-type MOSFET, the gate pattern of the p-type MOSFET, the compensation gap, and the dielectric layer, a shed glass layer is deposited. (BSG 1 ayer). Then, a part of the stone crushing glass layer and a part of the dielectric layer are etched for a second time, thereby forming a first borosilicate glass spacer and a second shed glass spacer Wall (second BSG spacer). After that, a p-type impurity is implanted in the active region of the p-type metal-oxide half field-effect transistor to form a p-type heavily doped source / drain. Next, an n-type impurity is implanted in the active region of the n-type metal-oxide-semiconductor half-effect transistor to form a n-type heavily doped source / drain. Finally, the first borosilicate glass spacer is tempered, and the boron atoms are diffused in the area below the first borosilicate glass spacer, thereby forming a source / drain extension junction in a p-type gold-oxygen half field effect transistor. . 5-4 Invention Details:

Page 12 Λ429 1 9 Case No. 88116902 Amendment V. Description of the Invention (9) A method for manufacturing complementary metal-oxide-semiconductor half-field-effect transistors using butterfly glass to form P-type metal-oxide-semiconductor half-field effect source / drain extension junctions The method is described in detail below. The structure of a typical complementary metal-oxide-semiconductor field-effect transistor includes a p-well complementary metal-oxide-semiconductor field-effect transistor (P-well CMOS), an n-well complementary metal-oxide-semiconductor field-effect transistor (p-well CMOS), and Double well complementary metal-oxide half-field effect transistor (twi η-we 1 1 C Μ 0 S). However, in this embodiment, only the η-type complementary metal-oxide-semiconductor field-effect transistor is described in detail, and the structures of the other two complementary metal-oxide-semiconductor half-field-effect transistors are also included therein. The first to eighth drawings are cross-sectional views of a process for manufacturing a complementary metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention. According to the diagram of the first figure, a region of a complementary metal-oxide-semiconductor field-effect transistor is provided on or in a p-type single crystal silicon substrate with a < 100 > crystal lattice orientation. This p-type semiconductor substrate (p-type semiconductor subs ΐ ra t e) 1 0 has a concentration of less than about 1.0 E 1 5 atoms per cubic centimeter. Then, an n-type well region (η-we 1 1 regi ο η) 15 is formed, and an ion implantation procedure using phosphorus (P) as an ion source is performed at an energy of about 10 OKeV to 2 0 KeV. Inject a dose of approximately 1.0E 1 2 to 1.0 E 1 3 atoms per square centimeter, and then use a drive-i η procedure at a temperature of approximately 1000 degrees to form a concentration The n-type well region 15 having a diameter of 1.0 0 E 1 per cubic centimeter is above the p-type semiconductor substrate 10. After that, a relatively deep shallow trench isolation (ST I) 20 is formed around the P-type semiconductor substrate 10 and a part of the n-type well region 15 to isolate the leakage current between the element regions, thereby forming Active region of a p-type metal oxide half field effect transistor (

Page 13 " .V 4Λ29 1 9 r_ Case No. 88116902 _iL_ Month Day Amendment V. Description of the invention (10) PMOSFET active region) 5 0 0 and a shot of metal-oxide-semiconductor half field effect transistor active region ) 505. An ion using boron (B) or boron fluoride (BF 2) as an ion source in the active region 500 of the p-type metal-oxide-semiconductor field-effect transistor and the active region 500 of the eta-type metal-oxide-semiconductor half-field-effect transistor. In the implantation procedure, a dose of about 1.0 OE 12 atoms per square centimeter is implanted at an energy of about 10 K e V to form a channel 25. After that, a thermal oxidation method is used on the p-type metal-oxide-semiconductor active region 500 and the n-type metal-oxide-semiconductor active region 505. This thermal oxidation method includes a dry oxidation method ( dry ο X idati η) and a wet oxidation method to form a gate oxide 1 ayer 3 0. Then, a polysilicon gate 35 is deposited on the gate oxide layer 30. Using silane as a source gas, low-pressure chemical vapor deposition (LPCVD) technology is used to form a polycrystalline silicon layer at a temperature of about 600 to 650 degrees, with a thickness of about 10 0 0 Angstroms to 2 500 Angstroms. Next, the polysilicon gate 35 and the gate oxide layer 30 are etched to form a p-type gold-alloy half-field-effect transistor gate pattern (PM0SFET gate pattern) 4 5 above the p-type metal-oxide half-field-effect transistor active region 50 0. And an n-type metal-oxide-semiconductor half-field-effect transistor gate pattern (NMOSFET gate pattern) 40 above the n-type metal-oxide-semiconductor half-field-effect transistor active region 505. According to the diagram in the second figure, a first defined photoresistive layer 50 A is formed above the active region 500 of a P-type metal-oxide-semiconductor field-effect transistor and a portion of the shallow trench isolation 200. Afterwards, in the active region of the η-type metal-oxide-semiconductor field-effect transistor 5 05, an ion implantation procedure using Jing (P) or arsenic (A s) as an ion source is performed at an energy of less than 30 K e V 'Implant a dose approximately

Page 14 ___ Case No. 88116902 V. Description of Invention (11)

1. 0E 14 to 5. 0E 15 atoms to form a lightly doped source / drain 50 of rr type. Then, the first defined photoresist layer 50A is removed.

According to the diagram in the third figure, a 20, η-type metal-oxide-semiconductor half-efficiency transistor gate is isolated in a shallow trench. A pole pattern of 40, ρ-type metal-oxide-semiconductor half-effect transistor pattern 45, η-type gold On top of the active area of the oxygen half field effect transistor 505 and the active area of the d-type metal oxide half field effect transistor 50 0, a dielectric layer 60 'is deposited. The dielectric layer 60 includes a siiiC0I1 oxide layer ), A silicon nitride layer (silicon nitride layer), or a silicon oxide / silicon nitride layer. The deposition method and conditions are as follows. During the deposition of the silicon dioxide layer, TEOS was used as a source gas, and low pressure chemical vapor deposition (LPCVD) technology was used. 'At a temperature of about 500 degrees to 800 degrees, A silicon dioxide layer is deposited to a thickness of about 50 angstroms to 300 angstroms. When depositing a silicon nitride layer, a low-pressure chemical vapor deposition (LpCVD) technique is used to deposit a nitrided nitride Mg ’s at a temperature of about 75 ° C and a thickness of about 50 angstroms to 300 angstroms. When depositing oxide / nitride layers, using low pressure chemical vapor deposition (LPCVD) technology, a silicon oxide / silicon nitride layer is deposited at a temperature of about 500 ° to 800 ° 100 angstroms to 300 angstroms. According to the diagram in the fourth figure, a second photoresist layer 60A is formed on the dielectric layer 60. After that, on the p-type metal-oxide-semiconductor field-effect transistor active region 500 and a portion of the shallow trench isolation 20, a reactive ion etching (R I E) technique using CHF as an etchant was used to etch a portion of the first

Page 15 V 4 429 1 9 __ Case No. 88116902-! _Λ .. Said Zheng Zheng _ V. Description of the invention (12) Dielectric layer 60. Then, during a part of the dielectric layer 60 etching step, an offset spacer 65 is formed on the P-type metal-oxide-semiconductor field-effect transistor active area 500. Then 'remove the second defined photoresist layer 60A according to the diagram of the fifth figure' to isolate a part of the shallow trench 20, P-type metal-oxide-semiconductor field-effect transistor active region 500, p-type metal-oxide-semiconductor half-field Effect transistor gate pattern 4 5. Compensating spacers 6 5 and dielectric layer 60. Using atmospheric pressure chemical vapor deposition (APCVD) technology, low pressure chemical vapor deposition (LPCVD) technology, or plasma assist The chemical vapor deposition (PEC VD) technology deposits a borosilicate glass layer (BSG layer) 70 with a thickness between about 500 angstroms and 20,000 angstroms. The deposited butterfly glass layer 70 contains a butterfly dose between about one and ten percent. According to the formula in the sixth figure, a reactive ion collar etch (RIE) technique using CHF3 as an etchant is used to 'etch a part of the collar silica glass layer 70 and a second part of the dielectric is etched. The layer 60 ′ forms a first borosilicate glass spacer (first BSG spacer) 75 and a second borosilicate glass spacer (second BSG spacer) 80. According to the diagram in FIG. 7A, the first region photoresist 5i 1 is used to cover the active region of the n-type metal-oxide-semiconductor field-effect transistor 5 0 5 and In the process, an ion implantation procedure using boron (B) or boron fluoride (Β) ρ2) as the p-type implanted ion 5 1 2 is performed to form a -p + -type heavily doped source / drain (heavi ly doped source / drain) 85, in

Page 16 V 4 429 1 9 _ΕΒ_8 «Ι16902_ V. Description of the invention (13) 2 2 Ϊ: The amount of t in the child is between about 1 KeV and 80 KeV, and its implantation dose is ΐ :: 1, 15 to UE 16 Between atoms. After: ΐI: shown in the two general Λ remove the first area photoresist 511 and form a second area light:? -Type 'oxygen half field effect transistor active area 50 0' and then in ΛΓ effect transistor active ㈣ 5 0 5 'Implement an ion implantation procedure using-(ρ) or Kun S as the η-type implant ion 5 1 4 to form a -η + -type re-transformed heterogeneous source / dimer 9 〇, where the ion implantation energy It is less than about 10 Ke e ¥ to 80 Ke V, and its implantation dose is about 15 to 1. OE 16 atoms per square centimeter. According to the diagram in the eighth figure, 'Tempering the first borosilicate glass partition wall 7 5 uses a rapid thermal process (RTP) to diffuse a boron at a temperature of about 95 ° to 1050 °. The time period of the atoms in the region below the first borosilicate glass spacer 75 is about 10 seconds to 60 seconds. Thereby, forming a source / drain extension junction (100 °) in a p-type metal-oxide-semiconductor half-field-effect transistor is only a preferred embodiment of the present invention. It is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application described below.

Page 17 4 429 1 9 _Case No. 88116902_Year Month Date __ Schematic illustrations The diagrams in the first to eighth figures are shown. According to the embodiment of the present invention, a complementary metal-oxide-semiconductor field-effect transistor is manufactured. A cross-sectional view of the process. Main symbols: 10 P-type semiconductor substrate 15 η-type well area 20 Shallow trench isolation 25 Channel 30 Gate oxide layer 35 Polycrystalline gate 40 η-type metal-oxide-semiconductor field-effect transistor gate pattern 45 ρ-type metal oxide Half field effect transistor gate pattern 50 Lightly doped source / drain 50A First defined photoresist layer 60 Dielectric layer 60A Second defined photoresist layer 65 Compensation barrier 70 Borosilicate glass layer 75 First boron Silica glass spacer 80 Second borosilicate glass spacer 85 P + -type heavily doped source / drain 90 η + -type heavily doped source / inverted 100 source / drain extension junction 500 ρ type Active region of metal oxide half field effect transistor 505 Active region of η type metal oxide half field effect transistor

P. 18 v 442919

Page 19

Claims (1)

442% No. 98_ Amendment VI. Patent Application Scope 1. A method of manufacturing a complementary metal-oxide-semiconductor field-effect transistor (CMOS) 'The method includes at least: providing a semiconductor substrate having a first conductivity ( first conductivity type); forming a well region in the semiconductor substrate, the well region having a second conductivity type, and the second conductivity and the first conductivity Instead; forming a shallow trench isolation (STI) between the semiconductor substrate and the well region, thereby forming a plurality of active regions; forming a channel between the semiconductor substrate and the well region Forming a P-type metal-oxide-semiconductor field-effect transistor (PM0SFET) gate pattern and an n-type metal-oxide-semiconductor field-effect transistor (NM0SFET) gate pattern over the semiconductor substrate and the well region; forming a first A photoresist layer has been defined over the well region; a first impurity of the second conductivity is implanted in the semiconductor substrate to form Lightly doped source / drain i; remove the first defined photoresist layer; deposit an insulating layer over the semiconductor substrate and the well region; form A second defined photoresist layer on the insulating layer; a portion of the insulating layer is etched on the well region for the first time; Page 20 'ZU29 1 9-_Case No. 88Π6902_ YYYY__ VI. The scope of the patent application forms a compensation gap (〇ffsetspacer) above the well area, during a part of the insulating layer etching step ; Remove the second defined photoresist layer; deposit a borosilicate glass (BS G) layer on the well region and the insulating layer »etch a part of the borosilicate glass layer and a second etch Part of the insulating layer, so as to form a first BSG spacer and a second borosilicate glass spacer; implanting an impurity of the first conductivity into the well region, Thereby forming a first heavily doped source / drain; implanting a second impurity of the second conductivity into the semiconductor substrate to form a second heavily doped source / drain; A source / drain, wherein a concentration of the second impurity is greater than the first impurity; and tempering the first shed glass barrier wall, diffusing atoms (b 〇r ο η atom) in the first borosilicate glass The area under the barrier wall to form a source / 源 and pole extension Extend the face. Page 21, 4429 1 9 _Case No. 88116902_Year_Month__ VI. Application for Patent Scope 4 · For the method of applying for the first item of the patent scope, in which the formation of the above well area contains at least phosphorus (P) as An ion implantation procedure of an ion source is implanted at a dose of about 1. 0E 1 2 to 1 · 0E 1 3 between an energy of about 100 K e V and 2 0 Ke V. 0 atom, and then using a drive-in program at a temperature of about 1000 degrees to form a well region with a concentration of about 1.0 0 E 16 per cubic centimeter. 5. The method according to item 1 of the patent application range, wherein the second conductive layer mentioned above includes at least an n-type. 6. The method according to item 1 of the scope of patent application, wherein the above active area includes at least an active area of a p-type metal-oxide half field effect transistor. 7. The method according to item 1 of the scope of patent application, wherein the above active area includes at least an active area of an n-type metal-oxide half field effect transistor. 8. The method of claim 1 in claim 1, wherein the formation of the above-mentioned channels includes at least an ion implantation procedure using boron (B) as an ion source at an energy of about 1 OKeV, and a dose of about 1 per square kilogram is implanted. 1. 0Ε 1 2 atoms 9. The method according to item 1 of the scope of patent application, wherein the formation of the above-mentioned channel includes at least an ion implantation procedure using II-butterfly (BF 2) as an ion source at an energy About lOKeV, implant a dose of about 1. 0E 12 Page 22 4 42 ^ 19 _Case No. 88116902_ Year Month ___ Six, the scope of patent application Atom. I 0. The method according to item 1 of the patent application range, wherein the formation of the p-type metal-oxide-semiconductor field-effect transistor gate pattern and the n-type metal-oxide-semiconductor field-effect transistor gate pattern include at least one polycrystalline silicon gate Electrode (ρ ο 1 ysi 1 ic ο nga ΐ e) and a gate oxide layer. 1 1. The method according to item 1 of the patent application range, wherein the formation of the lightly doped source / drain described above includes at least an ion implantation procedure using phosphorus (P) as an ion source at an energy of less than about 30 K e V, implanted at a dose of about 1,0 E 1 4 to 5.0 E 1 5 atoms per square centimeter. 1 2. The method according to item 1 of the scope of patent application, wherein the formation of the lightly doped source / drain described above includes at least an ion implantation procedure using arsenic (A s) as an ion source at an energy of approximately Less than 30 K e V, a dose of about 1.0 E 1 4 to 5.0 E 1 5 atoms per square centimeter is implanted. 1 3. The method according to item 1 of the scope of patent application, wherein the above-mentioned insulating layer includes at least a silicon oxide layer, using ethyl orthosilicate (TE0S) as a source gas, and low pressure chemical vapor deposition (LPCVD) technology, The insulating layer is deposited at a temperature between about 500 degrees and 800 degrees, with a thickness between about 50 angstroms and 300 angstroms. 14. The method according to item 1 of the scope of patent application, wherein the above-mentioned insulating layer is at least Page 23 4 42 9 1 9 _ Case No. 88116902 6. The scope of the patent application is amended to include a silicon nitride layer 'using low pressure chemical vapor deposition (LpcvD) technology, which is deposited at a temperature of about 7500 degrees' The insulating layer has a thickness between about 50 angstroms and 300 angstroms. 15. If you apply, please ask for the scope of patents! Method, wherein the above-mentioned insulating layer includes at least a silicon oxide / silicon nitride layer, and the insulating layer is deposited using a low pressure chemical vapor deposition (LpcVD) technology at a temperature of about 500 to 800 degrees. Layer having a thickness between about 100 angstroms and 300 angstroms. 16. The method according to item 1 of the scope of patent application, wherein the first engraving of the insulating layer mentioned above includes at least a reactive ion etching (RIE) technique using CHF 拃 as an etchant. 1 7. The method according to item 1 of the scope of patent application, which enables the above-mentioned deposition of borosilicate glass (BSG) layer to include at least atmospheric pressure chemical vapor deposition (APCVD) technology, and has a thickness of about 50 angstroms to 20 angstroms. Between 0 0 Angstroms. 18 The method according to item 1 of the scope of patent application, wherein the above-mentioned deposition of a borosilicate glass (BSG) layer includes at least a low pressure chemical vapor deposition (LPCVD) technology, and has a thickness of about 500 angstroms to 2000 angstroms. between. 19. The method according to item 1 of the scope of patent application, wherein the above-mentioned borosilicate glass (BSG) layer is deposited 'at least including plasma assisted chemical vapor deposition (pECVD) technology' and has a thickness of about 50 Angstroms to 2 0 Between 0 0 Angstroms. 4429 1 9 _ cable number 88Π6902 amended on __- ^ 6 'application for patent scope 20. If the method of applying for the scope of the first item of the patent application, wherein the above-mentioned deposition of borosilicate broken glass can contain at least a boron dose of about one hundred 0 · 10% to 0% 1 · The method according to item 1 of the patent application range, wherein the above-mentioned borosilicate glass etching includes at least reactive ion etching (RI using CHF 拃 as an etchant) Ε) Technology ^ 2 2. The method according to item 1 of the scope of patent application, wherein the second etching of the above-mentioned insulating layer includes at least a reactive ion engraving (RI EI) technology using CHF 拃 as an etchant. 23. The method of claim 1, wherein the formation of the first heavily doped source / drain described above includes at least an ion implantation procedure using boron (B) as an ion source at an energy of approximately Between 1 K e V and 80 Ke V 'implantation—the dose is approximately between 1.0 and 1.0 E 16 per square centimeter. 24. The method according to item 1 of the scope of the patent application, wherein the formation of the above-mentioned heavily doped source / deposit electrode includes at least an ion implantation procedure using a fluoride booth (BF z) as an ion source, Between an energy of about IKeV and about 80KeV, a dose of about 1.0 E 1 5 to 1.0 E 1 6 atoms per square centimeter is implanted. 25. The method according to item I of the scope of patent application ', wherein the above-mentioned first reintroduction Page 25, 4429 1 9 _Case No. 88116902_Year_Month__ VI. The formation of the source / drain in the patent application scope includes at least the ion implantation procedure with filling (P) as an ion source. The energy is less than 1 OKeV to 80KeV, and a dose of about 1.0 E 1 5 to 1.0 E 1 6 atoms per square centimeter is implanted. 2 6 · The method according to item 1 of the patent application range, wherein the first heavily doped source / drain is formed, including at least an ion implantation procedure using arsenic (As) as an ion source at an energy About less than 1 OKeV to 8 OKeV, a dose of about 1 · 0 E 1 5 to 1, 0 E 1 6 atoms per square centimeter is implanted. 2 7. The method according to item 1 of the scope of patent application, wherein the above-mentioned diffusion of boron atoms includes at least a rapid thermal process (RTP), and the diffusion is performed at a temperature of about 950 degrees to 105 degrees. Boron atom, its time is about 10 seconds to 60 seconds. 28. A method for manufacturing a complementary metal-oxide-semiconductor field-effect transistor (CMOS), the method at least includes: providing a p-type semiconductor substrate (p-type semiconductor substrate); forming an n-well region in the p-type semiconductor substrate; forming a shallow trench isolation (STI) on the p-type semiconductor substrate and a portion of the n In the well region, a P-type metal-oxide-semiconductor field-effect transistor (PM0SFET) active region (act i ve regi ο η) and an n-type metal-oxide-semiconductor field-effect transistor (NM MOS 0 SFET) active region are formed; Page 26 4429 1 9 _ Case No. 88116902 Amended 6. The scope of the patent application forms a channel in the active region of the p-type metal-oxide-semiconductor field-effect transistor and the active region of the n-type metal-oxide-semiconductor field-effect transistor. A gate oxide layer (gate ο X ide 1 ayer) is formed on the active region of the p-type metal-oxide-semiconductor field-effect transistor and the active region of the n-type metal-oxide-semiconductor field-effect transistor; a polycrystalline stone is deposited The inter-pole (ρ ο 1 ysi 1 ic ο ngate) is on the gate oxide layer; the maggot engraved the polycrystalline stone gate and the gate oxide layer to form a p-type metal-oxygen half field effect transistor gate A pole pattern is above the active region of the p-type metal-oxide-semiconductor field-effect transistor and an n-type metal-oxide-semiconductor field-effect transistor gate pattern is formed over the active region of the n-type metal-oxide-semiconductor field-effect transistor; forming a first defined A photoresist layer is isolated on the active region of the p-type metal-oxide-semiconductor field-effect transistor and a part of the shallow trench; an n-type impurity is implanted in the active region of the n-type metal-oxide-semiconductor field-effect transistor to form A lightly doped source / drain (Lightly doped source / dra in); removing the first defined photoresist layer; depositing a dielectric layer to isolate the shallow trench, the n-type metal-oxide-semiconductor field-effect transistor gate pattern, the ρ A gate pattern of a metal oxide semiconductor field-effect transistor, the active region of the n-type metal oxide semiconductor field effect transistor, and the active region of the p-type metal oxide semiconductor field effect transistor; forming a second defined photoresistive layer on the dielectric; Above the electrical layer; for the first time, a part of the dielectric layer is isolated on the p-type metal-oxygen half-field-effect electrical-a body active region and a part of the shallow trench; Page 27 d429 1 9 _ Case No. 88116902 Amendment VI. The scope of the patent application forms a compensation gap (0ffsetspacer) above the active area of the p-type metal-oxygen half field effect transistor. During the electrical layer etching step; removing the second defined photoresist layer; depositing a borosilicate glass (BSG) layer in a portion of the shallow trench isolation, the active area of the P-type metal-oxygen half field effect transistor, the p -Type metal-oxide-semiconductor field-effect transistor gate pattern, the compensation spacer, and the dielectric layer; a part of the borosilicate glass layer is etched and a part of the dielectric layer is etched a second time to form A first shed glass spacer (BSG spacer) and a second borosilicate glass spacer; a first photoresist is used to cover the active area of the n-type metal-oxide-semiconductor field-effect transistor, and a p-type impurity is implanted in In the active region of the p-type metal-oxide half field effect transistor, a p-type heavily doped source / and (hea ν i 1 y doped source / drain) is formed; the first photoresist is removed and a Second photoresist covers p-type metal-oxide half field effect transistor An active region, and an n-type impurity is implanted in the active region of the n-type metal-oxide half field effect transistor to form an n-type heavily doped source / drain; and tempering the first shed stone A glass spacer wall, with a diffusion atom (b ο ο η atom) in a region below the first borosilicate glass spacer wall, thereby forming a source / drain extension interface to a p-type metal-oxide-semiconductor field-effect transistor. in. 29. The method according to item 28 of the scope of patent application, wherein the above-mentioned p-type semiconductor substrate contains at least a concentration of less than about 1, 0 E 1 5 atoms per cubic centimeter. Page 28:; V 4429 1 9 _ Case No. 88116902 _ 6 、 Applicable patent scope 30 • If the method of the patent application scope No. 28, the formation of the above-mentioned n-type well area contains at least phosphorus (.P) is an ion implantation procedure for an ion source, implanting a dose between 1 · 0 E 1 2 and 1.0 E 1 3 between an energy of approximately 100 OKeV and 200 KeV. Then, a drive-i η program is used to form a n-type well region with a concentration of about 1.0 0 E 16 atoms per cubic centimeter at a temperature of about 1000 degrees. 3 1. The method according to item 28 of the scope of patent application, wherein the formation of the above-mentioned channels includes at least an ion implantation procedure using boron (B) as an ion source, at an energy of about 1 OKeV, and implanting a dose of about 1. 0Ε 1 2 atoms per square centimeter. 32. The method according to item 28 of the scope of patent application, wherein the formation of the above-mentioned channels includes at least an ion implantation procedure using boron fluoride (BF 2) as an ion source, and implanting at an energy of about 1 OKeV. One dose is about 1.0E 1 2 atoms per square centimeter. 3 3. The method according to item 28 of the scope of patent application, wherein the formation of the above-mentioned gate oxide layer includes at least a thermal oxidation method. 3 4. The method according to item 33 of the scope of patent application, wherein the above-mentioned thermal oxidation method includes at least a dry oxidation method (d r y ο X i d a t i ο η) and a wet oxidation method Page 29 -V 4 429 19 '_Case No. 88116902_Year Month _ ^ _ VI. Wet oxidation application. 35. The method according to item 28 of the scope of patent application, wherein the formation of the lightly doped source / drain described above includes at least an ion implantation procedure using phosphorus (P) as an ion source at an energy of approximately Less than 30 KeV, a dose of between 1.0 E 1 4 and 5.0 E 1 5 is implanted. 3 6. The method according to item 28 of the scope of patent application, wherein the formation of the lightly doped source / drain described above includes at least an ion implantation procedure using arsenic (A s) as an ion source at an energy Approximately less than 30 K e V, a dose of about 1 · 0 E 1 4 to 5.0 E 1 5 atoms per square centimeter is implanted. 37. The method according to item 28 of the scope of patent application, wherein the above-mentioned dielectric layer includes at least a fragmented dioxide layer, and uses TEOS as a source gas in low-pressure chemical vapor deposition. (LPCVD) technology, the dielectric layer is deposited at a temperature of about 500 degrees to 800 degrees, with a thickness of about 50 angstroms to 300 angstroms. 38. The method of claim 28, wherein the dielectric layer includes at least one gasification layer, and the dielectric is deposited using a low pressure chemical vapor deposition (LPCVD) technology at a temperature of about 750 degrees. Layer with a thickness between about 50 angstroms and 300 angstroms. 3 9. The method according to item 28 of the scope of patent application, wherein the above-mentioned dielectric layer to Page 30, 442919 _ Case No. 88116902 _ Month and Day _fvi._ VI. The scope of patent application includes silicon monoxide / silicon nitride layer, using low pressure chemical vapor deposition (LPCVD) technology, at a temperature of about 50 Between 0 and 800 degrees, the dielectric layer is deposited to a thickness of between about 100 and 300 angstroms. 40. The method according to item 28 of the scope of patent application, wherein the first contact of the dielectric layer described above includes at least a reactive ion | insect etch (R I E) technique using CHF as a food engraving agent. 4 1. The method according to item 28 of the scope of patent application, wherein the deposition of the above borosilicate glass (BSG) layer includes at least atmospheric pressure chemical vapor deposition (APCVD) technology and has a thickness of about 50 angstroms to 20 angstroms. Between 0 0 Angstroms. 4 2. The method according to item 28 of the scope of patent application, wherein the deposition of the above-mentioned borosilicate glass (BSG) layer includes at least low-pressure chemical vapor deposition (LPCVD) technology and has a thickness of about 50.0 angstroms to 2 0 Between 0 0 Angstroms. 43. The method according to item 28 of the scope of patent application, wherein the above-mentioned deposition of borosilicate glass (BSG) layer includes at least plasma-assisted chemical vapor deposition (PECVD) technology, and its thickness is about 500 Angstroms to 2 0 0 0 Angstroms. 4 4. The method according to item 28 of the scope of patent application, wherein the deposition of the above borosilicate glass layer comprises at least a boron dose of between about 1% and 10%. Page 31 *. 4A29 ^ 9 _ Case No. 88116902 _ month and year __ Six, the scope of patent application 4 5. If the method of the scope of patent application No. 28, wherein the above-mentioned etching of the borosilicate glass layer includes at least CHF 拃 is a reactive ion etching (RIE) technology of an etchant. 46. The method according to item 28 of the scope of patent application, wherein the second etching of the above-mentioned insulating layer includes at least a reactive ion engraving (R I E) technique using CHF as a post-etching agent. 47. The method according to item 28 of the scope of patent application, wherein the formation of the P-type heavily doped source / drain described above includes at least an ion implantation procedure using boron (B) as an ion source in a The energy is between about IKeV and 80KeV, and a dose of about 1.0 Ε 1 5 to 1.0 Ε 1 6 per square centimeter is implanted. 48. The method according to item 28 of the scope of patent application, wherein the formation of the above-mentioned P-type heavily doped source / drain includes at least an ion implantation procedure using boron fluoride (BF 2) as an ion source. At an energy of about IKeV to 80KeV, a dose of about 1.0 Ε 1 5 to 1.0 0 Ε 16 is implanted at a dose. 4 9 · The method according to item 28 of the scope of patent application, wherein the formation of the n-type heavily doped source / drain includes at least an ion implantation procedure using phosphorus (P) as an ion source. The energy is about less than lOKeV to 80KeV, and a dose of about 1.0E 15 to 1.0E 16 atoms per square centimeter is implanted. 50. The method according to item 28 of the scope of patent application, wherein the η honey is re-blended Page 32, Λ429 1 9 _Case No 88116902_Year Month __ VI. The formation of a source / drain with a range of patent applications, including at least an ion implantation procedure using arsenic (A s) as an ion source, Between an energy of approximately less than 1 OKeV and 80 KeV, a dose of approximately 1.0 E 1 5 to 1.0 E 1 6 atoms per square centimeter is implanted. 51. The method according to item 28 of the scope of patent application, wherein the above-mentioned diffusion of boron atoms includes at least a rapid thermal process (RTP), and the diffusion is at a temperature of about 950 degrees to 105 degrees. The boron atom has a time between about 10 seconds and 60 seconds. Page 33