TWI427707B - Method for fabricating mos transistors - Google Patents

Description

Method for fabricating a MOS transistor

The present invention relates to a method of fabricating a MOS transistor, and more particularly to a method of forming a fluorinated interfacial layer prior to fabrication of a deuterated metal.

In the process of semiconductor integrated circuit, metal-oxide-semiconductor (MOS) transistor is a very important electronic component, and as the size of semiconductor component becomes smaller and smaller, the manufacturing process of MOS transistor also has Many improvements have been made to produce small, high quality MOS transistors.

The conventional MOS transistor process is to form a lightly doped drain (LDD) in a substrate on opposite sides of the gate structure after forming a gate structure on the semiconductor substrate. Then, a spacer is formed on the side of the gate structure, and the gate structure and the sidewall are used as a mask, and an ion implantation step is performed to form a source/drain region in the semiconductor substrate. In order to properly electrically connect the gate, source and drain of the transistor to the circuit, it is necessary to form a contact plug for conduction. Generally, the material of the contact plug is a metal conductor such as tungsten (W), aluminum or copper, but direct conduction between a material such as a gate structure, a source/drain region, or a single crystal germanium is not preferable; Therefore, in order to improve the Ohmi contact between the metal plug and the gate structure and the source/drain region, it is usually in the gate structure, source/ A metal silicide is formed on the surface of the bungee region.

At present, most of them use a self-aligned silicide (salicide) process to form a metal telluride; that is, after forming a source/drain region, a cobalt (Co), titanium (Ti) is formed. a metal layer composed of nickel (Ni) and the like, covering the source/drain region and the gate structure, and then performing a rapid thermal anneal (RTA) process to make the metal layer and the gate structure and source/ The ruthenium reaction in the drain region forms a metal ruthenium to reduce the sheet resistance of the source/drain regions.

However, the formation of metal telluride in this manner also causes problems, such as when metal halides are formed, metal atoms in the metal layer diffuse into the germanium substrate and consume the germanium in the source/drain regions to complete. Not only the lattice structure in the original source/drain region will be destroyed, but also the distance between the PN junction between the source/drain region and the germanium substrate and the germanium metal layer is too close to destroy some of the source/deuterium. Part of the structure of the polar region, especially in the design of the ultra shallow junction (USJ), may even cause direct contact between the metal telluride and the substrate, which may lead to component failure.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams showing a process for fabricating a gold-oxygen semiconductor transistor having a self-aligned metal telluride. As shown in FIG. 1, a semiconductor substrate 60 is first provided, and then a gate structure 66 composed of a gate dielectric layer 62 and a gate conductive layer 64 is formed on the semiconductor substrate 60, and the top of the gate 66 is separately provided. There is a top protective layer (not shown) composed of a dielectric material such as tantalum nitride or hafnium oxide. An ion implantation step is then performed to form the lightly doped source/drain 70 in the semiconductor substrate 60 on either side of the gate structure 66. Substrate layer 67 and sidewall spacers 68 are then formed on the sidewalls of gate structure 66 and another ion implantation step is performed to form source/drain regions 72 in semiconductor substrate 60 on either side of sidewall spacer 68. A wet cleaning process is then performed to remove impure particles or native oxide on the surface of the gate structure 66 and the source/drain regions 72, and a degas removal step is performed to remove the wet cleaning process. Excess water. Subsequently, a metal layer 74, such as a nickel metal layer, is sputtered over the surface of the semiconductor substrate 60 and overlies the gate 64, the sidewall spacers 68, and the surface of the semiconductor substrate 60. Next, as shown in FIG. 2, a rapid thermal annealing process (RTA) is performed to react a portion of the metal layer 74 in contact with the source/drain region 72 into a deuterated metal layer 76. Finally, a selective wet etching is used, for example, a mixed solution of NH ₄ OH/H ₂ O ₂ /H ₂ O or H ₂ SO ₄ /H ₂ O ₂ to remove the metal layer 74 which is not reacted into the metal halide.

As described above, in order to avoid the MOS short channel effects derived from the reduction in the design of the transistor due to the increase in the degree of component accumulation, and to improve the interconnect resistance of the integrated circuit, The junction depth of the source and the drain of the transistor must be reduced to produce a transistor containing a metal telluride. However, while the junction depth between the source and the drain is reduced, if the source and the drain are thinned The thickness of the metal telluride may cause excessive interconnect resistance and contact resistance; however, if the metal telluride on the source and drain is maintained at a certain thickness, it may result in The distance between the PN junction between the source/drain region 72 and the germanium substrate 60 and the germanium metal layer 76 is too close to cause junction leakage of the MOS transistor. Moreover, the solvent used in the wet cleaning process before the deuteration metal reaction also causes erosion of the liner layer between the gate and the sidewall, so that the subsequent deuteration metal reaction makes the deuterated metal more accessible to the channel region. A so-called "nickel silicide piping" effect is produced.

In addition, the thermal stability of some metal halides is not good, and the as-deposition formed in the metal sputtering process is not even before the rapid temperature annealing treatment. A metal telluride having a polycrystalline structure may be formed due to a higher process temperature of the PVD reaction chamber in which the plasma is generated, or because of the high temperature of the water removal step before the metal deposition, that is, when the temperature is too high or When the high temperature treatment time is slightly longer, the metal telluride will agglomerate and become a piece of unconnected mass, resulting in an increase in sheet resistance, even in the subsequent high temperature process. Conversion occurs, excessive enthalpy is consumed, and spiking occurs on the shallow joint or a structure that forms a high resistivity, such as a low resistivity nickel (NiSi) type (about less than 20 μΩ - Cm) will be converted into a high resistivity nickel (NiSi ₂ ) type (about 50 μΩ-cm).

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method for fabricating a MOS transistor to improve the conventional formation of a nickel halide conduction or a metal sulphide agglomeration when a transistor having a metal ruthenium is produced.

A preferred embodiment of the present invention provides a method of fabricating a MOS transistor comprising the following steps. First, a semiconductor substrate is provided having a gate structure thereon, and the gate structure has a gate dielectric layer and a gate conductive layer. A source/drain region is then formed in the semiconductor substrate and a cleaning step is performed to remove oxides from the surface of the semiconductor substrate. An oxidizing agent is then used to oxidize the surface of the semiconductor substrate to form an oxide layer on the surface of the semiconductor substrate. The semiconductor substrate is then surface treated with a fluorine-containing plasma to react the fluorine-containing plasma with the oxide layer to form a fluorine-containing interface layer, and then a metal layer is deposited on the semiconductor substrate. Finally, a heat treatment is performed on the semiconductor substrate to form a deuterated metal layer.

The invention mainly removes the native oxide on the surface of the semiconductor substrate by a cleaning step before performing the metal telluride process, and then performs an oxidation process to form an oxide layer on the surface of the semiconductor substrate. The oxide layer is then subjected to a plasma treatment to convert the oxide layer into a fluorine-containing interface layer, followed by a subsequent metal halide process. Due to fluorine in the fluorine-containing interface layer The atom can make the deuterated metal not too close to the channel region when the deuterated metal reacts, and the present invention can improve the situation in which the conduction or agglomeration is easily generated in the deuterated metal process by using the fluorine-containing interfacial layer.

Please refer to FIG. 3 to FIG. 7 . FIG. 3 to FIG. 7 are schematic diagrams showing a process for fabricating a MOS transistor according to a preferred embodiment of the present invention. As shown in FIG. 3, a semiconductor substrate 100 is first provided, such as a wafer or a silicon-on-insulator (SOI) substrate, etc., which may include gates for different product requirements and process designs on or in the substrate. The structure of the source/drain region, the insulating region, the word line or the resistor, etc., in the preferred embodiment of the third to seventh embodiments of the present invention, the gate structure and the source/drain of the MOS transistor The area is explained. As shown in FIG. 3, the gate structure 106 includes a gate dielectric layer 102 and a gate conductive layer 104. The gate dielectric layer 102 may be composed of one or more of a silicon oxide compound, a nitrogen compound, a nitrogen oxide compound, a metal oxide, etc., and the gate 104 is doped polysilicon, metal telluride. Or a conductive material such as metal. A top protective layer 124 is further disposed on the top of the gate 104, and the top protective layer 124 is formed of a dielectric material such as tantalum nitride or tantalum oxide.

Subsequently, a lightly doped ion implantation process is performed, and a lightly doped material (not shown) is implanted into the semiconductor substrate 100 on opposite sides of the gate 104 to form a mask. Source/drain extension (source/drain) Extension, SDE) or lightly doped source/drain 110. The type of impurity implanted is related to the type of MOS; if the NMOS is implanted with N-type impurities such as phosphorus or arsenic, if the PMOS is implanted with P-type impurities such as boron. It should be noted that a selective sidewall (not shown) may be formed on the surrounding sidewalls of the gate structure 106 using a deposition and etching process prior to source/drain extension or lightly doped source/drain formation; When performing a lightly doped ion implantation process, the gate 104 and the selective sidewalls are used as a mask to implant impurities.

Next, a selective liner layer 107, such as an oxygen layer, and a single sidewall or a plurality of sidewalls 108 composed of a nitrogen ruthenium compound are formed on the sidewalls of the gate structure 106 by a deposition and etching process. The material of the backing layer 107 and the sidewall spacers 108 may be any insulating material.

Then, a heavily doped ion implantation process is performed, and a heavily doped substance (not shown) is implanted into the semiconductor substrate 100 by using the gate 104 and the sidewall spacers 108 as a mask to form a doping in the semiconductor substrate 100. A higher concentration source/drain region 112. Unlike the implanted impurity type of the lightly doped source and the drain 110, the NMOS implants an N-type impurity such as phosphorus or arsenic, and the PMOS implants a P-type impurity such as boron. A high temperature tempering process is then performed to activate the doping in the semiconductor substrate 100 using a high temperature of 1000 to 1050 ° C, and simultaneously repair the crystal on the surface of the semiconductor substrate 100 damaged in each ion implantation process. Grid structure.

It should be understood by those skilled in the art that although the above aspects of the present invention describe in detail the formation of the sidewall, lightly doped source/drain, source/drain, the invention is not limited thereto. All manufacturing methods capable of forming a sidewall, a lightly doped source/drain, and a source/drain are included in the scope of the present invention. For example, the order in which the sidewalls, the lightly doped source/drain, and the source/drain are formed may vary. In one embodiment, a single or a plurality of sidewalls may be formed first, followed by formation of a lightly doped source/drain, and finally the outermost layer of the single sidewall or plurality of sidewalls may be removed for source/drain implantation. In another embodiment, in addition to the original sidewall, lightly doped source/drain, source/drain formation, the source/drain may be formed on both sides of the gate structure before forming the source/drain A trench is formed and a material such as SiC or SiGe required for NMOS and PMOS is grown in the trench in an epitaxial manner.

Subsequently, a cleaning step is performed to completely remove the native oxide and other impurities remaining on the surface of the source/drain region 112 by using a cleaning solution such as hydrogen fluoride (HF), and can selectively perform A degas removal step is performed to remove excess moisture formed by the cleaning step. Then, as shown in FIG. 4, the surface of the semiconductor substrate 100 is subjected to an oxidation process using an oxidant to form an oxide layer 120 on the surface of the semiconductor substrate 100. According to a preferred embodiment of the present invention, the present invention mainly utilizes an oxidizing agent such as ammonia water mixture (APM) or hydrogen peroxide (H ₂ O ₂ ) to conduct the surface of the semiconductor substrate 100 during the oxidation process. The oxidation treatment is performed to form an oxide layer 120 having a thickness of about 5 angstroms to 20 angstroms on the surface of the semiconductor substrate 100, and the formed oxide layer 120 is mainly composed of cerium oxide (SiO ₂ ). It should be noted that the process conditions such as temperature, oxidant concentration, oxidation time, and the like in this step can be controlled to form the oxide layer 120 of good quality and having a desired thickness.

As shown in FIG. 5, the semiconductor substrate 100 is then surface treated with a fluorine-containing plasma to react the fluorine-containing plasma with the oxide layer 120 to form a fluorine-containing layer 122. In the preferred embodiment, the present invention first provides a reaction gas such as nitrogen trifluoride (NF ₃ ) and ammonia (NH ₃ ), and then the plasma is dissociated by plasma to produce ammonium fluoride (NH _{4 ).} F) a mixed gas with hydrogen fluoride ammonium fluoride (NH ₄ F.HF). Then, a surface of the oxide layer (SiO ₂ ) 120 on the surface of the semiconductor substrate 100 is subjected to a surface treatment using a mixed gas of ammonium fluoride (NH ₄ F) and hydrogen fluoride ammonium fluoride (NH ₄ F. HF) to make the fluorine-containing electricity. The slurry reacts with the oxide layer 120 to form a fluorine-containing interface layer 122 composed of ammonium fluoroantimonate ((NH ₄ ) ₂ SiF ₆ ) on the surface of the semiconductor substrate 100. It should be noted that this plasma may be formed in an in-situ manner in the processing chamber to directly react with the semiconductor substrate 100 in the processing chamber; or the plasma may be formed using a remote plasma source and then transported to a process. The chamber reacts with the semiconductor substrate 100. Further, the reaction can be carried out at a low temperature such as room temperature. In accordance with a preferred embodiment of the present invention, the present invention utilizes fluorine atoms in the fluorine-containing interface layer to avoid the occurrence of piging or agglomeration of subsequently formed metal halides.

Then, as shown in FIG. 6, the in-situ deposition method can be selectively used to control the process temperature in the physical vapor deposition (PVD) reaction chamber below 150 ° C, and then a metal is sputtered on the semiconductor substrate 100. The layer 114 covers the gate structure 106, the sidewall spacers 108, and the fluorine-containing interface layer 122 on the surface of the semiconductor substrate 100. The metal layer 114 may be selected from the group consisting of tungsten, cobalt, titanium, nickel, platinum, palladium, molybdenum, etc., or an alloy of the above metals. It should be noted that the present invention can simultaneously remove the top protective layer 124 on the top of the gate conductive layer 104 by an additional etching process or directly by the cleaning step of removing the oxide layer 120 before forming the metal layer 114. The scope covered.

Then, the process temperature in the PVD reaction chamber is continuously maintained below 150 ° C, and a mask layer 116 composed of titanium or titanium nitride is selectively deposited on the surface of the metal layer 114. Since a part of the metal telluride is formed, for example, Nisi or the like often causes a large junction leakage current, the present invention can cover a capping layer 116 on the metal layer 114 after the metal layer 114 is formed, except that rapid temperature rising annealing can be avoided. The diffusion of oxygen atoms in the (RTA) process can simultaneously improve the material stress at the edge of the element isolation region.

Next, as shown in FIG. 7, a heat treatment, such as a rapid thermal annealing process (RTA), is performed to heat the semiconductor substrate 100 to about 200 to 400 °C. While the heating step is being performed, any of the gate 104 and source/drain regions 112 that are in contact with the metal layer 114 will react and form a deuterated metal layer 118. Then after the rapid temperature annealing treatment, the typical wet is used. An etching solution such as ammonia water, hydrogen peroxide, hydrochloric acid, sulfuric acid, nitric acid, and acetic acid is etched to perform an etching step for removing the unreacted metal layer 114 and the capping layer 116. Thus, a preferred embodiment of the present invention has been completed to fabricate a MOS transistor crystal structure having a deuterated metal layer.

It should be noted that the above-mentioned fluorine-containing plasma treatment step, the sputtering step of the metal layer 114, the sputtering step of the mask layer 116, and the heat treatment step can be performed in different processing chambers of the same cluster, that is, in the case of These three steps can be completed under vacuum, thus reducing the chance of the substrate being exposed to external dirt and moisture.

It should be noted that the above embodiment is exemplified by forming a vaporized metal directly on the fluorine-containing interface layer 122 after the fluorine-containing interface layer 122 is formed. In other words, the above embodiment does not perform any additional process between forming the fluorine-containing interface layer 122 and subsequent metal layer deposition. However, the present invention is not limited to this method. In the present invention, after the fluorine-containing interface layer 122 is formed, a heating process such as hot plate heating, lamp heating, or a heating process using other heating elements may be performed, and the fluorine is used at a high temperature. The fluorine atoms in the interface layer 122 are driven-in the semiconductor substrate 100, and the position of the fluorine atoms is directly adjusted by the driving action, and then the desired deuterated metal layer deposition and another rapid temperature annealing are performed. The process, the process method and the sequence are all covered by the present invention. It should be noted that the above-described fluorine-containing plasma treatment step, the heating step after formation of the fluorine-containing interface layer, the sputtering step of the metal layer 114, and the hiding layer The sputtering step and the rapid temperature increasing step of 116 can be performed in different processing chambers of the same cluster, that is, the three steps can be completed without breaking the vacuum, thereby reducing the exposure of the substrate to the external environment. The opportunity of pollution and moisture. In addition, the thickness of the fluorine-containing interface layer 122 and the fluorine atom content driven into the semiconductor substrate 100 are also adjusted along with the thickness of the oxide layer 120. For example, as the thickness of the additional oxide layer 120 increases, the thickness of the subsequently formed fluorine-containing interface layer 122 also increases. When the thickness of the fluorine-containing interface layer 122 is increased, the fluorine atom content that can be driven into the semiconductor substrate 100 is also increased.

In summary, the present invention mainly removes the native oxide on the surface of the semiconductor substrate by a cleaning step before performing the metal telluride process, and then performs an oxidation process to form an oxide layer on the surface of the semiconductor substrate. The oxide layer is then subjected to a plasma treatment to convert the oxide layer into a fluorine-containing interface layer, followed by a subsequent metal halide process. Since the fluorine atom in the fluorine-containing interface layer can make the deuterated metal not too close to the channel region when the deuterated metal reacts, and at the same time protect the deuterated metal layer from the high temperature of the deionized water, the present invention can thereby pass through the fluorine-containing interfacial layer To effectively improve the situation in which the lead metal or the agglomeration is prone to occur in the process of deuterated metal.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

60‧‧‧Semiconductor substrate

62‧‧‧ gate dielectric layer

64‧‧‧ gate conductive layer

66‧‧‧ gate structure

67‧‧‧ liner

68‧‧‧ Sidewall

70‧‧‧Lightly doped source/drain

72‧‧‧Source/bungee area

74‧‧‧metal layer

76‧‧‧Deuterated metal layer

100‧‧‧Semiconductor substrate

102‧‧‧ gate dielectric layer

104‧‧‧ gate conductive layer

106‧‧‧ gate structure

107‧‧‧ liner

108‧‧‧ Sidewall

110‧‧‧Lightly doped source/dip

112‧‧‧Source/bungee area

114‧‧‧metal layer

116‧‧‧ Covering layer

118‧‧‧Deuterated metal layer

120‧‧‧Oxide layer

122‧‧‧Fluidated interface layer

124‧‧‧Top protective layer

Fig. 1 and Fig. 2 are schematic views showing the process of fabricating a MOS transistor.

3 to 7 are schematic views showing a process for fabricating a MOS transistor according to a preferred embodiment of the present invention.

100‧‧‧Semiconductor substrate

102‧‧‧ gate dielectric layer

104‧‧‧ gate

106‧‧‧ gate structure

107‧‧‧ liner

108‧‧‧ Sidewall

110‧‧‧Lightly doped bungee

112‧‧‧Source/bungee area

118‧‧‧Deuterated metal layer

122‧‧‧Fluidated interface layer

Claims (14)

A method of fabricating a MOS transistor, comprising: providing a semiconductor substrate having a gate structure having a gate dielectric layer and a gate conductive layer; forming a source/drain region In the semiconductor substrate; performing a cleaning step to remove oxides on the surface of the semiconductor substrate; performing an oxidation process on the surface of the semiconductor substrate with an oxidizing agent to form an oxide layer on the surface of the semiconductor substrate; after forming the oxide layer Forming a fluorine-containing interfacial layer by reacting a fluorine-containing plasma with the oxide layer; depositing a metal layer on the semiconductor substrate; and subjecting the semiconductor substrate to a heat treatment to form a deuterated metal layer. The method of claim 1, wherein the gate structure further comprises a sidewall disposed around the gate conductive layer. The method of claim 1, wherein the washing step is carried out using hydrogen fluoride (HF). The method of claim 1, wherein the oxidizing agent comprises a mixture of ammonia water and hydrogen peroxide (APM) or hydrogen peroxide (H ₂ O ₂ ). The method of claim 1, wherein the oxide layer is thick The degree is between 5 angstroms and 20 angstroms. The method of claim 1, wherein the reaction gas of the fluorine-containing plasma comprises nitrogen trifluoride (NF ₃ ) and ammonia (NH ₃ ). The method of claim 1, wherein the metal layer comprises tungsten, cobalt, titanium, nickel, platinum, palladium, molybdenum or an alloy of the above metals. The method of claim 1, wherein the forming of the fluorine-containing interface layer and before depositing the metal layer further comprises performing a heating process. The method of claim 1, wherein the heat treatment for forming the deuterated metal layer is a rapid temperature annealing treatment. The method of claim 1, wherein the step of forming the source/drain further comprises an implanting step. The method of claim 1, wherein the step of forming the source/drain further comprises: forming a groove on both sides of the gate structure; and filling the groove with a material. The method of claim 11, wherein the filling step further comprises epitaxially growing the material by doping the dopant in the field. The method of claim 11, wherein the filling step further comprises: epitaxially growing the material; and implanting the dopant. The method of claim 1, wherein the cleaning step further comprises completely or partially removing the oxide.