KR100613585B1 - Method For Manufacturing Semiconductor Devices - Google Patents

Abstract

In the method of manufacturing a semiconductor device of the present invention, a gate electrode is formed in the active region of the semiconductor substrate through a gate insulating film, a spacer is formed on the sidewall of the gate electrode, and the active region of the semiconductor substrate is centered on the gate electrode. Si ions are implanted into the gate electrode and the source / drain region as amorphous ions while the source / drain region having the LED region is formed, and the gate electrode and the source / drain region are included in the entire region of the semiconductor substrate. Forming a Ti / TiN layer, implanting fluorine (F) ions into the Ti / TiN layer, and performing a silicide reaction on the Ti / TiN layer by a heat treatment process, thereby forming titanium silicide in the gate electrode and the source / drain region. Form a layer.

Therefore, the present invention can reduce the resistance of the titanium silicide layer. In addition, since the thermal stability of the titanium silicide layer is improved, the resistance of the titanium silicide layer may be uniform, and agglomeration of the titanium silicide layer may be suppressed.

Silicide layer, amorphous ion, resistance, thermal stability, grain boundary size

Description

Method for manufacturing semiconductor device {Method For Manufacturing Semiconductor Devices}             

1 is a cross-sectional view showing the structure of a semiconductor device according to the prior art.

2A to 2E are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3D are cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the resistance of the titanium silicide layer on the gate electrode and the source / drain regions is reduced and uniformized.

In general, as the integration of semiconductor devices increases, the miniaturization of the semiconductor devices intensifies, and therefore, the MOS transistors for the semiconductor devices are also miniaturized. That is, the size of the source / drain, gate electrode, wiring, etc. of the MOS transistor is reduced. In addition, the size of the contact hole for the electrical connection between the source / drain and the wiring or the contact hole for the electrical connection between the gate electrode and the wiring is also reduced. Therefore, the sheet resistance of the gate electrode increases and the contact resistance of the contact hole increases, thereby delaying the electrical signal transmission of the MOS transistor and further lowering the operating speed of the semiconductor device.

Nevertheless, as the demand for higher speed of the semiconductor device is gradually increased, methods for reducing the contact resistance have been proposed to satisfy this demand. Among these methods, a method of forming a silicide layer having a low specific resistance on the source / drain of the contact hole is widely used. In the initial silicide process, since the silicide layer is formed on the gate electrode and the source / drain in separate steps, the manufacturing process is complicated and the manufacturing cost is high.

Recently, in order to simplify the silicide process and reduce the manufacturing cost, a salicide (Salicide: Self Aligned Silicide) process has been introduced. The salicide process simultaneously forms the silicide layer on the gate electrode and the source / drain by one same process. That is, in the salicide process, when the high melting point metal layer is laminated on the single crystal silicon, the polycrystalline silicon, and the insulating film at the same time, and the heat treatment is performed, the high melting point metal layer on the single crystal silicon and the polycrystalline silicon is silicided into a silicide layer. The high melting point metal on the insulating film is not silicided and remains as it is. Thereafter, the silicide layer may be left only on the single crystal silicon and the polycrystalline silicon by removing the non-silicided high melting point metal by an etching process.

In the salicide process, a titanium salicide process or a cobalt salicide process having good electrical resistance of a metal and a silicide layer are widely used in a semiconductor device manufacturing process.

1 is a cross-sectional structural view showing a semiconductor device according to the prior art. As shown in FIG. 1, in the conventional semiconductor device, an isolation layer 11 is formed in a field region of the semiconductor substrate 10 to define an active region of the semiconductor substrate 10, and the semiconductor substrate 10 is formed. A pattern of the gate electrode 15 is formed on the active region of the gate electrode 13, a spacer 17 is formed on the sidewall of the gate electrode 15, and an active region of the semiconductor substrate 10. A source / drain region S / D having a lightly doped drain (LDD) region is formed in the substrate. In addition, titanium silicide layers 21 and 23, such as TiSi ₂ , are formed in the source / drain regions S / D and the gate electrode 15, respectively.

However, in the related art, a high melting point metal layer (not shown), a gate electrode 15, and a source / drain region S / D for forming the titanium silicide layers 21 and 23 are not amorphous. By forming the titanium silicide layers 21 and 23, the grain boundary size of the metal layer, the gate electrode 15, and the source / drain regions S / D is increased, and the titanium silicide layers 21 and 23 are formed. ) Resistance increases.

In addition, since the thermal stability of the titanium silicide layers 21 and 23 is lowered, the resistance of the titanium silicide layers 21 and 23 is uneven, and the titanium silicide layers 21 and 23 are reduced. ) Agglomeration occurs.

Therefore, the contact resistance of the source / drain regions S / D increases and the surface resistance of the gate electrode 15 increases, thereby lowering the operating speed of the semiconductor device.

Accordingly, an object of the present invention is to reduce the resistance of the titanium silicide layer to reduce the contact resistance of the source / drain regions and the surface resistance of the gate electrode.

Another object of the present invention is to equalize the resistance of the titanium silicide layer and to suppress the aggregation of the titanium silicide layer by improving the thermal stability of the titanium silicide layer.

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Therefore, the present invention can reduce the grain size of the polycrystalline silicon layer of the gate electrode, thereby reducing the surface resistance and the contact resistance of the gate electrode.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part which has the same structure and the same action as the conventional part.

2A to 2E are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, first, a semiconductor substrate 10, for example, a first conductivity type single crystal silicon substrate, is prepared. Here, the p-type or n-type can be used as the first conductivity type, but for convenience of description, the semiconductor substrate 10 will be described based on the case where the p-type.

Subsequently, the device isolation layer 11 is formed in the field region of the semiconductor substrate 10 to define an active region of the semiconductor substrate 10. In this case, the device isolation layer 11 is formed by a shallow trench isolation (STI) process. Although not shown in the drawings, the device isolation film of the semiconductor substrate 10 may be formed by a local oxidation of silicon (LOCOS) process or the like.

Thereafter, a gate insulating layer 13 is formed on the active region of the semiconductor substrate 10 to a desired thickness, and a conductive layer for the gate electrode 15, for example, an impurity is doped on the gate insulating layer 13. A polycrystalline silicon layer is formed to a desired thickness. Subsequently, the gate electrode forming region of the active region of the semiconductor substrate 10 is removed by removing the polycrystalline silicon layer and the gate insulating layer 13 outside the gate electrode forming region of the active region of the semiconductor substrate 10 using a photolithography process. A gate electrode 15 and a gate insulating film 13 made of the polycrystalline silicon layer are formed on the gate electrode 15.

Thereafter, ion-implanted impurities, such as n-type impurities, are implanted at low concentration into the active region of the semiconductor substrate 10 using the gate electrode 15 as an ion implantation mask layer.

Subsequently, an insulating film, for example, a nitride film is deposited on the entirety of the semiconductor substrate 10 including the gate electrode 15 using, for example, a chemical vapor deposition process. Subsequently, the insulating layer is processed using, for example, an etch back process to form spacers 17 formed of the nitride layer on both left and right side walls of the gate electrode 15. The upper surface of 15 and the surface of the active region outside the gate electrode 15 are exposed.

Then, using the gate electrode 15 and the spacer 33 as an ion implantation mask layer, the source / drain region forming impurities in the active region of the semiconductor substrate 10, for example n-type impurities, are ionized at high concentration. Inject.

Subsequently, a source / drain region (S / D) having an LED region spaced apart from the gate electrode 15 in the active region of the semiconductor substrate 10 by diffusing the ion implanted impurities using a heat treatment process. ) To form a junction.

Referring to FIG. 2B, a high melting point metal layer, eg Ti, for a titanium silicide layer over the entire surface of the semiconductor substrate 10, including the gate electrode 15, for example using a sputtering process The / TiN layer 30 is laminated.

At this time, the Ti layer 31 and the TiN layer 33 of the Ti / TiN layer 30 are formed to a thickness of 100 ~ 500Å respectively.

Referring to FIG. 2C, thereafter, amorphous ions for amorphousizing the Ti / TiN layer 30, the gate electrode 15, and the source / drain region S / D of the semiconductor substrate 10 will be described. For example, SiF ₃ ions 35 are implanted at an energy of 50 to 150 KeV and a concentration of 1E14 to 5E14 ions / cm ² . In this case, an ion implantation layer of the SiF ₃ ions 35 is formed near the surface of the source / drain region S / D and the gate electrode 15.

Accordingly, the Ti / TiN layer 30, the gate electrode 15, and the source / drain region S / D are amorphous to form the Ti / TiN layer 30, the gate electrode 15, and the source / drain. The grain boundary size of the region S / D may be reduced compared to before the ion implantation of the SiF ₃ ions 35.

Referring to FIG. 2D, the source / drain region S / D and the gate are then silicided by the Ti / TiN layer 30 of FIG. 2C using a first heat treatment process, for example, a rapid heat treatment process. Titanium silicide layers 41 and 43 such as TiSi ₂ in the C-49 state are formed on the electrode 15. At this time, the rapid heat treatment process is performed for 10 to 60 seconds in a temperature of 600 ~ 800 ℃ and nitrogen (N ₂ ) gas.

Subsequently, the source / drain region S / D and the gate electrode 15 may be removed by, for example, removing all of the unreacted Ti / TiN layer 30 that has not been silicided using a wet etching process. The titanium silicide layers 41 and 43 remain on. In this case, the wet etching process uses an etchant obtained by mixing H ₂ O, H ₂ O _2, and NH ₄ OH in a ratio of 5: 1: 1.

Referring to FIG. 2E, a titanium silicide such as TiSi _{2 in} a C-54 state is then thermally treated by the _second silicidation process, for example, by rapid thermal annealing. Phase transition to layers 45 and 47. At this time, the rapid heat treatment process is carried out in a temperature of 650 ~ 850 ℃ and nitrogen (N ₂ ) gas for 10 to 60 seconds.

Therefore, since the titanium silicide layers 45 and 47 are formed on the amorphous source / drain regions S / D and the gate electrode 15, grain boundaries of the titanium silicide layers 45 and 47 are formed. The size can be reduced compared to the conventional non-implantation of the SiF ₃ ions 35, and further the resistance of the titanium silicide layers 45, 47 can be reduced. In addition, the Florin (F) ions of the SiF ₃ ions 35 lower the silicidation reaction rate of the titanium silicide layers 45 and 47 to improve thermal stability of the titanium silicide layers 45 and 47. As a result, the resistance of the titanium silicide layers 45 and 47 can be made uniform, and the agglomeration of the titanium silicide layers 45 and 47 can be suppressed.

Therefore, the present invention can reduce the contact resistance of the source / drain regions S / D and the surface resistance of the gate electrode, thereby improving the operation speed of the semiconductor device.

Subsequently, although not shown in the drawings, an interlayer insulating film is formed on the semiconductor substrate using a conventional process, and contact holes of the gate electrode and the source / drain are formed in the interlayer insulating film, respectively, and together with the inside of the contact hole. A barrier metal layer is laminated on the interlayer insulating film, and a conductive layer such as, for example, a tungsten layer is laminated on the barrier metal layer to fill the contact hole, and the tungsten layer is left only in the contact hole by a planarization process. The manufacturing process of the semiconductor device of the present invention is completed by forming a conductive line on the interlayer insulating film so as to be electrically connected to the tungsten layer of the contact hole.

3A to 3E are cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. The same reference numerals are given to parts having the same configuration and the same operation as those of the embodiment of the present invention.

Referring to FIG. 3A, the trenches 11 are formed in the field region of the semiconductor substrate 10 and the device isolation layer 11 is formed in the trenches 11 by performing the same procedure as in FIG. 2A. The gate electrode 15 is formed through the gate insulating layer 13 in the active region of the semiconductor substrate 10, and the LED region is formed in the active region of the semiconductor substrate 10 with the gate electrode 15 interposed therebetween. And a spacer 17 on sidewalls of the gate electrode 15, and source / drain regions in the active region of the semiconductor substrate 10 with the gate electrode 15 and the spacer 17 therebetween. (S / D) is formed.

Then, near the surface of the source drain region S / D and the gate electrode 15, amorphous ions, for example, Si ions 51, have an energy of 10 to 60 KeV and a concentration of 1E13 to 3E14 ions / cm ² . The source drain region S / D and the gate electrode 15 are amorphous by ion implantation. In this case, an ion implantation layer of the Si ions 51 is formed near the surface of the source / drain region S / D and the gate electrode 15.

Accordingly, the Ti / TiN layer 30, the gate electrode 15, and the source / drain region S / D are amorphous to form the Ti / TiN layer 30, the gate electrode 15, and the source / drain. The grain boundary size of the region S / D can be reduced compared to before the ion implantation of the Si ions 51.

Referring to FIG. 3B, a high melting point metal layer for the titanium silicide layer, for example, Ti / The TiN layer 30 is laminated. At this time, the Ti layer 31 and the TiN layer 33 of the Ti / TiN layer 30 are formed to a thickness of 100 ~ 500Å respectively.

Next, Florin (F) ions are implanted into the Ti / TiN layer 30 at an energy of 10 to 50 KeV and a concentration of 5E14 to 1E15 ions / cm ² . In this case, the ion implantation layer of the florin (F) ions is formed in the Ti layer 31.

Referring to FIG. 3C, a titanium silicide layer 61 such as TiSi ₂ in a C-49 state on the source / drain region S / D and the gate electrode 15 may be subsequently performed by performing the same process of FIG. 2D. And (63).

Referring to Figure 3d, then, even in the titanium silicide layer 61, a (63) C-54 status as by a TiSi ₂ of the C-49 form shown in Figure 3c equally subjected to 2e process of TiSi ₂ The phase change to titanium silicide layer 65, 67 as shown.

Accordingly, since the titanium silicide layers 65 and 67 are formed on the amorphous source / drain regions S / D and the gate electrode 15, grain boundaries of the titanium silicide layers 65 and 67 are formed. The size can be reduced compared to before the ion implantation of the Si ions 51 and further, the resistance of the titanium silicide layers 65 and 67 can be reduced. In addition, since the florin (F) ion 53 improves the thermal stability of the titanium silicide layers 65 and 67 by lowering the silicideation reaction rate of the titanium silicide layers 65 and 67, the titanium The resistance of the silicide layers 65 and 67 can be made uniform, and the agglomeration of the titanium silicide layers 65 and 67 can be suppressed.

Therefore, the present invention can reduce the contact resistance of the source / drain regions S / D and the surface resistance of the gate electrode, thereby improving the operation speed of the semiconductor device.

Subsequently, although not shown in the drawings, an interlayer insulating film is formed on the semiconductor substrate using a conventional process, and contact holes of the gate electrode and the source / drain are formed in the interlayer insulating film, respectively, and together with the inside of the contact hole. A barrier metal layer is laminated on the interlayer insulating film, and a conductive layer such as, for example, a tungsten layer is laminated on the barrier metal layer to fill the contact hole, and the tungsten layer is left only in the contact hole by a planarization process. The manufacturing process of the semiconductor device of the present invention is completed by forming a conductive line on the interlayer insulating film so as to be electrically connected to the tungsten layer of the contact hole.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed in an active region of a semiconductor substrate through a gate insulating film, a spacer is formed on sidewalls of the gate electrode, and the gate electrode is centered. Si ions are implanted into the gate electrode and the source / drain region as amorphous ions in a state where a source / drain region having an LED region is formed in an active region of the semiconductor substrate, and includes the gate electrode and the source / drain region. Forming a Ti / TiN layer over the entire semiconductor substrate, implanting fluorine (F) ions into the Ti / TiN layer, and performing a silicide reaction on the Ti / TiN layer by a heat treatment process. A titanium silicide layer is formed in the source / drain regions.

Therefore, the present invention can reduce the resistance of the titanium silicide layer. In addition, since the thermal stability of the titanium silicide layer is improved, the resistance of the titanium silicide layer may be uniform, and agglomeration of the titanium silicide layer may be suppressed.

Therefore, the present invention can reduce the contact resistance of the source / drain regions S / D and the surface resistance of the gate electrode, thereby improving the operation speed of the semiconductor device.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (9)

Forming a source / drain region centering the gate electrode of the polycrystalline silicon layer on the active region of the semiconductor substrate; Depositing an arbitrary metal layer over the entirety of the semiconductor substrate including the gate electrode and source / drain regions; Implanting amorphous ions into the gate electrode and the source / drain region to amorphous the gate electrode and the source / drain region; And Forming a silicide layer on the source / drain region and the gate electrode by suicided the metal layer. The method for manufacturing a semiconductor device according to claim 1, wherein ion implantation of SiF ₃ ions as the amorphous ions is carried out. The method of claim 2, wherein the SiF ₃ ions are implanted at an energy of 50 to 150 KeV and at a concentration of 1E14 to 5E14 ions / cm ² . The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the metal layer is formed of a Ti / TiN layer. Forming a source / drain region centering the gate electrode of the polycrystalline silicon layer on the active region of the semiconductor substrate; Implanting amorphous ions into the gate electrode and the source / drain region to amorphous the gate electrode and the source / drain region; Depositing an arbitrary metal layer over the entirety of the semiconductor substrate including the gate electrode and source / drain regions; Implanting fluorine (F) ions into the metal layer; And Silicideing the metal layer to form a silicide layer on the source / drain regions and the gate electrode, And said florin ions improve the thermal stability of said silicide layer. The method for manufacturing a semiconductor device according to claim 5, wherein ion implantation of Si ions is carried out as the amorphous ions. The method of manufacturing a semiconductor device according to claim 6, wherein the Si ions are implanted at an energy of 10 to 60 KeV and a concentration of 1E13 to 3E14 ions / cm ² . The method of manufacturing a semiconductor device according to claim 5, wherein the fluorine (F) ions are implanted at an energy of 10 to 50 KeV and a concentration of 5E14 to 1E15 ions / cm ² . The method for manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the metal layer is formed of a Ti / TiN layer.

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