JPS626664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate type semiconductor device, and for example, in a MOS type semiconductor integrated circuit, when the gate length is 5 μm or less, the present invention relates to a method for manufacturing an insulated gate type semiconductor device.
The present invention provides a suitable manufacturing method for MOS type integrated circuits. Furthermore, in the manufacture of MOS transistors with minute dimensions, improvements in photomask accuracy and overlay accuracy are required, but the present invention introduces a self-alignment process to improve the process that requires high-precision mask alignment. The aim is to reduce

In recent years, there has been a demand for high-density MOS type integrated circuits called VLSIs, and the dimensions of the MOS type transistors that are the constituent elements are also becoming extremely miniaturized. On the other hand, in MOS transistors, as the gate length becomes shorter, the contribution of the drain depletion layer charge to the gate charge increases, resulting in a decrease in the threshold voltage (called Vt) and deterioration of the source-drain breakdown voltage. Problems arise. The present invention forms a region with a shallow diffusion depth (referred to as The present invention provides a method for manufacturing high-density MOS integrated circuits that alleviates the strict requirements for alignment accuracy.

First, MOS, which is a component of MOS integrated circuits,
An example of a conventional method for manufacturing a type transistor will be described. FIG. 1 describes an N-channel type, which is the most common manufacturing example. A field oxide film 2 is formed on a P-type silicon substrate 1 to a thickness of about 1 μm by thermal oxidation. Next, an opening is made in the oxide film 2 in a region where a transistor is to be formed, and a gate oxide film 3 is formed to a thickness of about 1000 Å. Furthermore, polycrystalline silicon 4 is placed on top of this.
It is deposited to a thickness of about 6000 Å using SiH ₄ thermal decomposition method. This state is shown in FIG. 1A.

Next, using a photoresist, the polycrystalline silicon is removed by etching except for the gate region 4a and wiring region 4b. Next, the gate oxide film is etched using the gate 4a as a mask to form a gate oxide film 3a, and then phosphorus is diffused to a depth of about 1 μm to form the source/drain regions 5.
form. At this time, polycrystalline silicon 4
Phosphorus is also diffused into a and 4b. This state is shown in B.

Next, a silicon oxide film 6 is formed on the entire surface to a thickness of about 5000 Å using the CVD method as an insulating layer, and a contact area is opened using a photoresist. This state is shown in C.

Next, an Al film 7 for wiring is deposited to a thickness of about 8000 Å by vacuum evaporation, and a wiring pattern is formed using a photoresist to complete the process. This state is shown in D.

Conventional MOS type transistors are manufactured through the above-described steps, but as integration becomes higher and the dimensions of transistors become smaller, various problems arise with this structure. The most notable of these is the decrease in threshold voltage Vt. When the effective gate length of a transistor becomes 4 μm or less (hereinafter referred to as short channel), as shown in Figure 2,
For example, it is stated in (Masuda Gato, Proceedings of the 23rd Japan Society of Applied Physics, p. 342) that Vt decreases rapidly.

This tendency becomes more pronounced as the source/drain diffusion depth increases. Therefore, for short channel transistors, it is necessary to keep the diffusion depth to about 0.3 microns. However, since an aluminum-silicon alloy layer is formed in the contact region of the Al wiring, a thin diffusion layer may cause Al to penetrate toward the substrate during recrystallization, causing a problem. For this reason, in short channel transistors, Figure 3A
The structure shown in is adopted. That is, the structure is such that the source/drain diffusion layer is divided into two regions 5 and 5a, and the contact portion is deep and the side of the gate is shallow. Usually 5 is 1-1.5 μm, 5a is
The depth is approximately 0.3 μm. The steps to realize this structure are as follows. First, a field oxide film 2 with a thickness of about 1 μm is formed on a P-type substrate 1 by thermal oxidation, and then, using photoresist, areas corresponding to 5 and 5a are opened, and then phosphorus is removed by about 1 μm. Diffuses to a depth of 1 μm. Next, the oxide film in the area where the transistor is to be formed is photo-photographed.
After creating an opening using a resist, a gate oxide film 3 is formed to a thickness of approximately 1000 Å by thermal oxidation, and polycrystalline silicon is further deposited on top of this to a thickness of approximately 6000 Å.
Precipitated by thermal decomposition of SiH ₄ . Next, using photoresist again, gate 4a is formed,
Apply phosphorus to the entire surface at an accelerating voltage of about 60KV, 1~2×
Ions are implanted to a concentration of 10 ¹⁵ cm ^-2 . Since field oxide film 2 and silicon gate 4a are thick, phosphorus is not implanted directly beneath them, but only into region 5 of the thin gate oxide film. After this, heat treatment is performed for activation, and the diffusion layer 5a of approximately 0.3 μm is formed.
is formed. This is shown in Figure 3B. Thereafter, a transistor is formed in the same manner as the process shown in FIG.

In addition, as a method to prevent deterioration of transistor characteristics due to short channels, for example,
No. 93779 and Japanese Unexamined Patent Publication No. 50-8484 have the following proposal. This structure is shown in FIG. In FIG. 4, 1 is a P-type silicon substrate, 2 is a field oxide film, 10 is an N-type diffusion layer, 11 is a gate oxide film, 1
2 is polycrystalline silicon for gate, 13, 14, 15
is Al for wiring. As can be seen from the figure, the feature of this structure is that the gate polycrystalline silicon 12 is buried in the substrate 1, and the channel region is located closer to the inside of the substrate than the diffusion layer 10. This is considered to be as if the diffusion depth Xj had become negative (Xj negative) when compared with the normal structure. This alleviates the drawbacks of short channels.

However, the structures shown in Figures 3 and 4 are
This is not necessarily an appropriate structure from the viewpoint of miniaturization of transistor dimensions and thorough self-alignment structure in order to increase integration density. For example, since the openings in the oxide film for taking out the electrodes 13 and 15 are not self-aligned, a margin is required, and even if this margin is 2 μm and the opening is 2 μm, the width of the diffusion layer 10 must be at least 6 μm, which requires mask alignment accuracy. It is difficult to reduce the thickness to 5 μm or less unless the conditions are extremely severe. Furthermore, the same applies to the contact of the gate electrode 14. In addition, in these structures, since the opening is made through a thick oxide film, the surface is quite uneven, and there remains a problem in routing an Al wiring having a width of 3 to 4 μm. That is, this is one of the causes of defects such as breakage and shorting.

The present invention takes the above-mentioned problems into full consideration and provides a new manufacturing method that can improve the integration density. The present invention will be explained in detail below.

Figure 5 shows a MOS type IC according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process. The process will be explained according to the diagram.

First, a silicon nitride film 22 having antioxidation ability is selectively formed on a silicon substrate 21 of a first conductivity type, for example, a P type, and a region 23 that will become a field region is formed.
A first conductivity type impurity is introduced to serve as a channel stopper. Next, regions 24 and 25 that become part of the source and drain have a second conductivity type, that is, N
Introducing type impurities. This state is shown in FIG. 5A.

Next, the substrate 21 is oxidized using the nitride film 22 as a mask to selectively form an oxide film 26, and then the nitride film 22 is removed (FIG. 5B). At this time, each impurity, like B, is diffused under the oxide film 26. Next, only the exposed silicon surface is etched from the surface using plasma etching or the like using the oxide film 26 as a mask to form recesses 27, 28, and 29. The etching depth in this case is the oxide film 2 formed.
Make the depth so that the silicon surface is at the bottom from 6.

Through the above steps, the locations of the source and drain contacts are determined in a self-aligned manner by forming the recesses, and no mask alignment step is required. That is,
After forming the nitride film 22, the field oxide film 26, source and drain regions, and recesses are formed according to the pattern of this nitride film, eliminating the need for precise mask alignment.

Next, a gate oxide film 29 is formed on the surface of the recess.
The appropriate thickness is 800 to 1200 Å. Then, the gate oxide film in the regions that will become source/drain contacts, that is, the recesses 27 and 29, is etched to form a gate oxide film 29 only in the recesses 28 for gate formation.
(Figure 5C).

Next, the polycrystalline silicon 30, 31, 32 is deposited on the concave portions 27, 28, 2 of the gate, source, and drain regions.
9, impurities of the second conductivity type are introduced into this polycrystalline silicon, and heat treatment is performed. Through this process,
Each polycrystalline silicon becomes conductive, and a gate electrode 31, a source contact electrode 30, and a drain contact electrode 32 of a MOS transistor are embedded therein. At the same time, N-type impurities are formed in the substrate, and source and drain contact regions 34, 3
5 is formed. 24 and 25 are source and drain regions (FIG. 5D).

In this step, polycrystalline silicon 30,3
1 and 32 can also be embedded in the recess in a self-aligned manner. That is, when polycrystalline silicon is formed over the entire surface, the surface becomes uneven. A photoresist (not shown) is applied thereon so that the surface is flat, and the photoresist is etched over the entire surface, leaving the photoresist selectively only on the recesses. Therefore, by etching the polycrystalline silicon using the remaining resist, the recesses 27, 28, 2 are etched.
9 can be easily formed with polycrystalline silicon 30, 31, and 32.

After that, the oxide film 36 that will become the insulating layer is formed by CVD.
A wiring 37 made of aluminum is formed by opening only the portion necessary for the wiring by etching (FIG. 5E). Note that in this case as well, since the polycrystalline silicon 30, 31, and 32 are embedded in the recess, the opening of the oxide film 36 may be shifted.
This is also advantageous in that it does not require precise mask alignment.

According to the method of FIG. 5, the relative depth of the diffusion layer is determined by etching.

As described above, according to the present invention: (1) Since the relative depth of the diffusion layer is determined by etching, the short channel effect caused by movement of the diffusion layer due to heat treatment can be prevented. This effect is particularly remarkable in the case of a MOSTr with a gate length of 5 μm or less.

(2) There are relatively many self-alignment steps, there is little need for precise mask alignment, and it is possible to easily form fine patterns.

(3) Since the surface is flat, defects such as breakage can be prevented.

The present invention greatly contributes to the production of high-density integrated circuits.

[Brief explanation of the drawing]

Figures 1A to 1D are manufacturing process diagrams of typical conventional silicon gate MOS transistors, Figure 2 is a curve diagram showing an example of Vt reduction due to shortening of the channel length in a conventional transistor, and Figure 3A. ,B
4 is a diagram of the formation process of a MOS transistor to prevent the short channel effect, FIG. 4 is a structural diagram of another conventional MOS transistor to prevent the short channel effect, and FIGS. 5A to 5E are one embodiment of the present invention. FIG. 3 is a manufacturing process diagram of a MOS transistor according to an example. 21... P-type silicon substrate, 22... silicon nitride film, 24, 25... source/drain region,
26... Oxide film, 27, 28, 29... Concave portion, 2
9... Gate oxide film, 30, 31, 32... Polycrystalline silicon, 36... Oxide film, 37... Wiring.

Claims (1)

[Claims] 1. A source of a semiconductor substrate with a flat surface of one conductivity type,
selectively forming an anti-oxidation film in the drain and gate formation regions; and flattening the surface of the semiconductor substrate in the substrate region sandwiched between the gate formation region and the source and drain formation regions. a step of introducing an impurity of a conductivity type opposite to that of the substrate while the semiconductor substrate is in the same state; a step of selectively oxidizing the semiconductor substrate using the anti-oxidation film as a mask to form an oxide film; and a step of forming an oxide film using the oxide film as a mask. The method includes a step of etching the surface to form a recess, a step of forming a gate insulating film in the recess for forming a gate, and a step of filling the recess with a polycrystalline semiconductor material to flatten the entire surface. A method of manufacturing an insulated gate semiconductor device, characterized in that: