JPS60189267A - Manufacture of mis field effect transistor - Google Patents

Abstract

PURPOSE:To check generation of a short channel effect without depending upon a complicated process, and moreover, to reduce formation of hot carriers at manufacture of an MIS field effect transistor by a method wherein a process to perform ion implantation specifying phosphorus and using a gate electrode as a mask, a process to perform the specified heat treatment are provided, or a process to provide an interlayer insulating film, a process to provide an opening, and a process to perform ion implantation are provided between the processes thereof. CONSTITUTION:Selective oxidation is performed on a P type silicon single crystal substrate 1 using a buffer oxide film and a nitride film as masks to provide element isolating oxide films 2. Then a gate oxide film 3 is formed in an element region, and impurity ions 4 are implanted to control the threshold voltage. Then a gate electrode 6 is formed, and to form source junction and drain junction, phosphorus ion implantation 5 is performed by the dose of 1X10<15>cm<-2> or more and 1X10<16>cm<-2> or less, and moreover at energy of 50keV or less. Then PSG is grown on the surface as an interlayer insulating film 7. Then heat treatment is performed for the hour of 30sec or less at the temperature of 900 deg.C or more and 1,100 deg.C or less using a halogen lamp annealer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing an MIS field effect transistor, and more particularly to a method for manufacturing an MIS field effect transistor having a short channel and a shallow junction.

(Prior Art) Conventionally, to form source and drain junctions of an n-channel MIS field effect transistor, a process has been used in which ions of arsenic or phosphorus are implanted as impurities, followed by heat treatment at a high temperature for several minutes to several tens of minutes. Therefore, when all phosphorus is used as an impurity, the diffusion coefficient of phosphorus is large, so the above FET
This has the disadvantage that the junction becomes deeper and a short channel effect occurs.

In addition, when arsenic is used as an impurity, the diffusion coefficient of arsenic is smaller than that of phosphorus, so the junction can be made shallow, but the impurity concentration distribution is step-like because the diffusion coefficient is dependent on the However, there is a drawback that electric field concentration occurs near the junction of the FET, resulting in increased generation of hot carriers.

Conventional methods for manufacturing MIS field effect transistors that alleviate the above-mentioned electric field concentration include doping with arsenic and doping with low-concentration phosphorus, but the process is complicated and the desired structure cannot be achieved. The drawback is that two types of doping must be done with sufficient precision in order to obtain
Furthermore, there is a fear that a shallow junction cannot be obtained and the short channel effect cannot be suppressed.

(Objective of the Invention) An object of the present invention is to provide a method for manufacturing an n-channel MIS type field effect transistor that completely prevents short channel effects from occurring and generates fewer hot carriers without using complicated processes. be.

(Structure of the Invention) A method for manufacturing an MIS field effect transistor according to the first uninvented invention is to form the source and drain regions of an n-channel MIS field effect transistor with a gate electrode length of 15 μm or less on a p-type silicon single crystal substrate. When forming the substrate on the surface, phosphorus is applied to the substrate using the gate electrode as a mask.
A step of implanting ions with an energy of 50 KeV or less at a dose of Xl0 cm or more and 1x1016C1n-2 or less, and a step of ion implantation with an energy of 900'O or more and 1.10-0° after the ion implantation.
It is constructed by having a step of performing the entire heat treatment at a temperature of 0 or less for a time of 30 seconds or less.

In addition, the method for manufacturing an MIS type field effect transistor according to the second uninvented invention is such that the source and drain regions of an n-channel MIS type field effect transistor having a gate electrode length of 15 μm or less are formed on the entire surface of a kp type silicon single crystal substrate. In this case, using the gate electrode as a mask, phosphorus is applied to the substrate at an amount of Ix 1015 cm-2 or more IX 1016 Crn
A step of implanting ions at a dose of -2 or less and an energy of 50 KeV or less, a step of providing an interlayer insulating film on the surface, a step of providing an opening for contacting the source and drain regions in the interlayer insulating film, A step of ion-implanting phosphorus through the opening, and a temperature of 900°C or higher after ion implantation1.
and a step of heat-treating at a temperature of 100° C. or less for a time of 30 seconds or less.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to all the drawings.

FIG. 1 (al to (fl) are sectional views shown in the order of steps for explaining one embodiment of the present invention.

An n-channel MIS field effect transistor according to an embodiment of the present invention can be manufactured by the following steps.

First, as shown in FIG. 1(b), on a p-type silicon single crystal substrate 1 shown in FIG. Note that the p-type silicon single crystal substrate 1 may be a p-type well formed on an n-type silicon single crystal substrate.After the element isolation oxide film 2 is completely formed, the buffer oxide film and nitride film are removed. do.

Next, as shown in FIG. 1C, a gate oxide film 3 is entirely formed in the element region, and impurity 4 for threshold voltage control is ion-implanted.

Next, in order to form the gate electrode 6 and form the source and drain junctions as shown in FIG. Implant 5 was performed, and the dose was chosen as above: lXl0
This is because if the resistance is less than 1.times.cm, the diffusion resistance of the source/drain is too high to be practical, and if it is more than 1.times.10.sup.16 Crn.sup.-2, the necessary shallow junction cannot be obtained. An ion energy of 50 Ke V or less is also a necessary condition for obtaining a shallow junction.

Next, as shown in FIG. 1(e), P is used as the interlayer insulating film 7.
In FIG. 4, reference numeral 8 denotes an impurity implanted by ion implantation in the previous step to form a source and drain.

Next, as shown in FIG. 30 at temperatures above °C and below J100°0
Performed in seconds or less. Note that below 900° C. activation is not sufficient, and above 1100'0 the bond moves and it is difficult to obtain a shallow bond.

The reason for setting the time to 30 seconds or less is to prevent bonding fluctuations due to annealing. Thereafter, a contact hole is opened and an aluminum wiring 9 is provided to obtain an n-channel MIS type field effect transistor.

In the n-channel MIS type field effect transistor obtained in the above-mentioned example, phosphorus is ion-implanted as an impurity, so the impurity concentration distribution does not become step-like but becomes a Gaussian-like distribution, and the electric field concentration is small near the cell train, and hot carriers are Therefore, in the FET, performance deterioration such as threshold voltage fluctuation due to hot carriers is less likely to occur.

Further, in the non-example, since the heat treatment is performed in a short time, impurities are not diffused more than necessary, and a shallow junction can be obtained. Therefore, short channel effects such as punch-through and reduction in threshold voltage do not occur.

Furthermore, the method of the fifth embodiment can be easily combined with the conventional manufacturing method of an n-channel MIS field effect transistor, and can be easily implemented since it does not involve complicated steps.

Next, a second example will be described. Figure 2(a)~
(d) is a sectional view shown in the order of steps for explaining the second embodiment of the invention.

In the second embodiment, all steps from the first step to the growth of the PSG film as an interlayer insulating film, that is, from FIG. 1(a) to FIG. 1te+ are completely the same. The subsequent process is the second
This will be explained with reference to Figures fa) to (d). Figure 2 (a) to (d)
The same parts as in Figures (a) to (e+) of Silk 1 are indicated by the same numbers.

First, after the steps in FIG. 1 ia) to (e), as shown in FIG. 2 (a), the PSG film 7 which is an interlayer insulating film formed on the surface is
Then, contact holes 141 are formed in the source and drain regions.Next, as shown in FIG. 2(b), ion implantation 11 of phosphorus is performed using the %PSG film 7 as a mask. This ion implantation has an energy of 50KeV and a dose of 5X1015cm-2.
This is done under certain conditions.

Next, as shown in FIG.
When the above is performed at a temperature of IJ00°C or less for a time of 30 seconds or less, the source and drain junctions 12 are formed.

Next, as shown in FIG. 2(d), the aluminum wiring 9
By providing , an n-channel MIS type field effect transistor can be obtained.

As described above, according to the second embodiment of the present invention, the contact resistance of the source and drain junctions can be reduced without impairing the effects of the first embodiment.

Note that in the above embodiments, Norogen-lamb annealing was used as the short-time heat treatment method, but the present invention is not limited to this, and other short-time annealing methods such as laser annealing, electron beam annealing, and flash lamp annealing can be used. It goes without saying.

(Effects of the Invention) As explained above, according to the invention, it is possible to manufacture an n-channel MIS type field effect transistor that prevents the short channel effect from occurring and generates fewer hot carriers without using complicated processes. Can be done.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views shown in the order of steps for explaining the first embodiment of the invention, and FIGS. 2(a) to Fdl
FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in order of steps. 1...P-type silicon single crystal substrate, 2...Element isolation oxide film, 3...Gate oxide film, 4...
・Impurity for threshold voltage control, 5... Ion implantation for source and drain formation, 6... Gate electrode, 7... P SO interlayer insulating film, 8...
...Impurity for source and drain formation, 9
... Aluminum interconnection, 10 ... Junction formed, 11 ... Ion implantation for contact formation, 12 ... Junction formed. U 謬 l fig.

Claims (3)

[Claims] (1) N-channel Mf with gate electrode length of 1.5 μm or less
When forming the source and drain regions of an S-type field effect transistor on the entire surface of an n-type silicon single crystal substrate,
Using the gate electrode as a mask, phosphorus is applied to the substrate.
5 at a dose of 0 cm or more and 1 x 1016 cm or less
A process of ion implantation with an energy of 0 KeV or less, and a step of ion implantation at a temperature of 900°C or more and 1100°C or less after the ion implantation.
A method for manufacturing an MIS type field effect transistor, comprising a step of performing heat treatment for a time of 0 seconds or less. (2) N-channel M with gate electrode length of 1.5 μm or less
When forming the source and drain regions of a type Ia field effect transistor on the entire surface of an n-type silicon single crystal substrate, using the gate electrode as a mask, the phosphorus tnIJ substrate is heated at a dose of 1x1015cm-2 or more and 1x1016cm or less and 50KeV or less. a step of implanting ions with an energy of 1. A method for manufacturing an MIS field effect transistor, which comprises the following steps: and a step of heat treatment at a temperature of 900"0 to 1100° C. for a period of 30 seconds or less after ion implantation. (3) The MIS type field effect transistor according to claim (1) or (2), wherein the n-type silicon single crystal substrate is a p-type well formed on the entire surface of the n-type silicon single crystal substrate. manufacturing method.