JPH11204783A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which increased speed diffusion or re-distribution of a punch through stopper layer formed for suppression of a short channel effect is reduced, and an inverted short channel effect is suppressed. SOLUTION: A region 17 where fluorine exists is provided at a region of a p-type conductive punch through stopper layer 16 formed in a p-type conductive silicone substrate 11. As fluorine is captured by excessive failure which is introduced in the silicone substrate when a high density source and a drain diffusion layer are formed, increased speed diffusion or re-distribution of a punch through stopper layer can be reduced, an inverted short channel effect is suppressed and a short channel effect is improved. Additionally a long term reliability represented by a hot carrier effect can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device effective for suppressing the reverse short channel effect which has become apparent in a fine MIS field effect transistor having a gate length of 0.3 .mu.m or less. And its manufacturing method.

[0002]

2. Description of the Related Art As described in Japanese Patent Application Laid-Open No. 63-136661, the formation of an impurity diffusion layer in the manufacture of a semiconductor device is performed by introducing impurities by ion implantation into the main surface of a semiconductor, and then performing thermal treatment. This was done by a method of performing diffusion. This prior art is based on MOS (Metal Oxide Semi
A general manufacturing method used to form source / drain diffusion layers of a conductor) type field effect transistor (FET) (hereinafter referred to as MOSFET) and a punch-through stopper layer for suppressing a short channel effect. is there.

As described in JP-A-63-9924, formation of a shallow impurity diffusion layer is carried out by introducing impurities by ion implantation and then using lamp heating. Was.

Further, as described in Japanese Patent Application Laid-Open No. 63-124519, a buried impurity layer is formed as follows.
After burying impurities in the substrate by implanting high energy impurities, annealing is performed for a short time to reduce redistribution of impurities.

[0005]

Generally, MOSFETs
The high concentration ion implantation for forming the source and drain diffusion layers causes excessive defects in the silicon substrate. Among the above-mentioned prior arts, in the method of forming an impurity diffusion layer by thermal diffusion, the diffusion depth is increased due to accelerated diffusion due to defects or the like caused by the ion implantation, which makes it difficult to miniaturize the MOSFET. There was a problem of doing.

A fine MO having a gate length of 0.3 μm or less is used.
In the SFET, the punch-through stopper layer introduced to suppress the short channel effect has a high concentration. Impurities in the punch-through stopper layer are redistributed due to ion implantation defects caused by this, and an inverse short channel effect (a phenomenon in which the threshold voltage increases as the gate length decreases) occurs. The reverse short channel effect cannot be suppressed by conventional lamp heating or short-time annealing, and the fine M
This makes it difficult to control the threshold voltage of the OSFET.

Accordingly, an object of the present invention is to reduce the accelerated diffusion and redistribution of impurities due to heat treatment after ion implantation, which is essential for activating impurities introduced into a silicon substrate by ion implantation. An object of the present invention is to provide a semiconductor device having a high-performance fine MOSFET in which a channel effect is suppressed. Another object of the present invention is to provide a method for manufacturing the semiconductor device.

[0008]

In order to achieve the above object, a semiconductor device according to the present invention is achieved by trapping an excess defect formed by ion implantation with a halogen element such as fluorine. That is, in a semiconductor device including a MIS field-effect transistor, a region in which a halogen element such as fluorine or chlorine or a halogen ion is present is provided in at least one of the surface and the inside of an active region of a semiconductor substrate. It is assumed that.

In this case, the halogen element or the halogen ion may be selectively present in the channel region or under the gate electrode of the MIS field effect transistor.

It is preferable that the dose of the halogen element or the halogen ion is in the range of 10 ¹⁴ to 10 ¹⁶ cm ^-2 .

Further, the MIS field-effect transistor has a source / drain diffusion layer including a region whose impurity concentration is lower than the impurity concentration, that is, a so-called LDD (Lightly Doped).
(pedDrain) structure.

Further, the gate insulating film of the MIS type field effect transistor may be a silicon oxide film, a silicon nitride film, a composite film of a silicon oxide film and a silicon nitride film, a silicon oxide film having a nitrided surface, or an oxidized surface. It is preferable to use any of the silicon nitride films described above.

A method for manufacturing a semiconductor device according to the present invention
In a method of manufacturing a semiconductor device including an IS type field effect transistor, an ion implantation step of implanting a halogen element such as fluorine, chlorine or the like into an active region, a channel region or a gate electrode below a MIS field effect transistor on a semiconductor substrate is performed. It is characterized by having.

In this case, the dose of the halogen ions is set to 1
It is preferable to set the range of 0 ¹⁴ to 10 ¹⁶ cm ^-2 .

[0015]

An embodiment of the present invention will be described below with reference to the drawings.

<Embodiment 1> FIGS. 1 and 2 are views showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. Here, as an example, an n-channel type MOSF
3 shows a manufacturing process of ET. Hereinafter, description will be made in the order of steps.

First, as shown in FIG. 1A, an oxidation treatment is performed using a p-conductivity type silicon substrate 11 having an impurity concentration of about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ , and a silicon film having a thickness of 15 nm is formed on the surface. After forming the oxide film 12, the silicon oxide film 1
2 a silicon nitride film 1 acting as an oxidation resistant mask
3 is partially formed.

Next, as shown in FIG. 1B, the silicon substrate 11 is oxidized and a silicon oxide film 14 acting as an element isolation insulating film is selectively formed on a portion not masked by the silicon nitride film 13. Form.

Subsequently, as shown in FIG. 1C, the silicon nitride film 13 and the silicon oxide film 12 are removed, and a new oxidation process is performed to form a silicon oxide film 15 having a thickness of 20 nm on the silicon substrate 11. I do.

Next, as shown in FIG. 2A, a so-called punch-through stopper of 10 ¹⁷ to 10 ¹⁸ cm ^{-3 is formed on} the silicon substrate 11 by using boron (B) as an ion source at an acceleration voltage of, for example, 40 keV. A buried layer 16 of p-conductivity type is formed, and subsequently, a fluorine (F) is used as an ion source in the silicon substrate 11 at an acceleration voltage of, for example, 60 keV.
Ions are implanted at a dose of 10 ¹⁵ cm ^-2 to form a fluorine existing region 17. After that, the silicon oxide film 15 is removed.

At this time, fluorine may be present at the interface between the silicon oxide film 15 and the silicon substrate 11 or at any position within the silicon substrate 11, but the projection range of ion implantation of fluorine and the punch-through stopper layer 16 It is desirable that the projection range of the boron ion implantation for formation be the same. The dose of the fluorine ion implantation is MO
The lower limit of the defect concentration introduced at the time of forming the source and drain diffusion layers of the SFET, that is, 10 ¹⁴ cm ⁻² or more may be implanted. However, since the case of introducing more than the upper limit of the concentration of defects cause such leakage current occurring defects by halogen, it is desirable to implant in 10 ¹⁶ cm ^-2 or less. Further, in this embodiment, fluorine ion implantation is performed after boron ion implantation is performed. However, similar effects can be obtained by performing fluorine ion implantation first.

Next, as shown in FIG. 2B, the silicon substrate 11 is oxidized to form a gate oxide film 18 having a thickness of about 5 nm on the surface. Subsequently, a polycrystalline silicon film having a thickness of 200 nm is deposited on the gate oxide film 18 by a reduced pressure vapor deposition method, and an n-conductivity type impurity is diffused to make the n-conductivity type. An electrode 19 is formed.

Next, as shown in FIG. 2C, a p-type silicon substrate 11 is formed using arsenic (As) as an ion source using the remaining gate electrode 19 made of a polycrystalline silicon film as a mask. Arsenic ion implantation is performed on the n-type source region 10 having an impurity concentration of about 10 ²¹ cm ^−3.
1 and the drain region 102 are formed. Subsequently, although not shown, wiring is applied to each of the polycrystalline silicon film serving as the gate electrode 19, the source region 101, and the drain region 102 to form contacts.
The n-channel MOSFET is completed.

In the above-described embodiment, the p-type buried layer 16 serving as a punch-through stopper is formed on the silicon substrate 11 before the gate electrode 19 is formed. The gate electrode 19 may be formed by ion implantation of boron using the mask as a mask.

FIG. 3 is a characteristic diagram showing the relationship between the threshold voltage (vertical axis) and the gate length (horizontal axis) in the n-channel MOSFET manufactured according to the present embodiment. It is shown in comparison with the characteristics of FIG. In FIG. 3, a characteristic line 21 indicates the element characteristics according to the conventional example, and characteristic lines 22 and 23 indicate the element characteristics according to the present embodiment. The characteristic line 22 shows the case where the acceleration energy of the fluorine ion implantation is 60 keV, and the characteristic line 23 shows the case where the acceleration energy of the fluorine ion implantation is 120 keV.

The characteristic line 21 of the element according to the prior art is represented by MOS
As the gate length of the FET becomes shorter, the threshold voltage increases (maximum 60 mV), and then the threshold voltage rapidly decreases. On the other hand, the device characteristics of the n-channel MOSFET manufactured by the manufacturing method according to the present embodiment are as follows.
There is no increase in the threshold voltage and the threshold voltage gradually decreases. That is, it is shown that the reverse short channel effect is suppressed and the short channel effect is also improved by the present embodiment.

FIG. 4 is a characteristic diagram showing the relationship between the hot carrier lifetime (vertical axis) and the reciprocal of the drain voltage (horizontal axis) of the n-channel MOSFET manufactured according to this embodiment. It is shown in comparison with the characteristics of the element. A characteristic line 31 shows the characteristics of the element according to the conventional example, and characteristic lines 32 and 33 show the characteristics of the element according to the present embodiment. The characteristic line 32 shows the case where the acceleration energy of the fluorine ion implantation is 60 keV, and the characteristic line 33 shows the case where the acceleration energy of the fluorine ion implantation is 120 keV. From FIG. 4, in the case of this embodiment,
It can be said that the hot carrier lifetime of the device is longer than that of the conventional example and the long-term reliability is excellent.

FIG. 5 is a distribution diagram showing the relationship between the concentration (vertical axis) and the depth (horizontal axis) of a p-type buried layer (boron) 16 serving as a punch-through stopper formed according to this embodiment. This is shown in comparison with the distribution chart according to the conventional example. A characteristic line 41 indicates the distribution of boron in the depth direction according to the conventional example, and a characteristic line 42 indicates the distribution of boron in the depth direction according to the embodiment. As is clear from FIG. 5, in the boron distribution according to the present embodiment, the peak concentration is increased and the spreading in the depth direction is suppressed as compared with the distribution of the conventional example. The distribution of boron according to the conventional example is a high concentration source,
At the time of arsenic ion implantation for forming the drain diffusion layer, excessive defects introduced into the silicon substrate caused redistribution by accelerated diffusion or the like. However, as in the present embodiment, the fluorine region 17 was formed on the silicon substrate 11. By providing this, redistribution of boron can be suppressed. As a result, as shown in FIG. 3 and FIG. 4, the suppression of the inverse short channel effect, the improvement of the short channel effect, and the improvement of the hot carrier life and the like have been made possible.

Further, in the n-channel MOSFET manufactured according to the present embodiment, the gate oxide film 18 is formed.
Trapped fluorine necessarily exists at the trap level at the interface between the silicon and the silicon substrate 11. As a result, the dielectric constant of the gate oxide film 18 changed, and a gate oxide film resistant to various stresses could be formed.

The drain saturation characteristic of the n-channel MOSFET having a gate length of 0.3 μm or less manufactured in the present embodiment is the same as that of a conventional n-channel MOSFET in which the fluorine existing region 17 is not formed. ing.

<Embodiment 2> FIG. 6 is a view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention, and is an enlarged sectional view of a main part of the semiconductor device shown in the order of steps.
Here, a manufacturing process of an n-channel MOSFET is shown as an example. Hereinafter, description will be made in the order of steps.

FIG. 6A is a sectional view showing a state in which a silicon oxide film 14 as an element isolation insulating film is selectively formed on the silicon substrate 11. The steps up to FIG. 6A are the same as the manufacturing steps up to FIG. 1C in the first embodiment, and a detailed description thereof will be omitted.

Thereafter, as shown in FIG. 6B, the silicon substrate 11 is oxidized to form a gate oxide film 18 having a thickness of about 5 nm on the surface. Subsequently, an amorphous silicon film 51 having a thickness of 20 nm and a silicon oxide film 52 having a thickness of 200 nm are sequentially formed on the gate oxide film 18 by a reduced pressure vapor deposition method. At this time, when the temperature of the silicon substrate 11 is kept so as not to exceed 560 ° C. when the amorphous silicon film 51 is formed, and when the silicon oxide film 52 is formed,
The amorphous silicon film 51 can be formed at a temperature at which the amorphous silicon film 51 is not crystallized, for example, plasma TEOS (Tetraethylorthosilicat).
It is important to use a silicon oxide film that can be formed at 390 ° C. such as an e: methyl tetrasilicate film. This is to prevent the amorphous silicon film 51 from crystallizing and causing a variation in ion distribution due to channeling at the time of ion implantation.

Next, as shown in FIG. 6C, a desired region of the silicon oxide film 52 is opened by a resist method, boron ion implantation and fluorine ion implantation are performed, and the punch-through stopper layer 53 and the fluorine are implanted. Is formed.

Next, as shown in FIG. 7A, after a polycrystalline silicon film 55 having a thickness of 200 nm is selectively grown on the opened amorphous silicon film 51, impurity diffusion of n conductivity type is performed. Was carried out to obtain n-type conductivity.

Next, as shown in FIG. 7B, the silicon oxide film 52 is removed, and then the amorphous silicon film 51 is selectively removed to remove the amorphous silicon 51 and the polycrystalline silicon 5.
The gate electrode 50 made of the laminated film No. 5 was formed.

Thereafter, as shown in FIG. 7C, arsenic ions are implanted into the p-conductivity type silicon substrate 11 using arsenic (As) as an ion source, using the gate electrode 50 as a mask. An n-conductivity source region 101 and a drain region 102 having an impurity concentration of about 10 ²¹ cm ⁻³ are formed.

Subsequently, although not shown, wiring is applied to each of the gate electrode 50, the source region 101, and the drain region 102 to form contacts, thereby completing an n-channel MOSFET.

According to the present embodiment, the punch-through stopper layer 53 and the region 54 in which fluorine exists are formed in a MOSFE in a self-aligned manner without requiring a mask for ion implantation.
It can be formed under the T gate electrode. Therefore, the number of times of using the mask can be reduced, and the junction capacitance between the source / drain diffusion layers and the substrate is reduced. Further, in the manufacturing method according to the present embodiment, the ion implantation for forming the punch-through stopper layer 53 and the region 54 where fluorine is present is performed before the gate oxide film 18 is formed. The heat treatment at the time of forming 18 could be avoided, and the punch-through stopper layer 53 with smaller redistribution could be formed.

The drain saturation characteristic of the n-channel MOSFET having a gate length of 0.3 μm or less manufactured in the present embodiment is the same as that of a conventional n-channel MOSFET in which the fluorine existing region 54 is not formed. ing.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the invention.

For example, in the above embodiment, an n-channel MOSFET having a single drain structure has been described. However, the present invention can be applied to a p-channel MOSFET. Further, the present invention can be applied to a structure including a low concentration region in a source and a drain, that is, a so-called LDD structure.

Further, the gate oxide film 18 shown in each embodiment is not limited to a silicon oxide film, but may be a silicon nitride film,
Another insulating film such as a composite film of a silicon oxide film and a silicon nitride film, a silicon oxide film having a nitrided surface, or a silicon nitride film having a oxidized surface can be used.

Further, in the above embodiment, an example using fluorine has been described. However, even when a halogen element such as chlorine, which is a monovalent element of the same family as fluorine, is used, the formation of the source and drain diffusion layers may occur. Therefore, the same effect can be obtained.

[0045]

The following is a brief description of typical effects obtained in the semiconductor device and the method of manufacturing the same according to the present invention.

Fluorine is captured by excessive defects introduced into the silicon substrate during the formation of the high-concentration source and drain diffusion layers, so that the redistribution of the impurity layer for the punch-through stopper can be suppressed. As a result, the reverse short channel effect, which has been a problem in the fine MOSFET, can be suppressed, and the short channel effect can be improved accordingly. Furthermore, long-term reliability represented by the hot carrier effect can be improved.

[Brief description of the drawings]

FIGS. 1A to 1C are views showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 1A to 1C are cross-sectional views showing the steps of manufacturing an n-channel MOSFET in the order of steps; is there.

FIGS. 2A to 2C are views showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, wherein FIGS.
It is sectional drawing which shows the following process of (c).

FIG. 3 shows a threshold voltage (vertical axis) and a gate length (horizontal axis) of an n-channel MOSFET obtained by a first embodiment of a method of manufacturing a semiconductor device according to the present invention and an element according to a conventional example FIG.

FIG. 4 shows the hot carrier lifetime (vertical axis) and the reciprocal of the drain voltage (horizontal) of an n-channel MOSFET obtained by the first embodiment of the method of manufacturing a semiconductor device according to the present invention and an element according to a conventional example. FIG. 3 is a characteristic diagram showing the relationship of (axis).

FIG. 5 shows the concentration (vertical axis) and depth of a p-type buried layer (boron) serving as a punch-through stopper formed according to the first embodiment of the method of manufacturing a semiconductor device according to the present invention and a conventionally formed punch-through stopper. FIG. 4 is a distribution diagram showing a relationship with (horizontal axis).

FIGS. 6A to 6C are views showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 6A to 6C are cross-sectional views showing the steps of manufacturing an n-channel MOSFET in the order of steps. is there.

FIGS. 7A to 7C are views showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention, wherein FIGS.
It is sectional drawing which shows the following process of (c).

[Explanation of symbols]

11 silicon substrate of p conductivity type, 12 silicon oxide film, 13 silicon nitride film, 14 silicon oxide film, 1
5 ... silicon oxide film, 16 ... p conductivity type region (punch through stopper layer), 17 ... fluorine existing region, 18 ... gate oxide film, 19 ... polycrystalline silicon film, 101 ... n conductivity type source region, 102 ... n Drain region of conductivity type, 21: characteristic line indicating the relationship between threshold voltage and gate length according to the conventional example, 22, 23: characteristic line indicating the relationship between threshold voltage and gate length according to the first embodiment , 31 ... characteristic lines showing the relationship between the hot carrier lifetime and the reciprocal of the drain voltage according to the conventional example, 32, 33 ... characteristic lines showing the relationship between the hot carrier lifetime and the reciprocal of the drain voltage according to the first embodiment, 41: Distribution of the p-type buried layer (boron) according to the conventional example, 42: distribution of the p-type buried layer (boron) according to the first embodiment, 50: gate electrode, 51
... non-condensed silicon film, 52 ... silicon oxide film, 53 ... p
Conductive region (punch-through stopper layer), 54... Fluorine existing region, 55... Polycrystalline silicon film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shizunori Oyu 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. 3-1-1, Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Akihiro Shimizu 3-1-1, Higashi-Koigakubo, Kokubunji-shi, Tokyo Hitachi Ultra-LSI Engineering, Inc. (72) Inventor Takeo Shiba 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] In a semiconductor device including a MIS field-effect transistor, at least one of a surface and an inside of an active region of the semiconductor substrate where the MIS field-effect transistor is formed has a halogen element such as fluorine or chlorine. Alternatively, a semiconductor device provided with a region where a halogen ion exists. 2. A semiconductor device including a MIS field-effect transistor, wherein a region where a halogen element or a halogen ion is present is provided in a channel region of the MIS field-effect transistor. 3. A semiconductor device including a MIS field-effect transistor, wherein a region where a halogen element or a halogen ion is selectively present is provided below a gate electrode of the MIS field-effect transistor. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the dose of the halogen element or the halogen ion is in a range of 10 ¹⁴ to 10 ¹⁶ cm ⁻² . 5. The semiconductor device according to claim 1, wherein the source and drain diffusion layers of the MIS field effect transistor include a region having a lower concentration than the impurity concentration. 6. A gate insulating film of the MIS field effect transistor, wherein the gate insulating film is a silicon oxide film, a silicon nitride film, a composite film of a silicon oxide film and a silicon nitride film, a silicon oxide film having a nitrided surface, or an oxidized surface. The semiconductor device according to claim 1, comprising a silicon nitride film. 7. A method of manufacturing a semiconductor device including a MIS field-effect transistor, wherein fluorine is added to an active region of the semiconductor substrate on which the MIS field-effect transistor is formed.
A method for manufacturing a semiconductor device, comprising an ion implantation step of implanting a halogen element such as chlorine. 8. A method of manufacturing a semiconductor device including a MIS field effect transistor, comprising an ion implantation step of implanting a halogen element such as fluorine or chlorine into a channel region of the MIS field effect transistor. A method for manufacturing a semiconductor device. 9. A method for manufacturing a semiconductor device including a MIS field-effect transistor, comprising an ion implantation step of implanting a halogen element such as fluorine or chlorine below a gate electrode of the MIS field-effect transistor. Semiconductor device manufacturing method. 10. The method according to claim 1, wherein the dose of the halogen ions is 10 ¹⁴
10. Any one of claims 7 to 9, wherein the range is from 10 to 10 ¹⁶ cm ^-2.
13. The method for manufacturing a semiconductor device according to the above item.