JPS56130972A - Manufacture of mos type semiconductor device - Google Patents

Manufacture of mos type semiconductor device

Info

Publication number
JPS56130972A
JPS56130972A JP3335280A JP3335280A JPS56130972A JP S56130972 A JPS56130972 A JP S56130972A JP 3335280 A JP3335280 A JP 3335280A JP 3335280 A JP3335280 A JP 3335280A JP S56130972 A JPS56130972 A JP S56130972A
Authority
JP
Japan
Prior art keywords
oxide film
layer
gate electrode
semiconductor device
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3335280A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Hisakazu Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3335280A priority Critical patent/JPS56130972A/en
Publication of JPS56130972A publication Critical patent/JPS56130972A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To enhance the integration of an MOS type semiconductor device by forming a high density impurity diffused layer on a semiconductor substrate with a gate electrode as a mask and reducing the overlap between the gate and the diffused layer. CONSTITUTION:An oxide film 2 and a gate oxide film 3 are formed on an N type monocrystalline silicon substrate 1, and a gate electrode 4 is further formed thereon. Subsequently, with the oxide film 2 and the gate electrode 4 as masks a high density impurity layer 5 is formed. Then, a CVD silicon oxide film 6 is grown, and a contact hole with aluminum wire is opened. Subsequently, an ion implantation region 7 is formed under the layer 5, and a diffused layer 8 is formed by heat treatment.
JP3335280A 1980-03-18 1980-03-18 Manufacture of mos type semiconductor device Pending JPS56130972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3335280A JPS56130972A (en) 1980-03-18 1980-03-18 Manufacture of mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3335280A JPS56130972A (en) 1980-03-18 1980-03-18 Manufacture of mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS56130972A true JPS56130972A (en) 1981-10-14

Family

ID=12384178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3335280A Pending JPS56130972A (en) 1980-03-18 1980-03-18 Manufacture of mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56130972A (en)

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