JPS56135972A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56135972A
JPS56135972A JP4064280A JP4064280A JPS56135972A JP S56135972 A JPS56135972 A JP S56135972A JP 4064280 A JP4064280 A JP 4064280A JP 4064280 A JP4064280 A JP 4064280A JP S56135972 A JPS56135972 A JP S56135972A
Authority
JP
Japan
Prior art keywords
silicon layer
polycrystalline silicon
region
oxide film
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4064280A
Other languages
Japanese (ja)
Other versions
JPS621269B2 (en
Inventor
Tadashi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4064280A priority Critical patent/JPS56135972A/en
Publication of JPS56135972A publication Critical patent/JPS56135972A/en
Publication of JPS621269B2 publication Critical patent/JPS621269B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To unify an absorption coefficient of a laser beam extending over the whole region on a semiconductor wafer and to effect annealing a monocrystalline region and protecting a polycrystalline region by one time laser radiation by a method wherein a thin polycrystalline silicon layer is deposited over the whole surface of the semiconductor wafer. CONSTITUTION:A field oxide film 2 is formed in the monocrystalline region and a prescribed gate oxide film 4 is formed in an active region. Then, the polycrystalline silicon layer 5 is deposited and a source-drain region 6 is formed with the polycrystalline silicon layer 5 as a mask. In the following, after a phosphorus-doped polycrystalline silicon layer 8 is deposited over the whole surface of the semiconductor wafer, the laser annealing is applied. After the radiation of the laser, the polycrystalline silicon layer 8 is oxidized to form an oxide film, and the oxide film effects insulation of the source-drain region 6 and the polycrystalline silicon layer 5 as the gate and wiring body from each other.
JP4064280A 1980-03-28 1980-03-28 Manufacture of semiconductor device Granted JPS56135972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4064280A JPS56135972A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4064280A JPS56135972A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56135972A true JPS56135972A (en) 1981-10-23
JPS621269B2 JPS621269B2 (en) 1987-01-12

Family

ID=12586205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4064280A Granted JPS56135972A (en) 1980-03-28 1980-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56135972A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621411A (en) * 1984-09-28 1986-11-11 Texas Instruments Incorporated Laser-enhanced drive in of source and drain diffusions
US5142344A (en) * 1984-05-18 1992-08-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US7157660B2 (en) * 2002-11-06 2007-01-02 Ultratech, Inc. Laser scanning apparatus and methods for thermal processing

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142344A (en) * 1984-05-18 1992-08-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US5313077A (en) * 1984-05-18 1994-05-17 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US5315132A (en) * 1984-05-18 1994-05-24 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor
US5543636A (en) * 1984-05-18 1996-08-06 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor
US6221701B1 (en) 1984-05-18 2001-04-24 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US6635520B1 (en) 1984-05-18 2003-10-21 Semiconductor Energy Laboratory Co., Ltd. Operation method of semiconductor devices
US6660574B1 (en) * 1984-05-18 2003-12-09 Semiconductor Energy Laboratory Co., Ltd. Method of forming a semiconductor device including recombination center neutralizer
US6680486B1 (en) 1984-05-18 2004-01-20 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US6734499B1 (en) 1984-05-18 2004-05-11 Semiconductor Energy Laboratory Co., Ltd. Operation method of semiconductor devices
US4621411A (en) * 1984-09-28 1986-11-11 Texas Instruments Incorporated Laser-enhanced drive in of source and drain diffusions
US7157660B2 (en) * 2002-11-06 2007-01-02 Ultratech, Inc. Laser scanning apparatus and methods for thermal processing

Also Published As

Publication number Publication date
JPS621269B2 (en) 1987-01-12

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