JPS56105663A - Manufacture of ic device by complementary type field effect transistor - Google Patents

Manufacture of ic device by complementary type field effect transistor

Info

Publication number
JPS56105663A
JPS56105663A JP896980A JP896980A JPS56105663A JP S56105663 A JPS56105663 A JP S56105663A JP 896980 A JP896980 A JP 896980A JP 896980 A JP896980 A JP 896980A JP S56105663 A JPS56105663 A JP S56105663A
Authority
JP
Japan
Prior art keywords
region
type
layer
polycrystalline
crystallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP896980A
Other languages
Japanese (ja)
Other versions
JPS6043027B2 (en
Inventor
Masahiko Ueda
Koji Nomura
Yasuhiro Funakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55008969A priority Critical patent/JPS6043027B2/en
Publication of JPS56105663A publication Critical patent/JPS56105663A/en
Publication of JPS6043027B2 publication Critical patent/JPS6043027B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To obtain the device which is high in integration degree, operates in high speed and low in consuming electric power by a method wherein when the complementary FET is formed on a same semiconductor substrate, a polycrystalline Si layer is accumulated on the whole surface, irradiated with laser rays and refused to be single-crystallized, and an active region of each FET is formed on the single-crystallized layer. CONSTITUTION:A thick SiO2 layers 7 are burried with the surface being made flat in an inactive region of an N<+> type Si substrate 1, and shallow P<+> type regions 14 are diffusion-formed on the substrate 1 in an active region surrounded by those layers. Then, the polycrystalline Si layers 15 are accumulated on the whole surface including those by CVD method, being irradiated with the laser rays on the whole surface to cause the layer 15 to be refused, being remained as polycrystalline on the layer 7 and single-crystallized on the regions 14. Thereafter, P<+>-ions and B<+>-ions are injected alternately using a mask to cause an N<-> type region 16 of a P-channel surrounded by P<+> type polycrystals 20 to be produced on the region 14 on one side and a P<-> type region 17 of an N-channel surrounded by N<+> type polycrystals 21 to be produced on the region 14 on the other side, which respectively are formed with source and drain regions 18 and 19.
JP55008969A 1980-01-28 1980-01-28 Method for manufacturing integrated circuit device using complementary field effect transistors Expired JPS6043027B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55008969A JPS6043027B2 (en) 1980-01-28 1980-01-28 Method for manufacturing integrated circuit device using complementary field effect transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55008969A JPS6043027B2 (en) 1980-01-28 1980-01-28 Method for manufacturing integrated circuit device using complementary field effect transistors

Publications (2)

Publication Number Publication Date
JPS56105663A true JPS56105663A (en) 1981-08-22
JPS6043027B2 JPS6043027B2 (en) 1985-09-26

Family

ID=11707504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55008969A Expired JPS6043027B2 (en) 1980-01-28 1980-01-28 Method for manufacturing integrated circuit device using complementary field effect transistors

Country Status (1)

Country Link
JP (1) JPS6043027B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201440A (en) * 1983-04-30 1984-11-15 Toshiba Corp Semiconductor device and manufacture thereof
US4829359A (en) * 1987-05-29 1989-05-09 Harris Corp. CMOS device having reduced spacing between N and P channel
JP2008231970A (en) * 2007-03-19 2008-10-02 Kubota Corp Engine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201440A (en) * 1983-04-30 1984-11-15 Toshiba Corp Semiconductor device and manufacture thereof
US4829359A (en) * 1987-05-29 1989-05-09 Harris Corp. CMOS device having reduced spacing between N and P channel
JP2008231970A (en) * 2007-03-19 2008-10-02 Kubota Corp Engine

Also Published As

Publication number Publication date
JPS6043027B2 (en) 1985-09-26

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