JPS5691461A - Manufacturing of complementary mos integrated circuit - Google Patents

Manufacturing of complementary mos integrated circuit

Info

Publication number
JPS5691461A
JPS5691461A JP16906279A JP16906279A JPS5691461A JP S5691461 A JPS5691461 A JP S5691461A JP 16906279 A JP16906279 A JP 16906279A JP 16906279 A JP16906279 A JP 16906279A JP S5691461 A JPS5691461 A JP S5691461A
Authority
JP
Japan
Prior art keywords
region
membrane
type region
type
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16906279A
Other languages
Japanese (ja)
Other versions
JPH0113229B2 (en
Inventor
Katsuyuki Inayoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16906279A priority Critical patent/JPS5691461A/en
Publication of JPS5691461A publication Critical patent/JPS5691461A/en
Publication of JPH0113229B2 publication Critical patent/JPH0113229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To prevent occurrence of crystal defect, by forming an n type region and a p type region on surface of a semiconductor substrate, introducing a p type impurity and an n type impurity into an isolation region, and forming a field isolation layer by oxidation. CONSTITUTION:A silicon nitride membrane 10 is provided as a protective membrane, and using this as a mask boron ion is driven into an entire surface of an isolation region 14 to form a p<+> region 30. And then, an impurity introduction preventive membrane 32 is formed covering a p type region 6, and using this membrane 32 and the silicon nitride membrane 10 on an n type region 4 as masks, phosphorus ion is driven partly in the isolation region 14 on the n type region 4 to form an n<+> type region 34. Finally, surface of a substrate 2 is selectively oxidized using the silicon nitride membrane 10 as a mask.
JP16906279A 1979-12-25 1979-12-25 Manufacturing of complementary mos integrated circuit Granted JPS5691461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16906279A JPS5691461A (en) 1979-12-25 1979-12-25 Manufacturing of complementary mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16906279A JPS5691461A (en) 1979-12-25 1979-12-25 Manufacturing of complementary mos integrated circuit

Publications (2)

Publication Number Publication Date
JPS5691461A true JPS5691461A (en) 1981-07-24
JPH0113229B2 JPH0113229B2 (en) 1989-03-03

Family

ID=15879630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16906279A Granted JPS5691461A (en) 1979-12-25 1979-12-25 Manufacturing of complementary mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5691461A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878453A (en) * 1981-08-31 1983-05-12 ヒューズ・エアクラフト・カンパニー Method of producing c-mos semiconductor
JPS58202562A (en) * 1982-04-08 1983-11-25 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Method of producing semiconductor device
JPS61225857A (en) * 1985-03-29 1986-10-07 Nippon Telegr & Teleph Corp <Ntt> Manufacture of complementary semiconductor device
US4931850A (en) * 1985-07-05 1990-06-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a channel stop region

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878453A (en) * 1981-08-31 1983-05-12 ヒューズ・エアクラフト・カンパニー Method of producing c-mos semiconductor
JPS58202562A (en) * 1982-04-08 1983-11-25 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Method of producing semiconductor device
JPH0479142B2 (en) * 1982-04-08 1992-12-15 Etsuse Jii Etsuse Atesu Konhonentei Eretsutoronishi Spa
JPS61225857A (en) * 1985-03-29 1986-10-07 Nippon Telegr & Teleph Corp <Ntt> Manufacture of complementary semiconductor device
US4931850A (en) * 1985-07-05 1990-06-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a channel stop region

Also Published As

Publication number Publication date
JPH0113229B2 (en) 1989-03-03

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