JPS644019A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS644019A JPS644019A JP62159103A JP15910387A JPS644019A JP S644019 A JPS644019 A JP S644019A JP 62159103 A JP62159103 A JP 62159103A JP 15910387 A JP15910387 A JP 15910387A JP S644019 A JPS644019 A JP S644019A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- resist layer
- alignment
- openings
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To reduce the required number of masks and to shorten a manufacturing process by a method wherein a patterning operation to form an alignment mask and another patterning operation to form a first bell region are executed simultaneously. CONSTITUTION:A silicon oxide layer 2 to be used as a film is formed on a silicon substrate 1 by a thermal oxidation method, a CVD method or the like; a first resist layer 3 to form an alignment mask and a well region is formed on the layer. Then, by a patterning operation using a mask I first openings 4 acting as alignment masks and a second opening 5 to form a first well region are made in the first resist layer 3. An impurity of, e.g., boron or the like is introduced into the silicon substrate 1 through these openings 4, 5; impurity regions 6 are formed directly under the first openings 4 and a p-well region 7 is formed directly under the second opening 5. By using this process, a mask and a resist layer which are used exclusively to form the alignment masks are not required; the process is simplified; the resist layer can be used effectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62159103A JP2545865B2 (en) | 1987-06-26 | 1987-06-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62159103A JP2545865B2 (en) | 1987-06-26 | 1987-06-26 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS644019A true JPS644019A (en) | 1989-01-09 |
JP2545865B2 JP2545865B2 (en) | 1996-10-23 |
Family
ID=15686305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62159103A Expired - Fee Related JP2545865B2 (en) | 1987-06-26 | 1987-06-26 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2545865B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4968637A (en) * | 1989-05-31 | 1990-11-06 | Raytheon Company | Method of manufacture TiW alignment mark and implant mask |
US5830799A (en) * | 1995-08-25 | 1998-11-03 | Sony Corporation | Method for forming embedded diffusion layers using an alignment mark |
JP2007103472A (en) * | 2005-09-30 | 2007-04-19 | Toshiba Corp | Semiconductor integrated circuit device and its manufacturing method |
CN101894800A (en) * | 2010-05-28 | 2010-11-24 | 上海宏力半导体制造有限公司 | Method for manufacturing high voltage CMOS devices |
-
1987
- 1987-06-26 JP JP62159103A patent/JP2545865B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4968637A (en) * | 1989-05-31 | 1990-11-06 | Raytheon Company | Method of manufacture TiW alignment mark and implant mask |
US5830799A (en) * | 1995-08-25 | 1998-11-03 | Sony Corporation | Method for forming embedded diffusion layers using an alignment mark |
JP2007103472A (en) * | 2005-09-30 | 2007-04-19 | Toshiba Corp | Semiconductor integrated circuit device and its manufacturing method |
US7943478B2 (en) | 2005-09-30 | 2011-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method |
CN101894800A (en) * | 2010-05-28 | 2010-11-24 | 上海宏力半导体制造有限公司 | Method for manufacturing high voltage CMOS devices |
Also Published As
Publication number | Publication date |
---|---|
JP2545865B2 (en) | 1996-10-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |