CN101894800A

CN101894800A - Method for manufacturing high voltage CMOS devices

Info

Publication number: CN101894800A
Application number: CN2010101873685A
Authority: CN
Inventors: 叶滋婧; 令海阳
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-05-28
Filing date: 2010-05-28
Publication date: 2010-11-24

Abstract

The invention provides a method for manufacturing high voltage CMOS devices, comprising the following steps: S1, forming an oxide layer on the surface of a substrate and coating photoresist on the surface of the oxide; S2, copying the patterns on a first mask onto the photoresist through photoetching and developing, wherein the first mask is provided with the photo alignment mark patterns and patterns for forming a high voltage well; S3, taking the photoresist as a mask layer, doping the areas which are not sheltered by the photoresist and forming deep mark wells and a deep high voltage well below the surface of the substrate; S4, taking the photoresist as the mask layer, etching the areas which are not sheltered by the photoresist and forming photo alignment marks in the deep mark wells; and S5, removing the photoresist. The method dispenses with the step of independently forming the photo alignment marks in the process of manufacturing the deep high voltage well, simplifies the manufacturing process and saves the manufacturing cost.

Description

The manufacture method of high voltage CMOS device

Technical field

The present invention relates to semiconductor device processing technology, relate in particular to a kind of manufacture method of high voltage CMOS device.

Background technology

Figure 1A～Fig. 1 G is depicted as the flow chart of prior art mesohigh cmos device manufacture method:

Referring to Figure 1A, on the surface of lining base 101, be deposited with one deck oxide 102, scribble photoresist (photoresist) 103 on the surface of described oxide 102;

Referring to Figure 1B, optics autoregistration mark (the photo alignment mark) pattern on zero mask (zero mask) 201 is copied on the described photoresist 103 by photoetching, development;

Referring to Fig. 1 C, with described photoresist 103 is mask layer, etching is carried out in described photoresist 103 uncovered zones, etch away the described lining base 101 of described oxide 102 and part, form optics autoregistration mark 300 on lining base 101 surfaces that are deposited with oxide 102, remove described photoresist 103 again;

Referring to Fig. 1 D, coat photoresist 104 on the surface of the oxide 102 that is formed with optics autoregistration mark 300;

Referring to Fig. 1 E, be alignment fiducials with described optics autoregistration mark 300, by photoetching, development, the high pressure trap on first mask 202 (high voltage well) pattern is copied on the described photoresist 104;

Referring to Fig. 1 F, be mask layer with described photoresist 104, ion is carried out in described photoresist 104 uncovered zones inject (promptly mixing), form deep high voltage well 400 in basic 101 lower face of described lining;

Referring to Fig. 1 G, remove described photoresist 104;

So far, finished the deep high voltage well making step in the high voltage CMOS device manufacturing process, next carried out the MOS transistor making step, the making flow process of relevant MOS transistor is no longer introduced here.

The manufacture method of the high voltage CMOS device of prior art, in the process of making deep high voltage well, adopt zero mask 201 to form optics autoregistration mark 300 earlier on lining base 101 surfaces that are deposited with oxide 102, utilize this optics autoregistration mark 300 alignment fiducials again as first mask 202, high pressure trap pattern on first mask 202 is copied on the photoresist 104 exactly, the effect of described zero mask 201 is not carried out other function except producing optics autoregistration mark 300, making other figure layer also needs other mask, and this has increased the complexity and the manufacturing cost of technology.

Summary of the invention

The object of the present invention is to provide a kind of manufacture method of high voltage CMOS device, in the process of making deep high voltage well, save the relevant step that forms optics autoregistration mark separately, simplified manufacturing process, saved manufacturing cost.

To achieve the above object, the invention provides a kind of manufacture method of high voltage CMOS device, may further comprise the steps: step S1, form an oxide layer on the surface of lining base, coat photoresist on the surface of described oxide; Step S2 copies to the pattern on first mask on the described photoresist by photoetching, development, and described first mask is provided with optics autoregistration indicia patterns and is used to form the pattern of high pressure trap; Step S3 is a mask layer with described photoresist, is mixed in the uncovered zone of described photoresist, forms mark deep trap and deep high voltage well below described lining primary surface; Step S4 is a mask layer with described photoresist, and etching is carried out in the uncovered zone of described photoresist, forms optics autoregistration mark at described mark deep trap place; Step S5 removes described photoresist.

The manufacture method of above-mentioned high voltage CMOS device, wherein, the optics autoregistration mark that forms among the described step S4 is used as next layer mask version to reference of reference.

The manufacture method of above-mentioned high voltage CMOS device, wherein, in the uncovered zone of described photoresist, the described lining base of described oxide layer and part is etched away among the described step S4.

The manufacture method of above-mentioned high voltage CMOS device, wherein, the material of described lining base is a silicon.

The manufacture method of above-mentioned high voltage CMOS device, wherein, described oxide layer is a silicon dioxide, this oxide layer is as sacrificial oxide layer.

The manufacture method of above-mentioned high voltage CMOS device wherein, adopts the surface deposition oxide layer of CVD (Chemical Vapor Deposition) method at described lining base among the described step S1.

The manufacture method of above-mentioned high voltage CMOS device wherein, adopts ion implantation to mix among the described step S3.

The manufacture method of high voltage CMOS device of the present invention is merged together pattern (optics autoregistration mark) on zero mask and the pattern (high pressure trap) on first mask in the process of making deep high voltage well, saved the relevant step that forms optics autoregistration mark separately, simplify the manufacturing process of high voltage CMOS device, saved the manufacturing cost of high voltage CMOS device.

Description of drawings

The manufacture method of high voltage CMOS device of the present invention is provided by following embodiment and accompanying drawing.

Figure 1A～Fig. 1 G is the flow chart of prior art mesohigh cmos device manufacture method.

Fig. 2 A～Fig. 2 G is the flow chart of high voltage CMOS device manufacture method of the present invention.

Embodiment

Below with reference to Fig. 2 A～Fig. 2 G the manufacture method of high voltage CMOS device of the present invention is described in further detail.

The manufacture method of high voltage CMOS device of the present invention may further comprise the steps:

Step S1 forms an oxide layer on the surface of lining base, coats photoresist on the surface of described oxide;

Step S2 copies to the pattern on first mask on the described photoresist by photoetching, development, and described first mask is provided with optics autoregistration indicia patterns and is used to form the pattern of high pressure trap;

Step S3 is a mask layer with described photoresist, is mixed in the uncovered zone of described photoresist, forms mark deep trap and deep high voltage well below described lining primary surface;

Step S4 is a mask layer with described photoresist, and etching is carried out in the uncovered zone of described photoresist, forms optics autoregistration mark at described mark deep trap place;

Step S5 removes described photoresist.

Now describe the manufacture method of high voltage CMOS device of the present invention in detail with an embodiment:

Step 1 forms an oxide layer 502 on the surface of lining base 501, shown in Fig. 2 A;

In the present embodiment, the material of described lining base 501 is a silicon, and described oxide layer 502 is a silicon dioxide, and this oxide layer 502 is as sacrificial oxide layer;

The method of formation oxide layer 502 is CVD (Chemical Vapor Deposition) method for example;

Step 2 is coated photoresist 503 on the surface of described oxide layer 502, shown in Fig. 2 B;

Step 3 copies to the pattern on first mask 601 on the described photoresist 503, shown in Fig. 2 C by photoetching;

Described first mask 601 is provided with and is used for next layer mask version optics autoregistration indicia patterns of aiming at and the pattern that is used to form the high pressure trap;

Step 4, the photoresist 503 on the zone of predetermined formation optics autoregistration mark and high pressure trap is removed in developing process, shown in Fig. 2 D;

In the predetermined zone that forms optics autoregistration mark and high pressure trap, the surface exposure of described oxide layer 502 comes out, and in other zone, photoresist 503 is arranged on the surface of described oxide layer 502;

Step 5 is a mask layer with described photoresist 503, is mixed in described photoresist 503 uncovered zones, forms mark deep trap 701 and deep high voltage well 702 in basic 501 lower face of described lining, shown in Fig. 2 E;

Ion implantation is for example adopted in described doping, in the present embodiment, select N type foreign ion, the high density ion is carried out in the predetermined zone (being described photoresist 503 uncovered zones) that forms optics autoregistration mark and high pressure trap inject, form mark deep trap 701 and high density N moldeed depth trap 702 in basic 501 lower face of described lining;

Step 6, be mask layer still with described photoresist 503, etching is carried out in the predetermined zone (being described photoresist 503 uncovered zones) that forms optics autoregistration mark and high pressure trap, form optics autoregistration mark 800 at described mark deep trap 701 places, shown in Fig. 2 F;

In etching process, the described lining base 501 of described oxide layer 502 and part is etched away;

Described optics autoregistration mark 800 is as the alignment fiducials of next layer mask version;

Step 7 is removed described photoresist 503, shown in Fig. 2 G;

Claims

1. the manufacture method of a high voltage CMOS device is characterized in that, may further comprise the steps:

Step S5 removes described photoresist.

2. the manufacture method of high voltage CMOS device as claimed in claim 1 is characterized in that, the optics autoregistration mark that forms among the described step S4 is used as next layer mask version to reference of reference.

3. the manufacture method of high voltage CMOS device as claimed in claim 1 is characterized in that, in the uncovered zone of described photoresist, the described lining base of described oxide layer and part is etched away among the described step S4.

4. the manufacture method of high voltage CMOS device as claimed in claim 1 is characterized in that, the material of described lining base is a silicon.

5. the manufacture method of high voltage CMOS device as claimed in claim 4 is characterized in that, described oxide layer is a silicon dioxide, and this oxide layer is as sacrificial oxide layer.

6. the manufacture method of high voltage CMOS device as claimed in claim 1 is characterized in that, adopts the surface deposition oxide layer of CVD (Chemical Vapor Deposition) method at described lining base among the described step S1.

7. the manufacture method of high voltage CMOS device as claimed in claim 1 is characterized in that, adopts ion implantation to mix among the described step S3.