JP2545865B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a well region is formed by ion implantation and selective oxidation is performed using an alignment mark. .

[Outline of Invention]

The present invention relates to a method of manufacturing a semiconductor device in which a well region is formed prior to selective oxidation, and by simultaneously performing patterning for forming an alignment mark and a first well region, the required number of masks and manufacturing This makes it possible to shorten the process.

[Conventional technology]

As semiconductor devices become highly integrated, annealing treatment for diffusing impurities in the well region causes crystal defects in the semiconductor substrate when an oxidation resistant film is formed on the surface, which adversely affects the characteristics of the semiconductor device. Is a problem. Such a defect is caused by a stress between an oxidation resistant film such as silicon nitride used for selective oxidation and a semiconductor substrate which is a base in a manufacturing process of a MOS transistor or a bipolar transistor. Therefore, if the oxidation resistant film does not exist during annealing, the above defects will not occur.

Therefore, as a method of manufacturing a semiconductor device in which an oxidation resistant film does not exist at the time of annealing, the applicant of the present invention has previously filed Japanese Patent Application No. 61-28.
The technology described in the specification of 3496 and the drawings is proposed. According to this technique, the well region can be formed and selective oxidation can be performed without the presence of the oxidation resistant film during annealing. This technique will be described with reference to FIGS. 2 (A) to 2 (H).

First, as shown in FIG. 2A, a pad oxide film (22) made of silicon oxide is formed on a semiconductor substrate (21) made of silicon, for example, by thermal oxidation or CVD. The pad oxide film (22) is an oxidation resistant film (not shown) formed on the pad oxide film (22) in a later selective oxidation step.
Plays a role of relieving the stress between the substrate and the semiconductor substrate (21) as the base. A first resist layer (23) is further formed on the pad oxide film (22). The first resist layer (23) is further patterned at a position corresponding to a scribe line by using the mask (i) to provide a window (24) serving as an alignment mark (first step).

Next, as shown in FIG. 2B, the pad oxide film (22) and the semiconductor substrate (21) are etched by RIE or the like by using the first resist layer (23) as a mask, and the window (24) is formed. Are formed deeper (second step).

Next, as shown in FIG. 2 (C), the first resist layer (23) is once removed (third step).

Next, as shown in FIG. 2D, a second resist layer (25) serving as a mask for ion implantation is newly formed by coating (fourth step).

Next, as shown in FIG. 2 (E), patterning is performed using the mask (ii) with the window (24) as a reference for alignment to form a first opening for forming a first well region. (26) is provided (fifth step). Impurities such as boron are introduced by the first ion implantation through the first opening (26) to form the p well region (27) in the semiconductor substrate (21) (sixth step).

Next, as shown in FIG. 2 (F), the second resist layer (25) is removed (seventh step).

Next, as shown in FIG. 2G, a third resist layer (28) is formed (eighth step), and patterning is performed using the mask (iii) with the window (24) as a reference for alignment. Then, a second opening (29) for forming the second well region is provided (9th step). This second opening (2
Impurities such as arsenic are introduced by second ion implantation through 9) to form an n-well region (30) in the semiconductor substrate (21) (tenth step).

Next, as shown in FIG. 2 (H), the third resist layer (28) is removed (11th step).

Thereafter, the p-well region (27) and the n-well region (30) are activated by annealing, and an oxidation resistant film (not shown) is formed so as to cover at least a part of them, and selective oxidation is performed. Be seen.

[Problems to be solved by the invention]

By the way, according to the technique as described above, since the oxidation resistant film that causes stress is not present at the time of annealing the both well regions (27) (30), no crystal defect occurs in the semiconductor substrate. As described above, from the formation of the alignment mark to the removal of the resist layer after the n-well region is formed.
11 steps and 3 masks, alignment marks,
Masks (i), (ii), and (iii) for forming the p-well region and the n-well region are required. In particular, a dedicated mask (i) and a resist layer are used for the step of forming the alignment mark, but these do not contribute to the actual formation of the device.

Therefore, the present invention is intended to provide a method for manufacturing a semiconductor device, which is an improvement over the above-described prior art and which enables effective utilization of the resist layer and shortening of the process.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention has been proposed in order to achieve the above-mentioned object, and includes a step of forming a film on a semiconductor substrate and forming a first resist layer on the film, A step of simultaneously forming a first opening used as an alignment mark and a second opening for forming a first well region in the first resist layer;
Performing a first ion implantation through the opening and the second opening, a step of selectively removing the film using the first resist layer as a mask, and a step of removing the first resist layer, A step of forming a second resist layer on the entire surface of the exposed film and the film removal region, a third opening used as an alignment mark in the film removal region by the first opening, and a second well A step of simultaneously forming a fourth opening for forming a region in the second resist layer, a step of performing second ion implantation through the third opening and the fourth opening, and etching And forming an alignment groove through the third opening, removing the second resist layer and the coating, and then activating the region into which the impurities have been introduced by annealing. Position Forming an oxidation resistant film so as to cover at least a portion of said well region a groove as a reference it was, is characterized in that a step of performing a selective oxidation as a mask the oxidation film.

[Action]

In the method of manufacturing a semiconductor device according to the present invention, since the patterning for forming the alignment mark and the first well region can be simultaneously performed on the same resist layer,
It becomes possible to effectively utilize the resist layer and to omit the two steps of removing the first resist layer and forming the second resist layer in the conventional technique.
Further, it is not necessary to prepare a dedicated mask for forming the alignment mark, and the semiconductor device can be efficiently manufactured.

〔Example〕

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG.
It will be described with reference to FIG. 1 (G).

The present embodiment is an example of a semiconductor device manufacturing method in which a well region is formed prior to selective oxidation, and patterning for forming an alignment mark and a first well region is simultaneously performed on the same resist layer. .

First, as shown in FIG. 1 (A), a silicon substrate (1)
A silicon oxide layer (2) to be a film is formed thereon by thermal oxidation or CVD, and a first resist layer (3) for forming an alignment mark and a well region is further formed thereon.

Next, as shown in FIG. 1B, the first resist layer (3) is formed by patterning using a mask (I).
A first opening (4) serving as an alignment mark in the first and second openings (5) for forming the first well region
Is provided (first step). These openings (4), (5)
An impurity such as boron is introduced into the silicon substrate (1) by first ion implantation through the impurity regions (6) and second openings (5) immediately below the first opening (4). A p-well region (7) is formed immediately below (second)
Process).

According to this process, the process is simplified and the resist layer is effectively used as compared with the conventional process that requires a dedicated mask and a resist layer for forming the alignment mark.

The first opening (4) is formed, for example, in the scribe line region existing in the middle of each device formation region. This scribe line area is a boundary line when the wafer is cut into individual device formation areas, that is, chips after all manufacturing processes are completed. Does not hurt.

Further, since the first opening (4) is formed as a steep recess by means of RIE or the like, a sharp alignment signal can be taken out when the position is detected by, for example, laser scanning or the like, which is reliable. Positioning is possible.

Next, as shown in FIG. 1 (C), the silicon oxide layer (2) exposed at the bottoms of the first opening (4) and the second opening (5) is removed by etching, The opening (4) is formed deeper (third step). At this time, the portion where the silicon oxide layer (2) has been removed is the film removal region, which corresponds to a region used as an alignment mark and a p-well region in a later step.

Next, as shown in FIG. 1D, the first resist layer (3) is removed (fourth step). As a result, the silicon oxide layer (2) and the film removal area are exposed on the surface of the wafer.

Next, as shown in FIG. 1 (E), a second resist layer (8) is formed on the entire surface of the wafer (fifth step), and a mask (II) is formed.
Is used to form a third opening (9) used as an alignment mark in the film removal region by the first opening, and the third opening (9) and the second opening are formed. A fourth opening (10) for forming the second well region is provided in a portion that does not overlap with the portion (5) (sixth step). Impurities such as arsenic are introduced into the silicon substrate (1) by second ion implantation through the third opening (9) and the fourth opening (10),
The impurity region (11) is formed immediately below the opening of the above, and the n well region (12) is formed immediately below the fourth opening (seventh step).
Here, the impurity region (6) in which the p-type impurity has already been introduced by the first ion implantation is changed to the impurity region (6a) further containing the n-type impurity. Further, since the p well region (7) is masked by the second resist layer (8), it does not receive impurities.

Next, as shown in FIG. 1 (F), the impurity region (6a) containing p-type and n-type impurities is removed by etching to form the alignment groove (13) deeply (eighth step), At this time, since the silicon oxide layer (2) which is a film is present in the n-well region (12), the n-well region (12) is not etched even if the fourth opening (10) is formed. . On the other hand, in the impurity region (6a), since the silicon oxide layer (2) is removed and a large amount of impurities are introduced, the impurity region (6a) is easily etched, and therefore the alignment groove (13) is formed. Easily formed.

Next, as shown in FIG. 1 (G), the second resist layer (8) is removed (step 9).

After that, the silicon oxide layer (2) is removed, the p-well region (7) and the n-well region (12) are activated by annealing, and the silicon oxide layer is newly added from the silicon oxide with the alignment groove (13) as a reference. A pad oxide film (not shown) and an oxidation resistant film (not shown) made of silicon nitride are formed so as to cover at least part of the well region, and selective oxidation is performed. At the time of this selective oxidation, p
Since the activation of impurities in the well region (7) and the n-well region (12), that is, annealing has been completed,
A semiconductor device having good characteristics is manufactured without the risk of crystal defects occurring in the silicon substrate (1).

Although the p-well region (7) is formed prior to the n-well region (12) in the above-mentioned embodiment, it may be formed in the reverse order.

〔The invention's effect〕

As is clear from the above description, in the method for manufacturing a semiconductor device according to the present invention, since selective oxidation is performed after annealing, the occurrence of crystal defects due to the strain existing in the adhered portion of the oxidation resistant film does not occur. This is effectively avoided, and thus the yield is improved and a highly reliable semiconductor device can be manufactured.

In addition, since the first opening for forming the alignment mark and the second opening for forming the first well region are simultaneously formed by patterning the same resist layer, the conventional method is used. Compared with three masks and eleven steps, the method according to the present invention requires two masks and nine steps. Furthermore, these steps can be carried out without significantly changing the existing equipment, so that it is possible to manufacture a semiconductor device extremely economically.

[Brief description of drawings]

1 (A) to 1 (G) are schematic cross-sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps thereof. FIG. 1 (A) shows a silicon oxide layer and First resist layer forming step, FIG. 1 (B) is a patterning step and first ion implantation step, FIG. 1 (C) is an etching step, and FIG. 1 (D) is a first resist layer removal step. Process, FIG. 1E shows a second resist layer forming / patterning process, and a second ion implantation process,
FIG. 1 (F) is a step of forming an alignment groove, FIG. 1 (G).
Shows the steps of removing the second resist layer, respectively. 2 (A) to 2 (H) are schematic cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device in the order of steps thereof, and FIG. 2 (A) shows formation of a first resist layer. Patterning step, FIG. 2B shows an etching step,
2 (C) is a step of removing the first resist layer, FIG. 2 (D) is a step of forming the second resist layer, and FIG. 2 (E) is a patterning for forming the first well region. Process and first ion implantation process, FIG. 2F is a second resist layer removal process, FIG. 2G is a third resist layer formation / patterning process and second ion implantation process,
FIG. 2H shows a step of removing the third resist layer. 1 ... Silicon substrate 2 ... Silicon oxide layer 3 ... First resist layer 4 ... First opening 5 ... Second opening 7 ... P-well region 8 ... Second resist layer 9 ...... Third opening 10 ...... Fourth opening 12 ...... n well region 13 ...... Alignment groove

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a well region, comprising the steps of forming a film on a semiconductor substrate and forming a first resist layer on the film, and an alignment mark on the first resist layer. For forming a first opening and a first well region used for
And the step of simultaneously forming a first opening and a step of performing first ion implantation through the first opening and the second opening, and using the first resist layer as a mask to selectively remove the coating film. And a step of removing the first resist layer and forming a second resist layer on the entire surface of the exposed coating film and coating removal area, and an alignment mark in the coating removal area by the first opening. Simultaneously forming a third opening portion used for forming the second well region and a fourth opening portion for forming the second well region in the second resist layer, and the third opening portion and the fourth opening portion. A step of performing second ion implantation through the opening, a step of performing etching to form an alignment groove through the third opening, and a step of annealing after removing the second resist layer and the film. impurities A step of activating the region into which is introduced, a step of forming an oxidation resistant film so as to cover at least a part of the well region based on the alignment groove, and a selective oxidation using the oxidation resistant film as a mask. A method of manufacturing a semiconductor device, comprising the steps of: