JPS55102240A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55102240A
JPS55102240A JP895179A JP895179A JPS55102240A JP S55102240 A JPS55102240 A JP S55102240A JP 895179 A JP895179 A JP 895179A JP 895179 A JP895179 A JP 895179A JP S55102240 A JPS55102240 A JP S55102240A
Authority
JP
Japan
Prior art keywords
film
sio
poly
layers
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP895179A
Other languages
Japanese (ja)
Inventor
Hideto Goto
Koji Takemae
Haruo Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP895179A priority Critical patent/JPS55102240A/en
Publication of JPS55102240A publication Critical patent/JPS55102240A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an Si-gate-type MOSFET at a high yield rate by eliminating the problems in forming an SiO2 mask for Si3N4 film etching in the conventional manufacturing method and the cracking in the Si3N4 film at the time of oxidation.
CONSTITUTION: Opening holes 104 and 105 are made in a gate oxide film 103 in p-type Si substrate 101, a poly Si 106 of phosphorus dope is stacked, oxidation is performed, thereby an SiO2 film 107 is made. Then, Si3N4 films 109W111 are fromed by covering with the Si3N4 film, and performing selective etching. Thereafter, the poly Si 106 is transformed into SiO2 112 by wet oxidation, and mutually separated poly Si layers 113 are formed. During this period, n-layers 116 and 117 are formed by diffusing phosphorus from poly Si 113 and 115 through holes 104 and 105, and shallow n-layers 118 and 119 are formed through the gate film. Then, the Si3N4 film 110 is selectively removed. After the poly Si 114 is transformed into SiO2 120, the Si3N4 films 109 and 111 are removed, the SiO2 film 107 is etched out, Al wirings 130 and 131 are provided, thereby the work is accomplished. In this method, the conventional defects can be eliminated, and the device having no wiring breakdown can be obtained at a high yield rate.
COPYRIGHT: (C)1980,JPO&Japio
JP895179A 1979-01-29 1979-01-29 Manufacture of semiconductor device Pending JPS55102240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP895179A JPS55102240A (en) 1979-01-29 1979-01-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP895179A JPS55102240A (en) 1979-01-29 1979-01-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55102240A true JPS55102240A (en) 1980-08-05

Family

ID=11706970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP895179A Pending JPS55102240A (en) 1979-01-29 1979-01-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55102240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02112237A (en) * 1988-10-21 1990-04-24 Matsushita Electron Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02112237A (en) * 1988-10-21 1990-04-24 Matsushita Electron Corp Manufacture of semiconductor device

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