JPS56140662A - Manufacture of field effect semiconductor of insulation gate complementary type - Google Patents

Manufacture of field effect semiconductor of insulation gate complementary type

Info

Publication number
JPS56140662A
JPS56140662A JP4377180A JP4377180A JPS56140662A JP S56140662 A JPS56140662 A JP S56140662A JP 4377180 A JP4377180 A JP 4377180A JP 4377180 A JP4377180 A JP 4377180A JP S56140662 A JPS56140662 A JP S56140662A
Authority
JP
Japan
Prior art keywords
layer
annealed
si3n4
injected
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4377180A
Other languages
Japanese (ja)
Other versions
JPH0312475B2 (en
Inventor
Koji Nomura
Masahiko Ueda
Yasuhiro Funakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4377180A priority Critical patent/JPS56140662A/en
Publication of JPS56140662A publication Critical patent/JPS56140662A/en
Publication of JPH0312475B2 publication Critical patent/JPH0312475B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To obtain C-MOSIC in high integration degree and high performance by a method wherein a poly-Si layer is formed by ion-injection in a single crystalline Si layer above an Si3N4 layer burried in an Si substrate, and after being laser- annealed to be made a single crystal, an MOS transistor is provided. CONSTITUTION:SiO2 12 is selectively mounted on a surface (100) of an N type Si 11, injected with N in order that the N may not pass through the layer 12, annealed in N2 to form the Si3N4 layeres 15, 16. The layer 12 is etched is etched as far as the surfaces of islands 17, 18 of the single crystal, piled up with poly-Si 19 and laser- annealed to form the single layers 20, 21. After an Si3N4 22 is applied to allow the layer 19 to be plasma etched to the prescribed thickness, the selective oxidation is made. Then, the mask 22 is removed to form a B-injected layer 24 over the whole surface, a resist mask is applied to allow P 25 to be injected, and an N-layer 17, a P-layer 27 can be obtained by removing the resist and annealing. Subsequently, the P type MOSFET is formed in the N-region and the N type MOSFET in the P- region to finish by a usual C-MOS forming method. With this construction, the device in the high integration degree which gives rise to no latch-up at all and has the less junction leak can be obtained.
JP4377180A 1980-04-02 1980-04-02 Manufacture of field effect semiconductor of insulation gate complementary type Granted JPS56140662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4377180A JPS56140662A (en) 1980-04-02 1980-04-02 Manufacture of field effect semiconductor of insulation gate complementary type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4377180A JPS56140662A (en) 1980-04-02 1980-04-02 Manufacture of field effect semiconductor of insulation gate complementary type

Publications (2)

Publication Number Publication Date
JPS56140662A true JPS56140662A (en) 1981-11-04
JPH0312475B2 JPH0312475B2 (en) 1991-02-20

Family

ID=12673007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4377180A Granted JPS56140662A (en) 1980-04-02 1980-04-02 Manufacture of field effect semiconductor of insulation gate complementary type

Country Status (1)

Country Link
JP (1) JPS56140662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60127740A (en) * 1983-12-15 1985-07-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO
JPS52113684A (en) * 1976-03-19 1977-09-22 Matsushita Electric Ind Co Ltd Semiconductor device
JPS53110479A (en) * 1977-03-09 1978-09-27 Fujitsu Ltd Production of semiconductor device
JPS5519831A (en) * 1978-07-28 1980-02-12 Toshiba Corp Semiconductor device manufacturing method
JPS55154744A (en) * 1979-05-21 1980-12-02 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS5679472A (en) * 1979-12-04 1981-06-30 Toshiba Corp Preparing method of mos-type semiconductor device
JPS56116627A (en) * 1980-02-20 1981-09-12 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO
JPS52113684A (en) * 1976-03-19 1977-09-22 Matsushita Electric Ind Co Ltd Semiconductor device
JPS53110479A (en) * 1977-03-09 1978-09-27 Fujitsu Ltd Production of semiconductor device
JPS5519831A (en) * 1978-07-28 1980-02-12 Toshiba Corp Semiconductor device manufacturing method
JPS55154744A (en) * 1979-05-21 1980-12-02 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS5679472A (en) * 1979-12-04 1981-06-30 Toshiba Corp Preparing method of mos-type semiconductor device
JPS56116627A (en) * 1980-02-20 1981-09-12 Chiyou Lsi Gijutsu Kenkyu Kumiai Thin film semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60127740A (en) * 1983-12-15 1985-07-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0312475B2 (en) 1991-02-20

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