JPS6028239A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6028239A
JPS6028239A JP13610983A JP13610983A JPS6028239A JP S6028239 A JPS6028239 A JP S6028239A JP 13610983 A JP13610983 A JP 13610983A JP 13610983 A JP13610983 A JP 13610983A JP S6028239 A JPS6028239 A JP S6028239A
Authority
JP
Japan
Prior art keywords
film
regions
electrode
electrodes
psg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13610983A
Other languages
Japanese (ja)
Inventor
Ikuo Kawamata
川又　郁夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13610983A priority Critical patent/JPS6028239A/en
Publication of JPS6028239A publication Critical patent/JPS6028239A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the dissolution of an electrode section by moisture, and to improve the moisture vapor resistance of a device by previously making the film thickness of the electrode section thicker than that of a metal for a wiring when a PSG layer is applied on a semiconductor substrate through an insulating layer and forming an external leading-out electrode on the PSG layer. CONSTITUTION:A thick filed SiO2 film 2 is formed to the peripheral section of a semiconductor substrate 1, source and drain regions 9 are diffused and shaped to the substrate 1 surrounded by the film 2, and a polycrystalline Si gate electrode 8 is formed on the substrate 1 through a gate oxide film 7 while being positioned between these regions. The whole surface is coated with a PSG film 3 and a bonding pad 12 is formed positioned on the film 2, and opening are bored made correspond to the regions 9. Al leading-out electrodes 14 being in contact with the pad 12 and the regions 9 are applied extended on the film 3, but the thickness of the electrodes 14 positioned on the regions 9 is previously made sufficiently thicker than that of the electrode wiring 14 connecting to the electrodes at that time. The whole surface is coated with a cover film 5 through a vapor phase growth method.

Description

【発明の詳細な説明】 本発明は半導体装置にかかシ、特にモールド樹脂封止さ
れた半導体装置の耐湿性を向上させる構造に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for improving the moisture resistance of a semiconductor device, particularly a semiconductor device sealed with a molded resin.

一般にモールド樹脂封入された半導体用パッケージは、
その量産性の良芒およびその低価格のため広く使用され
ている。しかし、他のパッケージ例えばハーメチックシ
ールされたセラミックパッケージに比べ、周囲からの水
分や湿気がモールド樹脂中を浮遊しやすい。そのため浮
遊してきた水分が衆面安定用及び表面形状を緩くする絶
縁膜として使用されている不純物含有ガラス、特にリン
理化ガラス（以下ＰＥＧ膜と称する）と反応してリン酸
となる。このリン酸が配線用金族であるアルミニウムを
溶解してしまい、ついには不良に至る欠点を有し、モー
ルド樹脂封入された牛導体用パッケージの耐湿性を低下
させていた。Generally, semiconductor packages encapsulated in molded resin are
It is widely used because of its mass-producible quality and low price. However, compared to other packages, such as hermetically sealed ceramic packages, moisture from the surroundings tends to float in the mold resin. Therefore, the floating water reacts with impurity-containing glass, especially phosphor chemical glass (hereinafter referred to as PEG film) used as an insulating film for stabilizing the surface and loosening the surface shape, and becomes phosphoric acid. This phosphoric acid dissolves aluminum, which is a metal group for wiring, which has the disadvantage of eventually leading to defects, and reduces the moisture resistance of the package for conductors sealed with molded resin.

この不良に対して半導体装置の表向を緻密なバッジベー
ジ冒ン膜（以後、カバー膜と称する）で被うことによシ
外部から浸透してきた水分とＰＳＧ膜を反応させないよ
うな対策が施されてきた。該対策によシカバー膜で被わ
れた部分の耐湿性は向上した。しかし、カバー膜で被う
ことの出来ない部分特に外部引き出し電極部については
アルミニウムが露出しているためモールド樹脂中を浸透
してきた水分等が原因で溶解してしまう問題が依然とし
て残っている。これを第１図および第２図を用いて説明
する。第１図は従来構造に於けるボンテインクパッド部
の断面図であシ、１はＰ型半導体基板、２は二酸化シリ
コン膜、３はＰＥＧ膜、４は外部引き出し電極、５はカ
バー膜である。この状態はメタライモーシロン後カバー
膜５を形成した段階の断面図である。次に第２図に示す
ように写真蝕刻法により外部引出し電極４上のカバー膜
５にケースの内部リードと電気的接続を行うだめのスル
ーホールを開孔する。この時、カバー膜のエッチャント
によシ、外部引出し電極４のアルミニウムもエツチング
され、膜厚が薄くなると同時に、エツチングがアルミニ
ウムのグレインに沿って進み外部引き出し電極４の下の
ＰＳＧ膜３にまで達するピンホール６が開いてしまう。A countermeasure against this defect was taken by covering the surface of the semiconductor device with a dense badge-base film (hereinafter referred to as a cover film) to prevent the PSG film from reacting with moisture penetrating from the outside. It's here. As a result of this measure, the moisture resistance of the area covered with the SiCover film was improved. However, there still remains the problem that aluminum is exposed in parts that cannot be covered with a cover film, particularly in the external lead-out electrode parts, and thus is dissolved by water that has penetrated into the mold resin. This will be explained using FIGS. 1 and 2. Figure 1 is a cross-sectional view of the bond pad part in a conventional structure, where 1 is a P-type semiconductor substrate, 2 is a silicon dioxide film, 3 is a PEG film, 4 is an external lead electrode, and 5 is a cover film. . This state is a cross-sectional view at the stage where the cover film 5 is formed after metalymosis. Next, as shown in FIG. 2, a through hole for electrical connection to the internal lead of the case is made in the cover film 5 on the external lead electrode 4 by photolithography. At this time, the aluminum of the external lead electrode 4 is also etched by the etchant of the cover film, and the film thickness becomes thinner.At the same time, the etching progresses along the aluminum grains and reaches the PSG film 3 below the external lead electrode 4. Pinhole 6 opens.

外部引き出し電極４上にピンホール６が開いた状態で、
モールド樹脂封入技術によシ組み立てられた半導体装置
は、周囲に存在する水分等がモールド樹脂中を浸透しシ
リコン牛導体表面に達し、外部引き出し寛惚４に開いた
スルーホール６を通シ、ＰＳＧ膜３と反応してしまい。With the pinhole 6 open on the external extraction electrode 4,
In the semiconductor device assembled using mold resin encapsulation technology, moisture present in the surroundings penetrates into the mold resin, reaches the surface of the silicon conductor, and passes through the through hole 6 opened to the external drawer 4, and is then inserted into the PSG. It reacts with membrane 3.

リン酸となシ、外部引き出し電極４のアルミニウムを溶
解してしまい、りいには半導体装置を不良に到らしめて
しまう耐湿性上の欠陥を有していた。When mixed with phosphoric acid, it dissolves the aluminum of the external lead electrode 4, and it has a moisture resistance defect that leads to failure of the semiconductor device.

本発明は、上記不都合を改善し、しいてはモールド樹脂
封入された半導体装置の耐湿性を向上させる構造を提供
するものである。The present invention provides a structure that improves the above-mentioned disadvantages and improves the moisture resistance of a semiconductor device encapsulated in a molded resin.

本発明は半導体基板上に形成された二酸化シリコン族と
、該二酸化シリコン膜上に形成されたリンガラス善と、
該リンガラス層上に形成された外部引き出し電極を有す
る半導体装置において、該外部引き出し電極部の膜厚が
配線用金属の膜厚よりも厚いことを特徴とする半導体装
置である。The present invention provides a silicon dioxide group formed on a semiconductor substrate, a phosphor glass layer formed on the silicon dioxide film,
The present invention is a semiconductor device having an external lead-out electrode formed on the phosphor glass layer, characterized in that the film thickness of the external lead-out electrode portion is thicker than the film thickness of the wiring metal.

以下本発明の詳細な説明する第３図乃至第８図は本発明
一実施例の工程説明図でめυ、次にこれ等の図を参照し
つつ説明する。The present invention will be explained in detail below with reference to FIGS. 3 to 8, which are process explanatory diagrams of one embodiment of the present invention.

第３図は通常の技法を適用し、Ｐ型シリコン牛導体基板
ｌ上にフィールドの二酸化シリコン膜２、絶縁及び段部
のたらしのためのＰＳＧ膜３ゲート酸化膜７、シリコン
ゲート８、ンース領域或いはドレイン領域であるＮ型不
純物等人領域９、ソース領域及びドレイン領域９と引き
出し電極とを接続するためのコンタクト孔１０が形成さ
れた状態を表わしている。FIG. 3 shows a field silicon dioxide film 2, a PSG film 3 for insulation and leveling of steps, a gate oxide film 7, a silicon gate 8, a silicon gate 8, a silicon dioxide film 2, a silicon dioxide film 2, a silicon dioxide film 2, a gate oxide film 7, a silicon gate 8, and a silicon gate 8. This shows a state in which a contact hole 10 for connecting an N-type impurity region 9 which is a region or a drain region, a source region and a drain region 9, and an extraction electrode is formed.

次に第４図に示す如く、例えば、スパッタ蒸着法などに
よシ、およそｂ血程度のアルミニウム１２を全面に形成
し、その後写真蝕刻法によシ、ポンディングパッド部に
のみ、第１のボンデイングパッヱ１２を形成するその状
態を第５図に示す。Next, as shown in FIG. 4, a layer of aluminum 12 having a thickness of approximately 100 ml is formed on the entire surface by, for example, sputter deposition, and then a first layer of aluminum 12 is formed only on the bonding pad portion by photolithography. The state in which the bonding pad 12 is formed is shown in FIG.

しかる後第６図に示す如く、例えばスノくツタ蒸着法な
どによシ、およそｈ血　程度のアルミニウム１３を全面
に形成する。そめ後写真蝕刻法によムンース領域或いは
ドレイン領域からの引き出し電極４４を形成する。この
時該引き出し電極１４を延長し、前記第１のポンディン
グパッド部１２を被うように第２のポンディングパッド
１２Ａを形成する。この状態を第７図に示す。Thereafter, as shown in FIG. 6, a layer of aluminum 13 having a thickness of about 100 mL is formed on the entire surface by, for example, the vine evaporation method. After cooling, an extraction electrode 44 from the moons region or drain region is formed by photolithography. At this time, the extraction electrode 14 is extended to form a second bonding pad 12A so as to cover the first bonding pad portion 12. This state is shown in FIG.

次に第８図に示す如く、例えば気相成長法等によシカパ
ー膜５を形成する。その後写真蝕刻法によシ、該第２の
ポンディングパッド１２Ａ上のカバー族５をエツチング
する。該エツチング時に第２のポンディングパッド１２
Ａのアルミニウムがカバー膜５のエッチャントによシエ
ッチングされるが本発明によるポンディングパッドは第
１のポンディングパッド１２及び第２のポンディングパ
ッド１２Ａの厚膜の２層構造となっておｐ１従来構造の
ポンディングパッドに比べＰＳＧ膜３に達するピンホー
ル６ははるかに開きにくい構造となっている。したがつ
て、本発明による構造を刹する半導体装置をモールド樹
脂封入技術を用いて組み立てた製品は、たとえ外部より
水分が浸透してきても水分はボンデインク゛バッド部に
おいて、ＰＳＧ膜と反応出来ないので、ボ／ディングツ
くラド部のアルミニウムは溶解されず、耐湿性のすぐれ
た半導体装置ヲ得る仁とが出来る。Next, as shown in FIG. 8, a capacitor film 5 is formed by, for example, a vapor phase growth method. Thereafter, the cover group 5 on the second bonding pad 12A is etched by photolithography. During the etching, the second bonding pad 12
Although the aluminum of A is etched by the etchant of the cover film 5, the bonding pad according to the present invention has a two-layer structure of a thick film of the first bonding pad 12 and the second bonding pad 12A. The pinhole 6 reaching the PSG film 3 has a structure that is much more difficult to open than the conventionally structured bonding pad. Therefore, in a product in which a semiconductor device with a structure according to the present invention is assembled using mold resin encapsulation technology, even if moisture penetrates from the outside, the moisture cannot react with the PSG film in the bonded ink pad. The aluminum in the board/rad portion is not melted, resulting in a semiconductor device with excellent moisture resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は従来技術の半導体装置を示す断面図
でおシ、第３図及第８図は各々本発明の実施例を工程順
に示す断面図でめる。 なお図に於いて、１・・・・・・Ｐ型半導体基板、２・
・・・・・二酸化シリコン膜、３・・・・・・ＰＳＧｇ
、４・・・・・・外部引き出し電極、５・・・・・・カ
バー膜、６・・・・・・ピンホール、７・・・・・・ゲ
ート酸化層、８・・・・・・シリコンゲート、９・・・
・・・ソース領域或いはドレイン領域でおるＮ型不純物
導入領域、１０・・・・・・コンタクト孔、１１・・・
・・・アルミニウム層、１２・・・・・・第１のポンデ
ィングパッド、１２Ａ・・・・・・第２のポンディング
パッド、１３・・・・・・アルミニウム層、１４・・・
・・・ソース領域或いはドレイン領域からの引き出し電
極、である。 筋　！　国 力　２　閃1 and 2 are cross-sectional views showing a conventional semiconductor device, and FIGS. 3 and 8 are cross-sectional views showing an embodiment of the present invention in the order of steps. In the figure, 1...P-type semiconductor substrate, 2...
...Silicon dioxide film, 3...PSGg
, 4...External extraction electrode, 5...Cover film, 6...Pinhole, 7...Gate oxide layer, 8... Silicon Gate, 9...
. . . N-type impurity doped region in the source region or drain region, 10 . . . Contact hole, 11 . . .
...Aluminum layer, 12...First bonding pad, 12A...Second bonding pad, 13...Aluminum layer, 14...
...This is an extraction electrode from the source region or drain region. logic ! National power 2 flash

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された絶縁層と、該絶縁層上に形成
されたリンガラス層と、該リンカラス層上に形成された
外部引出し電極を有し、該外部引き出し電極部の膜厚が
配線用金属の膜厚よりも厚いことを特徴とする半導体装
置。It has an insulating layer formed on a semiconductor substrate, a phosphor glass layer formed on the insulating layer, and an external lead electrode formed on the link glass layer, and the film thickness of the external lead electrode part is for wiring. A semiconductor device characterized by being thicker than a metal film.
JP13610983A 1983-07-26 1983-07-26 Semiconductor device Pending JPS6028239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13610983A JPS6028239A (en) 1983-07-26 1983-07-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13610983A JPS6028239A (en) 1983-07-26 1983-07-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6028239A true JPS6028239A (en) 1985-02-13

Family

ID=15167497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13610983A Pending JPS6028239A (en) 1983-07-26 1983-07-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6028239A (en)

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