JPH0518259B2 - - Google Patents
Info
- Publication number
- JPH0518259B2 JPH0518259B2 JP58237358A JP23735883A JPH0518259B2 JP H0518259 B2 JPH0518259 B2 JP H0518259B2 JP 58237358 A JP58237358 A JP 58237358A JP 23735883 A JP23735883 A JP 23735883A JP H0518259 B2 JPH0518259 B2 JP H0518259B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- conductor
- groove
- insulating layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 15
- 230000010354 integration Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体集積回路に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor integrated circuit.
〔発明の技術的背景〕
従来、半導体集積回路として例えば、第１図に
示す構造のものが使用されている。図中１は、半
導体基板である。半導体基板１の所定領域には、
溝２が形成されている。溝２の内周面及び半導体
基板１の表面には、薄肉の絶縁膜３が形成されて
いる。半導体基板１上の絶縁膜３の表面には、溝
２を埋めるようにして所定パターンの導体４が形
成されている。絶縁膜３上には、露出した導体４
の表面を覆うようにして絶縁層５が形成されてい
る。絶縁層５には、導体４に通じる窓６が形成さ
れている。絶縁層５上には、この窓６を介して導
体４に接続する配線層７が形成されている。この
ような構造では、導体４は埋め込まれた配線、ゲ
ート、さらには絶縁膜３を含めて素子分離領域と
なる。[Technical Background of the Invention] Conventionally, a semiconductor integrated circuit having the structure shown in FIG. 1, for example, has been used. 1 in the figure is a semiconductor substrate. In a predetermined area of the semiconductor substrate 1,
A groove 2 is formed. A thin insulating film 3 is formed on the inner peripheral surface of the groove 2 and on the surface of the semiconductor substrate 1. A conductor 4 having a predetermined pattern is formed on the surface of the insulating film 3 on the semiconductor substrate 1 so as to fill the groove 2 . There is an exposed conductor 4 on the insulating film 3.
An insulating layer 5 is formed to cover the surface. A window 6 communicating with the conductor 4 is formed in the insulating layer 5 . A wiring layer 7 is formed on the insulating layer 5 to be connected to the conductor 4 through the window 6. In such a structure, the conductor 4 including the buried wiring, the gate, and further the insulating film 3 becomes an element isolation region.
このように構成された半導体集積回路１０で
は、溝２を埋める導体４を半導体基板１上に引出
すと共に、これに所定のパターニングを施して配
線層７と旨く接続するための工程を必要とする。
このため、製造工程が複雑になると共に、配線層
７の周辺領域の構造が複雑になり、集積度の向上
を達成できない問題があつた。
The semiconductor integrated circuit 10 configured in this manner requires a step of drawing out the conductor 4 filling the trench 2 onto the semiconductor substrate 1 and subjecting it to a predetermined patterning to successfully connect it to the wiring layer 7.
For this reason, the manufacturing process becomes complicated, and the structure of the peripheral region of the wiring layer 7 becomes complicated, resulting in the problem that an improvement in the degree of integration cannot be achieved.
本発明は、集積度の向上及び製造工程の簡略化
を達成した半導体集積回路を提供することをその
目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that achieves an improved degree of integration and a simplified manufacturing process.
本発明は、半導体基板に埋込まれた導体の露出
端部の周囲に不純物領域を形成して導体に直接配
線層を接続するようにしたことにより、集積度の
向上及び製造工程の簡略化を達成した半導体集積
回路である。
The present invention improves the degree of integration and simplifies the manufacturing process by forming an impurity region around the exposed end of a conductor embedded in a semiconductor substrate and connecting a wiring layer directly to the conductor. This is a semiconductor integrated circuit that has achieved this goal.
以下、本発明の実施例に付いて図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
第２図は、本発明の一実施例の断面図である。
図中１１は、Ｐ導電型の半導体基板である。半導
体基板１１の所定領域には、溝１２が形成されて
いる。溝幅L1は、例えば2μ以下に設定されてい
る。溝１２の内壁面には、薄肉の絶縁膜１３が形
成されている。絶縁膜１３の膜厚は、100乃至
2000Åの範囲で設定されている。溝１２内には、
半導体基板１１の表面と露出面を略同一平面にす
るようにして導体１４が充填されている。導体１
４は、不純物をドープした多結晶シリコン、シリ
サイド、金属等で形成されている。導体１４の露
出面近傍の半導体基板１１の表面領域には、Ｎ導
電型の不純物領域１５が、所定の拡散深さで半導
体基板１１の表面から内部に向かつて延在してい
る。導体１４および不純物領域１５の表面を含む
半導体基板１１表面には、絶縁層１６が形成され
ている。絶縁層１６には、導体１４の露出面及び
不純物領域１５の一部分を露出するようにしてコ
ンタクトホール１７が開口されている。絶縁層１
６の表面には、コンタクトホール１７を介して導
体１４に接続する配線層１８が形成されている。
配線層１８は、アルミニウム、Ｎ型不純物をドー
プした多結晶シリコン、シリサイド、金属等で形
成されている。 FIG. 2 is a cross-sectional view of one embodiment of the present invention.
11 in the figure is a P conductivity type semiconductor substrate. A groove 12 is formed in a predetermined region of the semiconductor substrate 11 . The groove width L1 is set to, for example, 2μ or less. A thin insulating film 13 is formed on the inner wall surface of the groove 12 . The thickness of the insulating film 13 is 100 to 100.
It is set in the range of 2000Å. In the groove 12,
The conductor 14 is filled so that the surface of the semiconductor substrate 11 and the exposed surface are substantially on the same plane. Conductor 1
4 is made of impurity-doped polycrystalline silicon, silicide, metal, or the like. In the surface region of the semiconductor substrate 11 near the exposed surface of the conductor 14, an N-conductivity type impurity region 15 extends inward from the surface of the semiconductor substrate 11 at a predetermined diffusion depth. An insulating layer 16 is formed on the surface of the semiconductor substrate 11 including the surfaces of the conductor 14 and the impurity region 15 . A contact hole 17 is formed in the insulating layer 16 so as to expose the exposed surface of the conductor 14 and a portion of the impurity region 15 . Insulating layer 1
A wiring layer 18 connected to the conductor 14 via a contact hole 17 is formed on the surface of the semiconductor device 6 .
The wiring layer 18 is made of aluminum, polycrystalline silicon doped with N-type impurities, silicide, metal, or the like.
ここで、溝１２の形状は、第３図に示す如く、
帯び状に長いものであつても良いし、正方形のも
のであつても良い。不純物領域１５は、溝１２の
周面に充分に密着していることがの望ましい。コ
ンタクトホール１７の開口部の幅L2は、不純物
領域１５の表面領域の幅L3よりも小さく設定さ
れている。 Here, the shape of the groove 12 is as shown in FIG.
It may be long like a band or it may be square. It is desirable that the impurity region 15 is in close contact with the circumferential surface of the groove 12. The width L 2 of the opening of the contact hole 17 is set smaller than the width L 3 of the surface region of the impurity region 15 .
このように構成された半導体集積回路２０によ
れば、導体１４の露出面は半導体基板１１の表面
と略同一平面に設定されており、この導体１４の
露出面にコンタクトホール１７を介して配線層１
８が直接接続されている。その結果、配線層１８
の周辺領域の構造を簡単なものにして集積度を向
上させることができる。また、配線層１８と導体
１４との電気的な接続は、不純物領域１５を形成
したことによつて確実に行われる。即ち、もし不
純物領域１５が存在しないとすると、配線層１８
がＰ型半導体基板１１に直接コンタクトしてしま
い、絶縁膜１３を形成したことの意味が全くなく
なつてしまう。しかし、本発明では不純物領域１
５の存在によつて、が形成されていることによつ
て、配線層１８とＰ型半導体基板１１との間の電
気的接続を防止し、配線層１８を導体１４にのみ
確実に接続することができる。即ち、不純物領域
１５はガードリングとしての機能を有する。しか
も、不純物領域１５の形成及びコンタクトホール
１７の開口は、集積回路の形成のために行われる
拡散工程や写真蝕刻工程を利用して容易に行なう
ことができる。その結果、製造工程を簡略にする
ことができる。また導体１４、絶縁膜１３及び半
導体基板１１からなるMOS構造が形成されるか
ら、導体（電極）１４に配線層１８を介して電位
を印加することにより、これをMOSキヤパシタ
として用いることができる。更に、帯状の長い溝
１２を形成し、コンタクトホール１７を介して該
溝内の導体１４に接続した二つ以上の配線層１８
を形成すれば、導体１４は、これら配線層１８の
間を接続するための埋め込まれた配線となる。 According to the semiconductor integrated circuit 20 configured in this way, the exposed surface of the conductor 14 is set to be substantially flush with the surface of the semiconductor substrate 11, and a wiring layer is formed on the exposed surface of the conductor 14 via the contact hole 17. 1
8 are directly connected. As a result, the wiring layer 18
The degree of integration can be improved by simplifying the structure of the peripheral area. Further, the electrical connection between the wiring layer 18 and the conductor 14 is ensured by forming the impurity region 15. That is, if the impurity region 15 does not exist, the wiring layer 18
will come into direct contact with the P-type semiconductor substrate 11, and the purpose of forming the insulating film 13 will be completely lost. However, in the present invention, the impurity region 1
5 prevents electrical connection between the wiring layer 18 and the P-type semiconductor substrate 11 and reliably connects the wiring layer 18 only to the conductor 14. I can do it. That is, impurity region 15 has a function as a guard ring. Furthermore, the formation of the impurity region 15 and the opening of the contact hole 17 can be easily performed using a diffusion process or a photolithography process used for forming an integrated circuit. As a result, the manufacturing process can be simplified. Further, since a MOS structure consisting of the conductor 14, the insulating film 13, and the semiconductor substrate 11 is formed, by applying a potential to the conductor (electrode) 14 via the wiring layer 18, it can be used as a MOS capacitor. Further, a long strip-shaped groove 12 is formed, and two or more wiring layers 18 are connected to the conductor 14 in the groove through a contact hole 17.
If formed, the conductor 14 becomes a buried wiring for connecting between these wiring layers 18.
以上説明した如く、本発明に係る半導体集積回
路によれば、集積度の向上及び製造工程の簡略化
を達成することができるものである。
As described above, according to the semiconductor integrated circuit according to the present invention, it is possible to improve the degree of integration and simplify the manufacturing process.
第１図は、従来の半導体集積回路の断面図、第
２図は、本発明の一実施例の断面図、第３図は、
同実施例の要部を示す説明図である。
１１……半導体基板、１２……溝、１３……絶
縁膜、１４……導体、１５……不純物領域、１６
……絶縁層、１７……コンタクトホール、１８…
…配線層、２０……半導体集積回路。
FIG. 1 is a sectional view of a conventional semiconductor integrated circuit, FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is a sectional view of a conventional semiconductor integrated circuit.
FIG. 3 is an explanatory diagram showing main parts of the same embodiment. 11... Semiconductor substrate, 12... Groove, 13... Insulating film, 14... Conductor, 15... Impurity region, 16
...Insulating layer, 17...Contact hole, 18...
...Wiring layer, 20...Semiconductor integrated circuit.
Claims (1)
所定領域に形成された溝と、該溝内に充填された
導体であつて、その露出面と前記半導体基板の表
面とが略同一平面になるように設けられた導体
と、該導体の露出面を除く周面を包むようにして
前記溝の内周面に形成された絶縁膜と、前記溝の
近傍に前記半導体基板の第一導電型領域が露出し
ないように、前記溝を取り囲んで前記半導体基板
の表面に形成された第二導電型の不純物領域と、
前記半導体基板上に形成され且つ前記導体の露出
面に通じる窓を有する絶縁層と、該窓を介して前
記導体および前記不純物領域に接続し、且つ前記
半導体基板の第一導電型領域には接続しないよう
に前記絶縁層上に形成された配線層とを具備する
ことを特徴とする半導体集積回路。 ２ 前記溝は、半導体基板の所定領域に帯状に形
成されている特許請求の範囲第１項に記載の半導
体集積回路。 ３ 前記窓が複数個形成されている特許請求の範
囲第２項に記載の半導体集積回路。[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, a groove formed in a predetermined region of the semiconductor substrate, and a conductor filled in the groove, the exposed surface and the surface of the semiconductor substrate. an insulating film formed on the inner circumferential surface of the groove so as to surround the circumferential surface of the conductor except for the exposed surface; a second conductivity type impurity region formed on the surface of the semiconductor substrate surrounding the groove so that the first conductivity type region is not exposed;
an insulating layer formed on the semiconductor substrate and having a window communicating with the exposed surface of the conductor; and an insulating layer connected to the conductor and the impurity region through the window and connected to the first conductivity type region of the semiconductor substrate. and a wiring layer formed on the insulating layer so as to prevent the insulating layer from being damaged. 2. The semiconductor integrated circuit according to claim 1, wherein the groove is formed in a band shape in a predetermined region of the semiconductor substrate. 3. The semiconductor integrated circuit according to claim 2, wherein a plurality of the windows are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23735883A JPS60130163A (en) | 1983-12-16 | 1983-12-16 | Semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23735883A JPS60130163A (en) | 1983-12-16 | 1983-12-16 | Semiconductor ic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60130163A JPS60130163A (en) | 1985-07-11 |
| JPH0518259B2 true JPH0518259B2 (en) | 1993-03-11 |
Family
ID=17014206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23735883A Granted JPS60130163A (en) | 1983-12-16 | 1983-12-16 | Semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60130163A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0691154B2 (en) * | 1985-10-22 | 1994-11-14 | 日本電気株式会社 | Semiconductor device |
| US4939567A (en) * | 1987-12-21 | 1990-07-03 | Ibm Corporation | Trench interconnect for CMOS diffusion regions |
| US5293512A (en) * | 1991-02-13 | 1994-03-08 | Nec Corporation | Semiconductor device having a groove type isolation region |
| EP0603461A3 (en) * | 1992-10-30 | 1996-09-25 | Ibm | Formation of 3-Dimensional silicon silicide structures. |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5681968A (en) * | 1979-12-07 | 1981-07-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS583261A (en) * | 1981-06-29 | 1983-01-10 | Fujitsu Ltd | Manufacture of vertical buried capacitor |
-
1983
- 1983-12-16 JP JP23735883A patent/JPS60130163A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5681968A (en) * | 1979-12-07 | 1981-07-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS583261A (en) * | 1981-06-29 | 1983-01-10 | Fujitsu Ltd | Manufacture of vertical buried capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60130163A (en) | 1985-07-11 |
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