JP3264402B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a substrate potential applying structure in an SOI semiconductor device.

[0002]

2. Description of the Related Art A plurality of single crystal island-shaped semiconductor regions which are disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and whose side surfaces are in contact with a sidewall isolation insulating region; In a conventional semiconductor device having a so-called SOI structure having an interlayer insulating film disposed on a substrate, it is customary to provide electrodes on the entire back surface of the substrate in order to apply the substrate potential. There are problems such as the necessity of the point, and the fact that the entire substrate is at the same potential and a predetermined bias potential cannot be applied only to a certain portion of the substrate.

In order to solve this problem, Japanese Patent Laid-Open No.
Japanese Patent No. 94076 discloses that a connection hole is formed by forming an element isolation insulating film (field insulating film) composed of a side wall isolation insulating region and a buried insulator layer and an interlayer insulating film thereover at once. Through this, the wiring for applying the substrate potential on the interlayer insulating film is connected to the substrate.

[0004]

However, in the substrate connection method disclosed in the above publication, in this case, the depth of the connection hole is generally referred to as the field insulating film (the side wall isolation insulating region and the buried insulator layer immediately below it). This is also the sum of the thicknesses of the field insulating film and the interlayer insulating film, which is about 1 μm or more.

That is, in a semiconductor device having an SOI structure,
Since the buried insulator layer exists which is relatively thick (the parasitic capacitance between the substrates increases when the thickness is small), the depth of the opening for applying the substrate potential is increased by at least that much. The step for disconnecting the wiring for applying the substrate potential is likely to occur. The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having an SOI structure capable of suppressing disconnection of a wiring for applying a substrate potential.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of single crystal island-shaped semiconductor regions disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and having side surfaces in contact with side wall isolation insulating regions. An interlayer insulating film disposed on the island-shaped semiconductor region and the sidewall isolation insulating region; a connection hole opened in the interlayer insulating film and the buried insulator layer; And a wiring for applying a substrate potential filled in the connection hole and provided in the connection hole,
The connection hole comprises an outer hole opened in the island-shaped semiconductor region and a buried insulator layer immediately below the island-shaped semiconductor region, and an inner hole opened in the interlayer insulating film filled in the outer hole, and A wiring for applying a potential is connected to the substrate through the inner hole.

According to a second aspect of the present invention, there is provided a semiconductor device having a plurality of single crystal island-shaped semiconductor regions disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and having side surfaces in contact with side wall isolation insulating regions; An interlayer insulating film provided on the region and the sidewall isolation insulating region; a connection hole opened in the interlayer insulating film and the buried insulator layer; and a connection hole provided on the interlayer insulating film. In a semiconductor device having a wiring for applying a substrate potential filled in a hole, the connection hole has an outer hole opened in the side wall isolation insulating region and a buried insulator layer immediately below the insulating film, and the outer hole is filled in the outer hole. Wherein the wiring for applying the substrate potential is connected to the substrate through the inner hole.

[0008]

The present invention relates to an SOI semiconductor device, wherein the bottom surface of each island-like semiconductor region is formed by a buried insulator layer.
The side surface is insulated and separated by the side wall insulating region. The wiring provided on the surface of the island-shaped semiconductor region is insulated and separated from each island-shaped semiconductor region by an interlayer insulating film.

In the semiconductor device of the first invention, an inner hole is formed by opening an interlayer insulating film filled in an outer hole opened in the island-shaped semiconductor region and a buried insulator layer immediately below the island-shaped semiconductor region. Wiring is connected to the substrate through this inner hole. In the semiconductor device according to the second aspect of the present invention, an inner hole is formed by opening an interlayer insulating film filled in an outer hole opened in a side wall isolation insulating region and a buried insulator layer immediately therebelow, and a wiring for applying a substrate potential is formed. Is connected to the substrate through this inner hole.

That is, according to these two inventions, the connection hole for applying the substrate potential is constituted by the two-stage opening of the outer hole and the inner hole, so that the connection hole for applying the substrate potential in the conventional SOI semiconductor device described above. As a result, the level difference is significantly reduced, and as a result, disconnection of the level difference of the wiring can be prevented.

[0011]

【Example】

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. A single-crystal silicon layer (single-crystal island-like semiconductor region according to the present invention, hereinafter also referred to as SOI layer) 3 is formed on a silicon substrate 1 via a buried oxide film (buried insulator layer according to the present invention) 2, The SOI layer 3 includes a gate insulating film 4, a gate electrode 5,
A MOSFET including an interlayer insulating film 6 and a wiring 7 is formed. Here, the interlayer insulating film 6 and the silicon substrate 1 are in contact with each other at a first connection hole (outer hole in the present invention) 8 formed inside the SOI layer (island-shaped semiconductor region) 3A where no MOSFET is formed. . Further, a second opening formed in the interlayer insulating film 6 and located inside the first connection hole 8 is formed.
The wiring 7 </ b> A and the silicon substrate 1 are in contact with each other at the connection hole (inner hole according to the present invention) 9.

In this case, the step of the first connection hole 8 is d ₂ + d ₃ . d ₂ corresponds to the thickness of the SOI layer 3A and is usually 100 nm or less, and d ₃ is the buried oxide film 2
Since the thickness is usually about 100 to 400 nm, the value of d ₂ + d ₃ is about 500 nm or less, and this step is almost equal to or less than the step due to the gate electrode of the MOSFET. After the first connection hole 8 is formed, the step of the surface of the interlayer insulation film 6 on the step of the connection hole 8 is reduced by the reflow treatment of the interlayer insulating film 6 formed on the step. The step of the provided wiring 7A is greatly reduced, and the disconnection of the step is prevented.

Next, the step d ₁ in the second connection hole 9 is a step due to the thickness of the interlayer insulating film 6 and has exactly the same shape as the step in the contact hole 11 of the MOSFET. But there is no disconnection. Hereinafter, a manufacturing process of the above-described device will be described with reference to FIGS. First, as shown in FIG. 2, a single crystal silicon layer is formed on a silicon substrate 1 via a buried oxide film 2 by a known method, and a predetermined region of the single crystal silicon layer is formed by, for example, LOCOS oxidation.
The gate insulating film 4 and the gate electrode 5 are formed in this order by forming 0 and the remaining portions as single crystal silicon layers (island-shaped semiconductor regions) 3 and 3A. The buried oxide film 2 and the sidewall isolation insulating region 10 immediately above the buried oxide film 2 are collectively referred to as an element isolation insulating film (field oxide film) 12.

Next, as shown in FIG. 3, the single-crystal silicon layer 3A and the buried oxide film 2 including the region where the second connection hole is to be formed and wider than this region are formed by ordinary photolithography and etching techniques. The first connection hole 8 is formed by etching and the surface of the silicon substrate 1 is exposed. Thereafter, although not shown in the figure, when the side wall for the gate electrode is formed, the side wall is also formed at the step portion by the first connection hole 8 at the same time.

Next, as shown in FIG. 4, when the impurity 13 'forming the source / drain of the MOSFET of the same conductivity type as the substrate formed in the single crystal silicon layer 3 is ion-implanted, the first connection hole is formed. At the same time, the impurity 13 'is ion-implanted into the surface of the silicon substrate 1 exposed by
A source / drain region 13 and a high concentration impurity region 14 are formed. At this time, if a thin oxide film is formed on the surface of the source / drain region 13, the first connection hole 8
An oxide film is similarly formed on the surface portion of the silicon substrate 1 exposed by the above.

Next, as shown in FIG. 5, after the interlayer insulating film 6 is formed, a heat treatment is performed to reflow the interlayer insulating film 6 so as to make the surface smooth and to make the source / drain regions 13 and the high concentration Activate impurity 13 ′ ion-implanted into impurity 14. After that, simultaneously with forming the contact hole 11 in the single crystal silicon layer 3, the second connection hole 9 is formed inside the first connection hole 8 to expose the surface of the silicon substrate 1 again. Therefore, the interlayer insulating film 6 is preferably made of phosphorus glass, but may be a CVD silicon oxide film.

Next, as shown in FIG. 1, by forming wirings 7 and 7A, the structure shown in FIG. 1 is completed. According to the present embodiment, in a semiconductor device having an SOI structure, a plurality of steps are provided in a connection hole for connecting a wiring for applying a substrate potential on an interlayer insulating film to a substrate, thereby preventing disconnection of the wiring. Can be.

Further, in order to form a good electrical contact, it is necessary to dope the surface of the substrate in contact with the wiring with a high concentration of impurities. The manufacturing process can be simplified because the process is performed simultaneously with the impurity doping process for the drain and the like. (Embodiment 2) A second embodiment of the present invention will be described with reference to FIG.

In this embodiment, an element isolation insulating film (field isolation insulating film) comprising a buried insulator layer 2 and a sidewall isolation insulating region 10 formed by LOCOS-oxidizing a single crystal silicon layer on the buried insulator layer 2 The first embodiment differs from the first embodiment in that the first connection hole 8A is formed by opening the oxide film 12. The level difference dd ₂ in the first connection hole 8A in the present embodiment corresponds to the thickness (dd ₂ ) of the element isolation insulating film 12;
reducing the value of d ₂ increases the parasitic capacitance of the gate electrode wiring, the operation speed of the device slows down, leading to problems such as power consumption increases, the value of dd ₂ d ₂ + d ₃
Cannot be smaller than the value of. Therefore, the step due to the first connection hole 8A in this embodiment is larger than the step due to the first connection hole 8 in the first embodiment. However, the step of the connection hole of the conventional structure shown in FIG.
2 Given that the sum of the thickness (D ₂₎ and the thickness of the interlayer insulating film 6 (buried insulator layer 2 and the sidewall isolation region 10) (D _1), realizing remarkable step difference reduction Can be
Disconnection can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device of FIG. 1;

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device of FIG. 1;

FIG. 6 is a sectional view showing another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional device structure.

[Explanation of symbols]

1 is a silicon substrate (semiconductor substrate), 2 is a buried oxide film (buried insulator layer), 3A is a polycrystalline silicon layer (island-shaped semiconductor region), 6 is an interlayer insulating film, 7A is a wiring, and 8 is a first Connection holes (outer holes), 9 are second connection holes (inner holes), and 12 is an element isolation insulating region (sidewall insulating region and a buried insulator layer immediately below it).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/822 H01L 27/04 H01L 27/12

Claims (2)

(57) [Claims] A plurality of single-crystal island-shaped semiconductor regions disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and having a side surface in contact with a sidewall-isolated insulating region; the island-shaped semiconductor region and the sidewall-isolated insulating region; An interlayer insulating film disposed on the region, a connection hole opened in the interlayer insulating film and the buried insulator layer,
A semiconductor device provided on the interlayer insulating film and having a wiring for applying a substrate potential filled in the connection hole, wherein the connection hole is formed in the island-shaped semiconductor region and a buried insulator layer immediately below the island-shaped semiconductor region. And an inner hole opened in the interlayer insulating film filled in the outer hole, wherein the wiring for applying the substrate potential is connected to the substrate through the inner hole. Semiconductor device. 2. A plurality of single-crystal island-shaped semiconductor regions disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and having a side surface in contact with a side-wall isolation region, the island-shaped semiconductor region and the side-wall isolation region. An interlayer insulating film disposed on the region, a connection hole opened in the interlayer insulating film and the buried insulator layer,
A semiconductor device provided on the interlayer insulating film and provided with a wiring for applying a substrate potential filled in the connection hole, wherein the connection hole is formed in the side wall isolation insulating region and a buried insulator layer immediately therebelow. And an inner hole opened in the interlayer insulating film filled in the outer hole, wherein the wiring for applying the substrate potential is connected to the substrate through the inner hole. Semiconductor device.