JP3031137B2 - Insulator-isolated semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating semiconductor device.

[0002]

2. Description of the Related Art Conventionally, an insulator-isolated semiconductor in which a semiconductor element is formed in an island-like semiconductor region whose side is insulated and isolated by a trench buried region formed by a pair of insulator partition walls and a polysilicon trench buried region therebetween. Devices are known. In this kind of insulator-separated semiconductor device, in order to suppress the increase in crystal defects due to the above-described insulator burying , for example, a crystal defect suppressing region ( Usually, the following is N-type, as N type crystalline defect suppression region) single crystal territory such as
It is known to interpose a zone .

[0003]

In the case of employing the above-mentioned insulator-separated semiconductor device having a single-crystal region , when a multilayer wiring is employed, it is naturally necessary to connect the lower-layer electrode wiring and the upper-layer electrode wiring through via holes. Therefore, single crystal
The insulator separating the semiconductor device of the conventional multi-layer wiring system having no space, by arranging the via hole on special idle region not forming a semiconductor device, a via hole the influence of irregularities, such as opening immediately above the semiconductor element Care is taken not to adversely affect the parts.

However, the provision of such an idle region has a problem that a wiring layout is restricted and a degree of integration of a chip is reduced. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an insulator-separated semiconductor device that can solve problems such as restriction on wiring layout and reduction in the degree of integration of a chip.

[0005]

According to a first aspect of the present invention, there is provided an insulator-isolated semiconductor device in which side surfaces are insulated and separated by a pair of insulator partition walls and a trench buried region including a polysilicon trench buried region therebetween, and are regularly arranged. A plurality of island-shaped semiconductor regions each having a built-in element therein, and a single-crystal region surrounding each of the island-shaped semiconductor regions with the trench buried region interposed therebetween.
A region, a lower electrode wiring extending over the island-shaped semiconductor region, the polysilicon trench filling region, and the single crystal region via an insulating film, and the lower electrode wiring only above the single crystal region. comprising a via hole is opened in the interlayer insulating film, extending on the interlayer insulating film, an upper layer electrode wiring connected to the lower electrode wiring through the via hole, before
The surface of the insulating film immediately above the single crystal region is filled with the trench.
Is formed flat with respect to the surface of the insulating film immediately above the installation region.
It is characterized in that there.

A semiconductor device according to a second aspect of the present invention is a semiconductor device in which side surfaces are insulated and separated regularly by a trench buried region comprising a pair of insulator partition walls and a polysilicon groove buried region therebetween, and an element is provided therein. A plurality of island-shaped semiconductor regions, a single crystal region surrounding each of the island-shaped semiconductor regions with the trench buried region interposed therebetween, the island-shaped semiconductor region, the polysilicon trench-filled region, and the single crystal.
A lower electrode wiring extending over the region via an insulating film, and the single crystal sandwiched between the pair of adjacent island-shaped semiconductor regions
A via hole opened in the interlayer insulating film on the lower electrode wiring over the region and the pair of trench buried regions on both sides thereof; and a via hole extending on the interlayer insulating film and extending through the via hole to the lower electrode wiring. An upper-layer electrode wiring to be connected, and the insulating film table immediately above the single-crystal region.
The surface is opposite to the surface of the insulating film immediately above the trench buried region.
It is characterized by being formed flat .

In a preferred aspect, the insulating film is
The surface portion of the single crystal region and the polysilicon trench filling region
Including the field oxide film formed by oxidizing the surface
I have.

[0008]

According to the first aspect of the present invention, a single crystal sandwiched between a pair of adjacent island-shaped active element cell regions is provided.
Only Oite over the regions, to a via hole. By doing so, it is not necessary to set the idle region immediately below the via hole region unlike the conventional case, and the degree of integration of the chip does not decrease. In addition, since the single crystal region exists vertically and horizontally surrounding each island-shaped semiconductor region, there is no restriction on the layout, there is no need to uselessly route wiring to the via hole above the idle region as in the conventional case, and a simple wiring An insulator-isolated semiconductor device having a layout and a high degree of integration can be realized.

Furthermore, since no via hole is opened above the island-shaped semiconductor region and the trench buried region, the connection reliability of the via hole does not decrease due to the influence of the unevenness of the surface of the island-shaped semiconductor region and the trench buried region. Furthermore,
Insulation over the single crystal region above which a via hole is formed
The surface of the film is insulated on the adjacent trench buried area
Since it is formed flat against the surface of the film,
There is no need to widen the single crystal region just below
In a buried region type insulator isolation semiconductor device,
Integration degree can be improved while ensuring connection reliability
You. The via hole of the second invention is opened over a single crystal region sandwiched between the pair of adjacent island-shaped active element cell regions and a pair of trench buried regions on both sides thereof.

[0010] In this case, the following effects can be obtained in addition to the effects of the first invention. That is, the width of the via hole even by reducing the width of the single crystal region has a wider than conventional by the width of the sides of the trench buried region, further thereon, a single binding
The surface of the insulating film on the crystalline region is
Since it is formed flat with respect to the surface of the insulating film on the installation region, it is possible to improve the degree of integration while solving problems such as an increase in via hole resistance and a decrease in connection reliability.

Since the via hole is not opened above the island-shaped semiconductor region, the influence of the unevenness of the interlayer insulating film for each lower electrode wiring and contact opening on the island-shaped semiconductor region is affected by the via hole and the upper layer electrode which fills the via hole. It is possible to improve the reliability of connection (prevention of disconnection of step) and prevent short-circuit without reaching the wiring. That is, since the upper electrode wiring necessarily has a step at the opening end of the via hole, near the opening end of the via hole,
It is preferable to avoid unevenness of the interlayer insulating film in order to reduce disconnection of a step.

[0012]

[0013]

【Example】

(Embodiment 1) An embodiment of a process for manufacturing an insulator-isolated semiconductor device according to the present invention will be described below with reference to FIGS.
After mirror polishing is performed on one main surface of the first P ^- type single crystal silicon substrate 1, thermal oxidation is performed to form an insulating film (silicon oxide film) 2. Then, the first silicon substrate 1
A second surface having a mirror-polished main surface on the surface of the insulating film 2 side;
The single-crystal silicon substrate 3 is closely adhered and heated under a sufficiently clean atmosphere, and is integrally joined so as to sandwich the insulating film 2 between the respective silicon substrates 1 and 3. As a result, an SOI substrate formed by bonding the second silicon substrate 3 to the first silicon substrate 1 via the insulating film 2 is manufactured (FIG. 1).
reference). In FIG. 1, before applying the joining 4 second N ^-
N-type high-concentration impurity (Sb) layer formed by doping from the surface of the silicon substrate 3.

Next, a pad oxide film 8a is formed on the surface on the side of the second silicon substrate 3 by thermal oxidation, and a Si ₃ N ₄ film 9 as a first insulating layer and a second insulating An SiO ₂ film 10 as a layer is sequentially deposited by a CVD method, and an annealing process at 1000 ° C. is performed to densify the SiO ₂ film 10. Here, to form the Si ₃ N ₄ film 9, Si ₃ N ₄ during etching removal of the SiO ₂ film 10
This is to prevent the oxide film such as the pad oxide film 8a or the insulating film 13 thereunder from being etched by the film 9.

Next, depositing a resist (not shown) on the surface side, using CF _4, CHF ₃ series gas as known a photolithography process and an etching gas R. I. Subjected to E process, the resist formed a SiO ₂ film 10 on the surface as a mask, selectively etching the SiO ₂ film 10, Si ₃ N ₄ film 9 and the pad oxide film 8a until reaching the surface of the silicon substrate 3 The opening 11 is formed (see FIG. 2).
FIG. 2 shows a state after the resist is stripped.

Next, using the SiO ₂ film 10 as a mask, an R.B. I. The second silicon substrate 3 is selectively etched by the E process. The deposition thickness of the SiO ₂ film 10 in the previous process is determined so that the isolation trench (trench) 12 reaches the insulating film 2 satisfactorily by the etching selectivity between the SiO ₂ film 10 and the silicon substrate 3.

Next, C.I. D. E processing is performed. This C. D. The E treatment uses an RF discharge type plasma etching apparatus, for example, raw material gas: CF ₄ , O
₂ , N ₂ , frequency: 13.56 MHz, etching rate: 1500 ° / min, distance from plasma to wafer: 100 cm. Thereby, the separation groove 12
Is etched about 1500 °. Next, C.I.
D. The inner wall surface of the separation groove 12 subjected to the E treatment is annealed. This annealing treatment is performed, for example, by heating at 1000 ° C. for 30 minutes in an N ₂ atmosphere. Next, a sacrificial oxidation process may be performed on the inner wall surface of the separation groove 12 that has been annealed. This sacrificial oxidation process
For example, after a sacrificial oxide film of 500 ° is formed by dry oxidation at 1000 ° C., the sacrificial oxide film is removed with hydrofluoric acid (see FIG. 3).

Next, for example, 105
An insulating film 13 is formed by wet thermal oxidation at 0 ° C., and then polysilicon 14 is deposited by LP-CVD. At this time, the polysilicon 14 is buried in the isolation trench 12 and is also deposited on the SiO ₂ film 10 (see FIG. 4). Next, by dry etching
Extra polysilicon 14 deposited on the SiO ₂ film 10
Back by dry etching (first time)
(See FIG. 5). At this time, the etching is stopped so that the upper end of the polysilicon 14 remaining in the separation groove 12 is located above the Si ₃ N ₄ film 9.

Next, the SiO ₂ film 10 is removed by wet etching using a fluorine solution. At this time, the Si ₃ N ₄ film 9 and the polycrystalline silicon 14 left so that the upper end is located above the Si ₃ N ₄ film 9 serve as an etching stopper, and the pad oxide film 8a and the isolation trench 1 are formed.
The insulating coating 13 formed on the inner wall surface of No. 2 is not etched (see FIG. 6).

Next, Si ₃ N of the polycrystalline silicon 14 buried in the isolation trench 12 by dry etching.
_{4 The} portion projecting above the film 9 is etched back (second time). At this time, when a thermal oxide film 15 described later is grown on the polysilicon 14 in the next step, the upper end of the polysilicon 14 is so formed that the thermal oxide film 15 and the surrounding pad oxide film 8a are at the same height. Is controlled to be about 0.3 μm below the upper end of the pad oxide film 8a (FIG. 7).
reference).

Next, the poly embedded in the separation groove 12 is formed.
Silicon The upper part of silicon 14 is Si _ThreeN_FourSelected by membrane 9
Alternatively, thermal oxidation is performed to grow oxide film 15 (see FIG. 8).
Then, Si_ThreeN_FourThe film 9 is removed by etching (see FIG. 9).
See). As is clear from FIG.
The step in the position is reduced. And a known photolithography
The p-well region 6 and the n-well
L region (not shown) is formed on the second silicon substrate 3 side
(See FIG. 10).

Thereafter, the surface on the second silicon substrate 3 side
Then, the field oxide film 8 is changed to LOCOS (Local Oxidatio).
n of Silicon) method. The LOCOS method
Indicates that Si is used as an oxidation suppressing film on a predetermined portion of the substrate surface._ThreeN
_FourAfter forming the film again, the Si _ThreeN_FourFilm is formed
Thick field acid by oxidizing non-existent parts by thermal oxidation etc.
Forming an oxide film 8, after oxidation by the LOCOS method,
The above Si_ThreeN_FourThe membrane is H_ThreePO_FourTo be removed.

At this time, the Si ₃ N _{4 on} the surface of the thermal oxide film 15 is
Since the film 9 is removed, the thermal oxide film 1 is removed during LOCOS oxidation.
5, the polysilicon 14 immediately below is oxidized, and the thermal oxide film 15 rises. However, since the upper end of the polysilicon 14 is controlled to be lower than the upper end of the pad oxide film 8a by about 0.3 μm (see FIG. 7), the LOCOS
After the oxidation, the LOCOS on the surface of the second silicon substrate 3
The oxidized field oxide film 8 has almost the same height as the raised thermal oxide film 15. As a result, the insulating film (insulator partition) 13 and the upper surface of the thermal oxide film 15
The upper surface of the field oxide film 8 formed by LOCOS oxidation on the surface of the second silicon substrate 3 can be flattened (see FIG. 11).

Next, after removing the pad oxide film 8a, a thin gate
Then, a polysilicon wiring (gate electrode) 16 is formed by performing an LP-CVD process, a photolithography process, and an etching process, and a P-type base region 17 and an N ⁺ diffusion layer 18 are formed by selective doping. Is formed (see FIG. 12). Subsequently, an interlayer insulating film 19 such as PSG or BPSG is deposited, a contact hole is formed in a necessary portion, an aluminum wiring (lower electrode wiring according to the present invention) 20 is formed, and an interlayer insulating film such as PSG or BPSG is formed. A via hole 22 is opened in the interlayer insulating film 21;
Furthermore, aluminum wiring (upper electrode wiring in the present invention)
23, a protection film (not shown) made of a nitride film or the like by plasma CVD, and a Bi-CMO in which a CMOS transistor and a bipolar transistor are combined.
An S semiconductor device (see FIG. 13) is manufactured.

At this time, via hole 22 is opened only above N-type crystal defect suppression region 200. That is, the via hole 22 is formed between two adjacent island-shaped semiconductor regions 10.
0, 101 and trench buried region 30 surrounding them
There is no opening above 0,301. Each of the trench buried regions 300 and 301 has an insulating film (insulating barrier) 13 made of a silicon oxide film and a polysilicon groove buried region (buried in the trench between the insulating films (insulator barrier) 13 on both sides. 14).

FIG. 14 is an enlarged plan view of a main part of FIG.
The via hole 22 is formed above the N-type crystal defect suppression region 200 in the width direction of the N-type crystal defect suppression region 200, and the upper electrode wiring 23 also extends above the N-type crystal defect suppression region 200. I have. By doing so, any branch line may be extended from the upper electrode wiring 23 linearly extending above the linear N-type crystal defect suppression region 200 to reduce the parasitic capacitance, or the upper electrode wiring may be extended. Without bending the upper electrode wiring 23 and the lower electrode wiring 2.
0 can be connected to the upper electrode wiring 2
The wiring layout of No. 3 is simplified.

Since the surface of the N-type crystal defect suppression region 200 is flatter than the surfaces of the island-shaped semiconductor regions 300 and 301, disconnection of the via hole connection portion of the upper electrode wiring 23 and other portions is prevented. can do. (Embodiment 2) Another embodiment will be described with reference to FIGS.

The manufacturing process of this embodiment is the same as that of the first embodiment except that the via hole 22 is formed in the N-type crystal defect suppressing region 2 between the two adjacent island-shaped semiconductor regions 100 and 101.
00, a trench buried region 300 between the N-type crystal defect suppression region 200 and the island-shaped semiconductor regions 100 and 101,
301 and is opened. Incidentally, each of the trench buried regions 300 and 301 is formed of an insulating film (insulating partition) 13 made of a silicon oxide film and a polysilicon groove burying region ( 14).

FIG. 16 is an enlarged plan view of a main part of FIG.
In the width direction of the N-type crystal defect suppression region 200, the opening end of the via hole 22 is just
01 is located above each of the polysilicon trench filling regions 14. Therefore, even if the width of the N-type crystal defect suppression region 200 is small, the width of the via hole 22 can be sufficiently ensured. It is possible to improve the degree of integration while ensuring the reliability of the connection between the two wirings 20 and 23.

In particular, in this embodiment, the thermal oxide film 15 on the polysilicon trench filling region 14 is formed by the above-described process.
Are formed at the same height as the LOCOS oxide film 8 on the adjacent N-type crystal defect suppression region 200 and the island-shaped semiconductor regions 100 and 101, and are flattened. However, the disconnection of the step does not increase, and the reliability of the wiring can be ensured.

The above-described N-type crystal defect suppression region 20
Numeral 0 is provided to reduce crystal defects in the island-shaped semiconductor regions 100 and 101, and preferably has a width of 4 to 100 μm, and here, has a width of 4 μm.
Also, the polysilicon groove filling region 14 preferably has a width of 1 to 5 μm, and here has a width of 2 μm.
Further, the width of the insulating coating 14 is preferably 0.5 to 4.5 μm, and here, the width is 1.5 μm. The via hole 22 preferably has a width of 0.5 to 10 μm, and here has a width of 3 μm.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a process of manufacturing an insulator-isolated semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a process of manufacturing the insulator-separated semiconductor device of the present embodiment.

FIG. 3 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 4 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 5 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 6 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 7 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 8 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 9 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 10 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 11 is a cross-sectional view illustrating a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 12 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present example.

FIG. 13 is a cross-sectional view showing a step of manufacturing the insulator-isolated semiconductor device of the present embodiment.

FIG. 14 is an enlarged plan view of a main part of the insulator separation semiconductor device.

FIG. 15 is a cross-sectional view of an insulator-separated semiconductor device according to a second embodiment.

16 is an enlarged plan view of a main part of FIG.

[Explanation of symbols]

20 is a lower electrode wiring, 21 is an interlayer insulating film, 22 is a via hole, 23 is an upper electrode wiring, 13 is a silicon oxide film (insulator partition, trench buried region), 14 is a polysilicon groove buried region (trench buried region), 200 is an N-type crystal defect suppression region ( single crystal region ), and 100 and 101 are island-shaped semiconductor regions.

Continuation of the front page (56) References JP-A-3-234404 (JP, A) JP-A-5-90418 (JP, A) JP-A-5-41454 (JP, A) JP-A-4-67656 (JP) , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/762 H01L 21/8249 H01L 27/06 H01L 27/12

Claims (3)

(57) [Claims] A plurality of island-shaped semiconductor regions having side surfaces insulated and regularly arranged by a trench buried region comprising a pair of insulator partition walls and a polysilicon trench buried region therebetween, and having a built-in element therein A single-crystal region surrounding each of the island-shaped semiconductor regions with the trench-buried region interposed therebetween; and a single-crystal region extending over the island-shaped semiconductor region, the polysilicon-groove-filled region, and the single-crystal region via an insulating film. A lower electrode wiring to be formed, a via hole opened in the interlayer insulating film on the lower electrode wiring only above the single crystal region , and a via hole extending on the interlayer insulating film and passing through the via hole to the lower electrode wiring. and an upper layer electrode wiring connected, wherein the insulating film surface immediately above the single-crystal region, said trench
The insulating film is formed flat on the surface of the insulating film immediately above the buried region.
And that the insulation material separating wherein a. 2. A plurality of island-shaped semiconductor regions having side surfaces insulated and regularly arranged by a trench buried region comprising a pair of insulator partition walls and a polysilicon trench buried region therebetween, and having elements built therein. A single-crystal region surrounding each of the island-shaped semiconductor regions with the trench-buried region interposed therebetween; and a single-crystal region extending over the island-shaped semiconductor region, the polysilicon-groove-filled region, and the single-crystal region via an insulating film. Lower electrode wiring to be formed, and the single connection sandwiched between a pair of adjacent island-shaped semiconductor regions.
A via hole opening in the interlayer insulating film on the lower electrode wiring over the crystal region and the pair of trench buried regions on both sides thereof; and a lower electrode wiring extending through the interlayer insulating film through the via hole. and an upper layer electrode wiring connected to, the said surface of the insulating film directly above the single-crystal region, said trench
The insulating film is formed flat on the surface of the insulating film immediately above the buried region.
And that the insulation material separating wherein a. 3. An insulating film according to claim 1 , wherein said insulating film is provided on a surface portion of said single crystal region.
And oxidize the surface of the polysilicon trench filling region to form
3. The semiconductor device according to claim 1 , further comprising a field oxide film.