JP3021850B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device such as a bipolar transistor in which an element is separated from a silicon substrate by an insulator.

[0002]

2. Description of the Related Art Conventionally, as a method of separating elements used in a monolithic semiconductor integrated circuit, a method of separating elements using an insulator has been known. For example, Ultra-
Fast Silicon Bipolar Tech
No. 6, page 66, discloses a method of forming a partially thick field oxide film on a main surface of a silicon substrate and then forming an isolation groove for element isolation. This method will be described below.

As shown in FIG. 18, a partially thick field oxide film 32 is formed on a main surface of a silicon substrate 31.
A silicon nitride film 33 and a silicon oxide film 34 as a mask are sequentially formed, and the field oxide film 32 and the silicon nitride film 33 are formed in a thin range of the field oxide film.
After the silicon oxide film 34 is selectively etched to form an opening, the silicon substrate 31 is etched from the opening to form a separation groove 35. Then, the silicon oxide film 34 as a mask is removed by etching, and the separation groove 35 is removed.
After the insulating film 36 is formed on the inner wall surface of the
Is filled with polycrystalline silicon 37. Further, when the polycrystalline silicon 37 is filled, the polycrystalline silicon 37 deposited on the silicon nitride film 33 is etched back, and the silicon nitride film 33 is removed by etching. By forming the oxide film 38 (see FIG. 18), the silicon substrate 31 is completely electrically separated by the separation groove 35 and the insulating film 36.

[0004]

The reason why the isolation groove is formed after the formation of the field oxide film as in the above-mentioned conventional method is to suppress generation of crystal defects around the isolation groove. That is, when a field oxide film is formed after forming an isolation groove and performing insulation separation, the silicon substrate expands when oxidized to become a field oxide film.
Stress concentrates on the boundary between the silicon substrate and the separation groove, and as a result, crystal defects occur.

Further, as in the above-mentioned conventional method, after the formation of the field oxide film, the separation groove is formed in the thin portion of the field oxide film because the separation groove is formed in the thick portion of the field oxide film. Since the end surface of the field oxide film is largely exposed by the separation groove, the silicon oxide film as a mask is etched and removed when etching the silicon oxide film, resulting in large constriction, thereby deteriorating the flatness of the substrate surface. Because you do.

However, when a separation groove is formed in a thin portion of the field oxide film after the formation of the field oxide film as in the above-described conventional method, the end face of the thick portion of the field oxide film is separated from the separation groove. In order to reliably prevent the inconvenience caused by the exposure, the size of a semiconductor device to be manufactured, for example, a transistor, must be increased in consideration of misalignment of a mask.

Further, since the isolation groove 35 is formed in the thin portion of the field oxide film 32, the edge B of the silicon substrate 31 exists around the upper end of the isolation groove 35. The upper end of the edge B
Since the oxide film 38 is formed above the polycrystalline silicon 37, the vertical bird's beak A is formed at the corner when the oxide film 38 is formed. As a result, stress concentrates on the edge B of the silicon substrate 31 and the crystal is formed. Defects are more likely to occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is possible to form a separation groove in a thick portion of a field oxide film without deteriorating the flatness of a substrate surface. It is an object of the present invention to prevent a large size and crystal defects from occurring.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a partially thickened field oxide film, silicon nitride film or polycrystalline silicon film and a mask are formed on a main surface of a silicon substrate. Forming a silicon oxide film in sequence, and selectively forming an opening by selectively etching the field oxide film, the silicon nitride film or the polycrystalline silicon film, and the silicon oxide film in the thickness range of the field oxide film. Forming a separation groove by etching the silicon substrate from the opening; forming an insulating film on the inner wall surface of the separation groove; and filling the separation groove with polycrystalline silicon. The polycrystalline silicon deposited on the silicon oxide film, the upper end of the polycrystalline silicon in the isolation trench being higher than the upper end of the silicon nitride film or the polycrystalline silicon film. And etching back with an etching control as, the second silicon oxide film,
Etching the polycrystalline silicon in the isolation trench and the silicon nitride film or the polycrystalline silicon film as an etching stopper for the field oxide film and the insulating film.

[0010]

According to the method of manufacturing a semiconductor device of the present invention, a partially thickened field oxide film, a silicon nitride film or a polycrystalline silicon film, and a silicon oxide film are sequentially formed on a main surface of a silicon substrate. When etching back the polycrystalline silicon, the etching is controlled so that the upper end of the polycrystalline silicon in the isolation trench is higher than the upper end of the silicon nitride film or the polycrystalline silicon film. Therefore, when the silicon oxide film serving as a mask is removed by etching, the polycrystalline silicon and the silicon nitride film or the polycrystalline silicon film in the isolation trench act as an etching stopper for the field oxide film and the insulating film. In addition, the field oxide film and the insulating film are not etched, and the isolation groove can be formed in the thick region of the field oxide film without impairing the flatness of the substrate surface in the isolation groove portion.

In addition, since the isolation trench is formed in the thick region of the field oxide film as described above, the upper end of the etched back polysilicon is located higher than the upper end of the silicon substrate. When the silicon oxide is oxidized, stress does not occur in the silicon substrate due to the vertical bird's beak as in the conventional method of forming an isolation groove in a thin region of the field oxide film, and no crystal defect occurs. Further, unlike the conventional method of forming an isolation groove in a thin region of a field oxide film, it is not necessary to increase the size of a semiconductor device in consideration of misalignment of a mask.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) After mirror-polishing one main surface of a P ^- type first silicon substrate 1, thermal oxidation was performed to form an insulating film 2 having a predetermined thickness. Then, a second silicon substrate 3 having a mirror-polished main surface is brought into close contact with the insulating film 2 side of the first silicon substrate 1 in a sufficiently clean atmosphere and heated, so that the respective silicon substrates 1, 3 They were integrally joined so as to sandwich the insulating film 2. Thus, an SOI substrate constituted by joining the second silicon substrate 3 on the first silicon substrate 1 via the insulating film 2 was produced (see FIG. 1). In FIG. 1,
Reference numeral 4 denotes an N-type high-concentration impurity (Sb) layer formed by doping from the surface of the second N ^- type silicon substrate before bonding.

Then, a P-well region 5, an N-well region 6, and a deep N ⁺ region 7 were formed on the second silicon substrate 3 by a series of oxidation, photolithography, and impurity diffusion steps (see FIG. 2). During this time, the second silicon substrate 3
The growth and removal of the oxide film on the surface can be performed freely. Thereafter, a field oxide film 8 is formed on the surface of the second silicon substrate 3.
To LOCOS (Local Oxidation of
(See FIG. 3). In the LOCOS method, a predetermined portion of Si is used as an oxidation suppressing film.
After the formation of the ₃ N ₄ film, a portion where the Si ₃ N ₄ film is not formed is oxidized by thermal oxidation or the like.
FIG. ₃ is a view after removing the Si ₃ N ₄ film by H ₃ PO ₄ after oxidation by the OCOS method.

Next, Si ₃ forming the silicon nitride film of the present invention
An N ₄ film 9 and a CVD-SiO ₂ film 10 serving as a silicon oxide film as a mask of the present invention were deposited and annealed at 1000 ° C. to densify the CVD-SiO ₂ film 10. Subsequently, the thick range of the field oxide film 8, using CF _4, CHF ₃ series gas as photolithography and etching gas R. I. E (R
active ion etching), and using the resist film formed on the surface of the CVD-SiO ₂ film 10 as a mask, the field oxide film 8 and the Si ₃ N ₄
The film 9 and the CVD-SiO ₂ film 10 are transferred to the second silicon substrate 3
The opening 11 was formed by selective etching until the surface 11 reached (see FIG. 4).

After the removal of the resist film, CVD-SiO ₂
Using the film 10 as a mask, an R.V. I. The second silicon substrate 3 was selectively etched by the E process to form a separation groove 12 reaching the insulating film 2 (see FIG. 5). Next, C.I.
D. E treatment was performed. This C. D. In the E treatment, an RF discharge type plasma etching apparatus was used, and a raw material gas: C was used.
The etching was performed under the conditions of F ₄ , O ₂ , N ₂ , frequency: 13.56 MHz, and etching rate: 1500 ° / min. Thus, the inner wall surface of the separation groove 12 was etched at about 1500 °.

Next, C.I. D. The inner wall surface of the E-treated separation groove 12 was annealed. This annealing treatment was performed by heating at a temperature of 1000 ° C. for 30 minutes in an N ₂ atmosphere. Next, after an insulating film 13 is formed on the inner wall surface of the separation groove 12 by thermal oxidation, the polycrystalline silicon 14 is
Separated by -CVD method groove 12 and the CVD-SiO ₂ film 1
Then, polycrystalline silicon 14 was filled in the isolation trench 12 (see FIG. 6).

Next, CV is performed by dry etching.
Polycrystalline silicon 14 deposited on D-SiO ₂ film 10
Was etched back (first time) (see FIG. 7). At this time, the upper end of the polycrystalline silicon 14 remaining in the separation groove 12 is S
The etching was stopped so as to be above the i ₃ N ₄ film 9. Next, the CVD-SiO ₂ film 10 was etched away by wet etching using a fluorine solution (see FIG. 8). At this time, the the Si ₃ N ₄ film 9, the Si ₃
The polycrystalline silicon 14 left so that the upper end is located above the N ₄ film 9 becomes an etching stopper, and the insulating film 1 formed on the inner wall surfaces of the field oxide film 8 and the isolation trench 12
3 was not etched.

Next, the Si ₃ N of the polycrystalline silicon 14 buried in the isolation trench 12 by dry etching.
₄ An etching back (second time) of a portion projecting above the film 9 was performed (see FIG. 9). At this time, when a thermal oxide film 15 described later is formed on the polycrystalline silicon 14 in the next step, the polycrystalline silicon 14 is formed so that the thermal oxide film 15 and the surrounding field oxide film 8 are at the same height. It is desirable to control the upper end to be about 0.3 μm below the upper end of the field oxide film 8.

Next, after an oxide film 15 is formed on the polycrystalline silicon 14 buried in the isolation trench 12 by thermal oxidation (see FIG. 10), the Si ₃ N ₄ film 9 is removed by etching (FIG. 11). reference). As is clear from FIG. 11, no step is formed in the separation groove 12, and the separation groove 12 has a flat shape. Next, a thin gate oxide film is formed and LP-CVD
A polycrystalline silicon wiring (gate electrode) 16 is formed by performing processing, photolithography, and etching, and a P ⁺ diffusion layer 17 and an N ⁺ diffusion layer 18 are formed by selective doping (see FIG. 12). During this time, the etching of the field oxide film 8 is about 0.2 μm, and the flatness of the isolation groove 12 is not impaired.

Subsequently, an interlayer insulating film (oxide film) 19 is deposited, a contact hole is formed in a necessary portion, an Al wiring 20 and a protective film (oxide film) 21 are formed, thereby manufacturing a semiconductor device (FIG. 13). As described above, according to the manufacturing method of this embodiment, no step is formed in the isolation groove 12 and a flat shape is obtained.
It is possible to manufacture a semiconductor device in which disconnection or short circuit of the wiring 20 does not occur.

Further, as described above, the separation groove is formed in the thick range of the field oxide film 8 and the upper end of the second etched back polycrystalline silicon 14 is higher than the upper end of the second silicon substrate 3. As shown in FIG. 9, when the polycrystalline silicon 14 is oxidized, stress is applied to the second silicon substrate 3 by vertical bird's beak as in the conventional method of forming an isolation groove in a thin area of the field oxide film 8. Does not occur and crystal defects do not occur. Therefore, current leakage caused by crystal defects can be prevented. Further, unlike the conventional method of forming an isolation groove in the thin region of the field oxide film 8, it is not necessary to increase the size of the semiconductor device in anticipation of misalignment of the mask, and the size of the semiconductor device can be reduced. it can.

Further, in the above embodiment, C.I. D. E treatment and annealing treatment are performed.
For this reason, the damage layer generated on the inner wall surface of the separation groove 12 during the formation of the separation groove 12 is formed by C.I. D. E is sufficiently or completely removed by the E treatment, and the C.E. D.
E layer and the damaged layer that could not be removed by the E treatment. D. The damage layer newly generated by the E treatment can be recovered, and the separation groove 12
It is possible to eliminate crystal defects such as the inner wall surface of the substrate.

In the above embodiment, an example is shown in which the present invention is applied to an SOI substrate. However, the present invention can be applied to a simple silicon substrate. Further, in the above embodiment, CVD-Si is used as a silicon oxide film as a mask.
An O ₂ film was formed, but instead of a CVD-SiO ₂ film, P
SG film (Phospho Silicate Glass)
s) may be formed.

Further, in the above embodiment, the etching back of the polycrystalline silicon 14 is performed by the dry etching process, but it may be performed by a polishing technique. (Second Embodiment) A second embodiment using a polycrystalline silicon film 9 'instead of the Si ₃ N ₄ film 9 of the first embodiment will be described below.

After going through the steps shown in FIGS. 1 to 3 described above,
Polycrystalline silicon film 9 'by LP over CVD in this embodiment, SiO ₂ is deposited film 10 by CVD, similarly to the step shown in FIG. 4 described above, an annealing process 1000 ° C., densify the SiO ₂ film 10 Become Subsequently, a resist is deposited, photolithography is performed to form a resist pattern, and CF ₄ , CHF _{3 is used} as an etching gas.
R. using a base gas I. E treatment, SiO ₂ film 10,
Opening 1 in polycrystalline silicon film 9 'and field oxide film 8
1 is formed, and a Si ₃ N ₄ film 22 is deposited on the substrate surface (see FIG. 14). And anisotropic R.I. I. E treatment is performed to leave the Si ₃ N ₄ film 22 only on the side wall of the opening 11 (see FIG. 15). The Si ₃ N ₄ film 22 prevents the polycrystalline silicon film 9 ′ exposed in the opening 11 from being simultaneously oxidized when the insulating film 13 is formed on the inner wall of the isolation groove 12 by thermal oxidation in a later step.

Next, using the SiO ₂ film 10 as a mask, an R.B. I. E treatment is performed, and the second silicon substrate 3 is selectively etched to form a separation groove 12 reaching the insulating film 2. Subsequently, on the inner wall surface of the separation groove 12, as in the first embodiment,
C. D. An E process and an annealing process are sequentially performed. Then, the inner wall surface of the separation groove 12 is thermally oxidized to form an insulating film 13,
Thereafter, the Si ₃ N ₄ film 22 covering the wall of the opening 11 is removed with an H ₃ PO ₄ solution (see FIG. 16). As described above, when the insulating film 13 is formed, the polycrystalline silicon film 9 ′ is not exposed to the opening 11 by the Si ₃ N ₄ film 22 and is not oxidized. Here, 'when is that oxidized, when the SiO ₂ film 10 is etched away in a subsequent step, the polycrystalline silicon film 9' polycrystalline silicon film 9 to the oxidation portion of the is also etched by the etchant simultaneously This causes a step in the separation groove 12.

Next, as in the step shown in FIG.
After depositing the polycrystalline silicon 14 (see FIG. 17), the Bi-CMOS semiconductor device shown in FIG. 13 is manufactured through the same steps as those shown in FIGS. 7 to 13 described above. In this embodiment, the polycrystalline silicon film 9 'and the isolation
The polycrystalline silicon 14 filled in the inside is the SiO ₂ film 10
It functions as an etching stopper at the time of removal, and prevents the field oxide film 8 and the insulating film 13 under the polycrystalline silicon film 9 'from being simultaneously etched. Further, as described above, since the oxidized portion does not exist also in the polycrystalline silicon film 9 ′, the etching does not proceed to a lower layer therefrom.

Further, in the second embodiment, the polycrystalline silicon film 9 'can be removed simultaneously with the second etching back of the polycrystalline silicon film 14.

[0029]

As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, it is possible to form an isolation groove in a thick range of a field oxide film without impairing the flatness of a silicon substrate. Therefore, there is no need to anticipate misalignment of the mask and the occurrence of crystal defects in the silicon substrate is suppressed, so that there is no breakage or short circuit of the polycrystalline silicon wiring and Al wiring, and there is no unnecessary enlargement. A semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing a semiconductor device of a first embodiment.

FIG. 2 is a process chart showing a method for manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a process chart showing a method for manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a process chart showing a method for manufacturing the semiconductor device of the first embodiment.

FIG. 5 is a process chart showing a method for manufacturing the semiconductor device of the first embodiment.

FIG. 6 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 7 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 8 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 9 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 10 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 11 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 12 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 13 is a process chart showing the method for manufacturing the semiconductor device of the first embodiment.

FIG. 14 is a process chart illustrating a method for manufacturing a semiconductor device of a second embodiment.

FIG. 15 is a process chart showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 16 is a process chart showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 17 is a process chart showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 18 is a process chart showing a conventional method for manufacturing a semiconductor device.

FIG. 19 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 is a first silicon substrate, 2 is an insulating film, 3 is a second silicon substrate, 8 is a field oxide film, 9 is a Si ₃ N ₄ film forming a silicon nitride film, 9 ′ is a polycrystalline silicon film, and 10 is a mask. A CVD-SiO ₂ film forming a silicon oxide film of
Reference numeral 11 denotes an opening, 12 denotes a separation groove, 13 denotes an insulating film, and 14 denotes polycrystalline silicon.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-1755651 (JP, A) JP-A-3-76140 (JP, A) JP-A-63-307756 (JP, A) JP-A-60-1985 753 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (1)

(57) [Claims] A step of sequentially forming a partially thickened field oxide film, a silicon nitride film or a polycrystalline silicon film, and a silicon oxide film as a mask on a main surface of a silicon substrate; A step of selectively etching the field oxide film, the silicon nitride film or the polycrystalline silicon film, and the silicon oxide film to form an opening in a thickness range of the film, and etching the silicon substrate from the opening. A step of forming an isolation groove; a step of forming an insulating film on the inner wall surface of the isolation groove; a step of filling the isolation groove with polycrystalline silicon; and a step of depositing the polycrystalline silicon deposited on the silicon oxide film. ,
Etching back while controlling the etching so that the upper end of the polycrystalline silicon in the isolation groove is higher than the upper end of the silicon nitride film or the polycrystalline silicon film; And removing the polycrystalline silicon and the silicon nitride film or the polycrystalline silicon film as etching stopper portions for the field oxide film and the insulating film.