DE69231803T2 - Method of manufacturing a semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a preferred manufacturing method for separating elements from each other by forming a deep trench on a silicon substrate.

STATE OF THE ART

So far, a method for separating individual elements from each other using an insulator is known as the element separation method, which is used in monolithic semiconductor integrated circuits.

For example, Japanese Patent Application JP-A-61-059852 discloses a semiconductor device manufacturing method for separating elements from each other by forming a separation trench on a bonded SOI (silicon on insulator) substrate. This method produces an SOI substrate by bonding a silicon substrate 42 to another silicon substrate 40 on the surface of which an insulating film 41 is formed as shown in Fig. 36(A) through an insulating film 41 as shown in Fig. 36(B), forms isolation trenches 43 reaching to the insulating film 41 in the SOI substrate from a main surface of this SOI substrate, then forms an insulating film 44 on the surface of the SOI substrate including inner walls of the isolation trench 43 by thermal oxidation or the like as shown in Fig. 36(C), fills the isolation trenches 43 with polycrystalline silicon 45 as shown in Fig. 36(D), removes excess parts of the insulating film 44 and the polycrystalline silicon 45 extending from the separation trenches 43, and electrically separates respective element surfaces 46 completely from the substrate 40 or from each other by means of an insulator, as shown in Fig. 36(E).

For example, as disclosed on page 66 of the cited publication "Ultra-Fast Silicon Bipolar Technology", a method of forming a separation trench for separating respective elements from each other after forming a field oxide film, which is partially thick in terms of film thickness, on the main surface of a silicon substrate is known as a method of forming a separation trench. The method is described below.

As shown in Fig. 37, the method sequentially forms in order a partially thick field oxide film 32, a silicon nitride film 33 and a silicon oxide film for use as a mask on the main surface of a silicon substrate 31, forms an opening by selectively etching the field oxide film 32, the silicon nitride film 33 and the silicon oxide film 34 in a region where the field oxide film is thin in film thickness, then forms a separation trench 35 by etching the silicon substrate 31 through the opening. Further, it etches away the silicon oxide film 34 used as a mask, forms an insulating film 36 on an inner wall of the isolation trench 35, then fills polycrystalline silicon 37 in the isolation trench 35. Further, it carries out etching back of the polycrystalline silicon 37 deposited on the silicon nitride film 33 when filling the isolation trench with the polycrystalline silicon 37, etches away the silicon nitride film 33, and then forms a silicon oxide film 38 on the top of the polycrystalline silicon 37 in the isolation trench. (See Fig. 38). And in this way, the process electrically completely separates the silicon substrate 31 into respective element areas through the separation trench 35 and the insulating film 36.

In a series of processings shown in Figs. 36(A) to 36(E), an oxide film as described above has been generally formed on the surface of an SOI substrate as a mask for forming a separation trench on the SOI substrate. Furthermore, the oxide film used as a mask for forming a separation trench was immediately removed after forming the separation trench. However, as shown in Fig. 36(E), in the case of separating an element surface 46 by an insulating film 41 from a substrate 40, an insulating film for separating the substrate is exposed within the separation trench immediately after forming the separation trench. In this case, since the insulating film 41 inside the SOI substrate for separating the substrate and the oxide film for the mask have an approximately equal etching rate, if it is attempted to etch away the oxide film as the mask immediately after forming the separation trench, the insulating film inside the substrate is also etched away at the same time.

The present invention has been made in consideration of the above-mentioned facts. The first object of the invention is to provide a method of manufacturing a semiconductor device which makes it possible to prevent local deterioration of the dielectric strength in a separation trench region by protecting the insulating film for separation between the substrates which is exposed inside the separation trenches from being etched during processing.

The reason why a separation trench is formed in a region where the field oxide film is thin in terms of film thickness as shown in Fig. 37 is to prevent deterioration of the flatness of the surface of a substrate which is feared in the case of forming the separation trench in a region where the field oxide film is thick in terms of film thickness. In the case of forming a separation trench in a region where the field oxide film is thick, an end face of the field oxide film is largely exposed by the separation trench, the field oxide film is also etched when a silicon oxide film used as a mask is etched away, and a deep cavity is caused which deteriorates the flatness of the substrate. Deterioration of the flatness of the substrate causes such problems as breakage and short-circuiting of a polycrystalline silicon wiring or aluminum wiring. Therefore, even if the field oxide film is etched, deterioration of the flatness of the substrate does not become so much of a problem when a separation trench is formed in an area where a field oxide film is thin in terms of film thickness.

On the other hand, in a case where a separation trench is formed in an area where the field oxide film is thin after forming an oxide film as shown in a previous process in Figs. 37 and 38, it is necessary to make a semiconductor device, for example, for a transistor larger in size by allowing a certain deviation in mask coverage in order to surely prevent a problem caused by the end face of a thick part of the field oxide film being exposed by a separation trench.

The second object of the invention is to prevent a semiconductor device from being made unnecessarily large in size without deteriorating the flatness of the surface of a substrate even when a separation trench is formed in a region where a field oxide film is thick, by taking into consideration the above-mentioned problem.

A separation trench as described above is generally formed by etching a silicon substrate by the RI E (reactive ion etching) process. The RI E process is a process in which a cathode drop voltage (bias voltage) is generated by applying a high frequency voltage to an electrode on which a silicon substrate is mounted, and the silicon substrate is etched by causing ions or radicals as active particles generated by being a plasma discharged from a fluoride series material gas to collide with the substrate and react. Since the RI E process accompanied by a physical etching process is highly aggressive to the silicon substrate, it causes crystal defects on the surface of inner walls of a separation trench and the surface of the silicon substrate surrounding the inner walls due to the etching damage, thus causing a leakage of electric current. For the purpose of removing such crystal defects, an inner wall of a separation trench has been processed by a sacrificial oxidation process or CD E (chemical dry etching) process, as disclosed in Japanese publications JP-A-3-127850 and JP-A-3-129854. The sacrificial oxidation process is a process of removing crystal defects by etching away an oxide film after forming the oxide film, which extends to a depth at which crystal defects exist in inner walls of a separation trench. Furthermore, the CD E-process a process of etching away a part which has crystal defects, solely by chemical etching of less aggressiveness with the help of radicals of a material gas which has been activated by plasma discharge.

Further previously published processes can be found in publications EP-A-0398468 and JP-A-58-190040.

DISCLOSURE OF THE INVENTION

The invention is defined by claim 1.

To achieve the object of the invention, a method of the invention fills a separation trench with polycrystalline silicon, removes an excess portion of the polycrystalline silicon protruding from the separation trench on the substrate, and then etches away an oxide film as a mask.

That is, the method of the invention comprises:

a step of depositing a first layer and a second layer on the main surface of an SOI layer deposited on an insulating substrate, sequentially in the order,

a step of forming an opening in the first and second layers to expose a specific part of the main surface on the SOI layer,

a step of forming a separation trench reaching to the insulating substrate by etching the SOI layer through the opening by creating the second layer as a mask,

a step of forming an insulating film on the surface of inner walls of the separation trench,

a step of filling the separation trench with a filler through the opening until the top of the filler becomes higher in height than the first layer, and

a step of removing the second layer by providing the filler and the first layer as etch stoppers, as more precisely defined in claim 1.

As a result, when the second layer used as a mask is etched away when forming the recess, the filler and the first layer prevent the etching from progressing to a layer deeper than themselves, so that, for example, a level difference caused by etching away a field oxide film and the like does not occur in a trench region formed on the surface of a semiconductor substrate and the like.

According to the invention, therefore, even if a separation trench is formed in a region where a field oxide film is thick, the flatness of the surface of a substrate is not deteriorated, and unnecessary bloating of the size of a semiconductor device, which has heretofore been caused by expecting some deviation in mask coverage, can also be prevented.

Furthermore, when the second layer used as a mask is removed, not only a field oxide film, but also an insulating film formed on the surface of inner walls of the recess is not etched in the depth direction. When the insulating film on the surface of the inner walls of the recess is etched, a sharp level difference formed on the surface of the substrate in a region of the trench brings a problem of breakage or short-circuiting of a polycrystalline silicon wiring or aluminum wiring on the surface of the substrate, but when the invention is applied, it is made possible to manufacture a semiconductor device which does not have breakage or short-circuiting of a polycrystalline silicon wiring or aluminum wiring, since level differences do not occur in the trench region and the surface of the substrate can be made flat.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1 to 13 are cross-sectional views of a 501 substrate for explaining the manufacturing process of the SOI substrate in order in the case of applying a manufacturing method of a first embodiment of the invention.

Figs. 14 to 17 are cross-sectional views of an SOI substrate for explaining the manufacturing process of the SOI substrate in order in case of applying a manufacturing method of a second embodiment of the invention.

Fig. 18 is a diagram illustrating the result of a defect density measurement after forming a separation trench.

Figs. 19 to 31 are cross-sectional views of an SOI substrate for explaining the manufacturing process of the SOI substrate in order in the case of applying a manufacturing method of the third embodiment of the invention.

Figs. 32 to 35 are cross-sectional views of an SOI substrate for explaining the manufacturing process of the SOI substrate in order in case of applying a manufacturing method of a fourth embodiment of the invention.

Fig. 36(A) to 36(E) are cross-sectional views of an SOI substrate for explaining conventional manufacturing processes of the SOI substrate in order.

Figs. 37 and 38 are cross-sectional views of a substrate for explaining a conventional treatment of forming a trench.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the invention are described below with reference to the drawings.

[FIRST EMBODIMENT]

The first embodiment of the invention subjects a main surface of a first P--type single crystal silicon substrate 1 to final polishing and then forms thereon an insulating film 2 of a specific thickness by thermal oxidation. Furthermore, the first embodiment connects a second single crystal silicon substrate 3 having the final polished main surface performed with mirror-like polishing, with the insulating film 2 side of the surface of the first silicon substrate 1 under a sufficiently pure atmosphere, and heats them to bond them together so as to hold the insulating film between the respective silicon substrates 1 and 3. In this form, an SOI substrate is produced which is composed by bonding the second substrate 3 on the first silicon substrate 1 through the insulating film 2 (see Fig. 1). In Fig. 1, a reference numeral 4 denotes an N-type high-density impurity (Sb) layer which is formed by doping from the surface of the N-type second silicon substrate 3 before the bonding is performed.

Furthermore, the embodiment forms a cushion oxide film 8a on the surface of the second silicon substrate 3 side by thermal oxidation, sequentially deposits on this surface in order a Si3N4 film 9 as a first insulating layer and a SiO2 film 10 as a second insulating layer by a CVD method, and anneals the substrate at 1000°C to make the SiO2 film 10 dense, and then deposits a photoresist (not shown) thereon, processes it by a known photolithography process and R.I.E process using a CF4 or CHF3 series gas. as an etching gas and creates an opening 11 by selectively etching the SiO₂ film 10, the Si₃N₄ film 9 and the cushion oxide film 8a until the surface of the silicon substrate 3 is reached, using the photoresist deposited on the surface of the SiO₂ film 10 as a mask (see Fig. 2). Fig. 2 shows a state after stripping the photoresist.

Next, the embodiment creates a separation trench 12 reaching to the insulating film 2 by selectively etching the second silicon substrate 3 using the SiO₂ film as a mask by means of an RI E process using an HBr series gas as an etching gas (see Fig. 3). In this case, the thickness of the SiO₂ film 10 to be deposited must be determined in the previous step so that the isolation trench 12 successfully reaches the insulating film 2 according to the etching rates of the SiO₂ film and the silicon substrate 3.

Next, C.D.E treatment is applied to the surface of the inner walls of the separation trench 12. The C.D.E treatment is carried out using an RF discharge type plasma etching system under the condition of, for example, material gases of CF4, O2 and N2, a discharge frequency of 13.56 MHz, an etching rate of 150 nm/min (1500 kImin) and a distance from the plasma to the wafer of 100 cm. In this way, the inner wall of the separation trench 12 is etched by about 150 nm (1500 Å).

Next, the inner walls of the separation trench 12 processed with the C.D.E treatment are annealed. The annealing process is carried out, for example, by heating at 1000ºC for 30 minutes in a N2 atmosphere.

Next, a sacrificial oxidation process may be applied to the annealed inner walls of the separation trench 12. The sacrificial oxidation process is carried out, for example, by forming a 50 nm (500 k) sacrificial oxide film by means of a dry oxidation process at 1000°C and then removing this sacrificial oxide film by fluoric acid.

Furthermore, an insulating film 13 is formed on the inner walls of the separation trench 12 by means of a wet thermal oxidation at, for example, 1050ºC and then polycrystalline silicon 14 is deposited thereon by means of an LP-CVD method. At this time, the polycrystalline silicon not only fills the separation trench 12 but also overlies the SiO₂ film 10 (see Fig. 4). Next, an excess part of the polycrystalline silicon 14 deposited on the SiO₂ film 10 is subjected to etching back (for the first time) by means of a dry etching method (see Fig. 5). At this time, the etching process is stopped so that the tip of the polycrystalline silicon 14 remaining in the separation trench 12 remains higher than the Si₃N₄ film 9.

Next, the SiO2 film 10 is etched away by a wet etching process using a fluorine solution (see Fig. 6). In this case, the pad oxide film 8a and the insulating film 13 formed on the inner wall of the separation trench 12 are not etched because the Si3N4 film 9 and the polycrystalline silicon 14, which is left so that its tip is higher than the Si3N4 film 9, act as an etching stopper.

Next, the part of the polycrystalline silicon 14 filled in the separation trench 12 which protrudes from the Si3N4 film 9 is etched back by dry etching (for the second time) (see Fig. 7). In this case, it is desirable to control the tip of the polycrystalline silicon 14 to be about 0.3 µm lower than the tip of the pad oxide film 8a so that a thermal oxide film 15 can come to a level with the surrounding pad oxide film 8a after the thermal oxide film 15 is caused to grow on the polycrystalline silicon 14 in the next step which will be described later.

Next, after the oxide film 15 is grown by selectively thermally oxidizing the tip of the polycrystalline silicon 14 filled into the isolation trench 12 through an opening of the Si3N4 film 9 (see Fig. 8), the Si3N4 film 9 is etched away (see Fig. 9). As is clear from Fig. 9, a portion of the isolation trench 12 is kept flat without forming a level difference.

Furthermore, a P-well region 5, an N-well region 6 and a deep N+ region 7 are formed in the side of the second silicon substrate 3, which are formed into an SOI layer by means of a known photolithography process and an impurity diffusion process (see Fig. 10).

Thereafter, a field oxide film 8 is formed on the surface of the second silicon substrate 3 side by means of the LOCOS (local oxidation of silicon) method (see Fig. 11). The LOCOS method is a process which again forms a Si3N4 film as an oxidation-preventing film on a specified part of a substrate and then forms a thick field oxide film 8 by oxidizing a part where the Si3N4 film is not formed by means of thermal oxidation or the like. Fig. 11 shows a state after removing the Si3N4 film by H3PO4 after performing oxidation by means of the LOCOS method.

Next, the method of the embodiment forms a thin gate film after removing a pad oxide film 8a, forms a polycrystalline silicon wiring (gate electrode) 16 by applying an LP-CVD process, a photolithography process and an etching process, and forms a P+ diffusion layer 17 and N+ diffusion layer 18 by means of selective doping. (See Fig. 12). During this time, while an etching depth of the field oxide film 8 is about 0.2 µm, the flatness of the portion of the separation trench 12 is not deteriorated.

Thereafter, the process deposits an interlayer insulating film 19 made of PSG, BPSG or the like, forms a contact hole in a necessary part, and forms an aluminum wiring 20 and a passivation film 21 made of a nitride film or the like by means of a plasma CVD method, thereby producing a Bi-CMOS semiconductor device in which a CMOS transistor and a bipolar transistor are assembled (see Fig. 13).

In this way, the manufacturing method of the invention prevents etching from progressing to the pad oxide film 8a or an insulating film 13 and the like existing under the Si3N4 film 9 and the polycrystalline silicon 14 when the SiO2 film 10 is etched away in the parts of the separation trench 12. Accordingly, a problem of breakage or short-circuiting of a polycrystalline silicon wiring 16 or aluminum wiring 20 is not caused because the flatness of a region of the separation trench 12 can be achieved without generating level differences.

Furthermore, since the embodiment performs a C.D.E treatment and an annealing process after forming a separation trench, it can prevent crystal defects which are inevitably generated on the inner walls of the separation trench and its surrounding surface of the silicon substrate when the separation trench is formed. This will be described in detail below.

In the above-mentioned embodiment, after an insulating film 13 was formed on the inner walls of the separation trench 12, the insulating film 13, SiO2 film 8a and Si3N4 film 9 were etched away, crystal defects were revealed by a secco etching method, and the surface of the second silicon substrate 3 was observed by an optical microscope. Furthermore, the density of defects was calculated by counting the defects observed within a square each having a side length of 200 µm. The result is shown in Fig. 18.

For comparison, the density of defects was also examined in the same way for specimens that were processed with neither C.D.E treatment nor annealing process, with only annealing process, with annealing process and sacrificial oxidation process, with only C.D.E treatment, with C.D.E treatment and sacrificial oxidation process, and with C.D.E treatment and annealing process. The result is also shown in Fig. 18. In Fig. 18, a curve marked by + points shows the result of examining the middle part of the surface on the second silicon substrate 3, a curve marked by Ei shows the result of examining the upper part of the surface of the second silicon substrate 3, and a curve marked by A shows the result of examining the lower part of the surface of the second silicon substrate 3.

As a result, in substrates processed by neither a CD E treatment nor an annealing process, as well as by only one of the above, no reduction in the density of defects was seen, while crystal defects in the vicinity of the separation trench 12 on the surface of the second silicon substrate 3 were observed. That is, it was confirmed that a conventional method which only performs a sacrificial oxidation process and a CD E treatment cannot completely prevent crystal defects and completely solve problems caused by crystal defects. On the other hand, crystal defects could be prevented in both substrates processed by a CD E treatment and an annealing process and by a CD E treatment, an annealing process and a sacrificial oxidation process. As a result, it can be confirmed that it is possible to prevent crystal defects by applying at least a CD E treatment and an annealing process. Fig. 18 shows that its density of defects is 104 defects/cm², but this value comes from the measurement limit, and not every crystal defect was actually observed. The above-mentioned measurement of the density of defects was made only by observing the surface of the second silicon substrate 3, but as a result of examining a cross section of the second silicon substrate 3, the method of the embodiment could prevent crystal defects in the inner walls of the separation trench as well.

In this way, damaged layers which were generated on the inner wall of a recess and on the surface of a silicon substrate in the vicinity of the recess when the recess was formed can be completely removed by performing a CD E treatment on the inner wall of the recess in the silicon substrate. Furthermore, a damaged layer which was not completely removed by the CD E process and another damaged layer which was newly generated by the CD E treatment are restored by annealing the inner wall of the recess. In this way, it is possible to remove crystal defects which were generated on an inner wall of a recess and on the surface of a silicon substrate in the vicinity of the recess when the trench is formed, and to prevent current leakage problems caused by crystal defects.

The circumstances of the C.D.E treatment are not particularly limited, but it is desirable that they be circumstances that enable a damaged layer generated when a recess is formed to be completely etched away and further that the generation of a new damaged layer by the C.D.E process can be suppressed to the utmost. This C.D.E treatment etches the substrate to a depth of two to five times the damaged layer generated when the recess was formed.

Furthermore, the circumstances for the annealing are not particularly limited as long as it can restore a damaged layer which has not been completely removed by the C.D.E treatment and another damaged layer which has been newly generated by the C.D.E process, but it can be carried out under the conditions of heating for 10 to 30 minutes at 1000 to 1100°C in an inactive N₂ atmosphere, for example.

In the above-mentioned first embodiment, a first etch-back treatment of the polycrystalline silicon 14 is performed by a dry etching process, but it may also be performed by polishing.

[SECOND EMBODIMENT]

A second embodiment using a polycrystalline silicon film 9' instead of the Si₃N₄ film 9 in the above-mentioned first embodiment will be described below.

The present embodiment obtains an SOI substrate shown in Fig. 1 as mentioned above, forms a cushion oxide film 8a on the substrate as described above, deposits a polycrystalline silicon film 9' by the LP-CVD method and a SiO2 film 10 by a CVD method in order, and anneals the substrate at 1000°C to make the SiO2 film 10 dense in the same manner as shown in Fig. 2. Thereafter, the embodiment deposits a photoresist on the substrate, forms a photoresist pattern by means of a photolithography treatment, forms an opening 11 in the SiO2 film 10, the polycrystalline silicon film 9' and the cushion oxide film 8a by means of an R.I.E treatment using a CF4 or CHF3 series gas as an etching gas, and deposits a Si3N4 film 22 on the surface of the substrate (see Fig. 14). Further, the embodiment processes the substrate by means of anisotropic R.I.E treatment and leaves the Si3N4 film 22 only on the side walls of the opening 11 (see Fig. 15). The Si3N4 film 22 prevents the polycrystalline silicon film 9' exposed within the opening 11 from being oxidized at the same time that an insulating film 13 is formed on an inner wall of the separation trench 12 by means of thermal oxidation in the subsequent step.

Next, the embodiment selectively etches the second silicon substrate 3 using the SiO₂ film as a mask by an RI E process using an HBr series gas as an etching gas to form a separation trench 12 reaching to the insulating film 2, and processes the inner walls of the separation trench 12 by a CD E treatment and a annealing process in the order as described above. Further, an insulating film 13 is formed by thermally oxidizing the inner walls of the separation trench 12, and the Si₃N₄ film 22 covering the wall of the opening 11 is removed by an H₃PO₄ solution (see Fig. 16). As described above, in the case of forming the insulating film 13, the polycrystalline silicon film 9' is not oxidized after being covered by the Si₃N₄ film 22 in the opening 11. If the polycrystalline silicon film 9' is oxidized at this time, the oxidized part of the polycrystalline silicon film 9' is also etched by the etching liquid at the same time when the SiO₂ film 10 is etched away in the subsequent step, and this causes a level difference in the area of the separation trench 12.

Next, in the same manner as the step shown in Fig. 4, after depositing the polycrystalline silicon 14 (see Fig. 17), a Bi-CMOS semiconductor device is manufactured by going through the same steps as shown in Figs. 5 to 13.

In the present embodiment, since the polycrystalline silicon film 9' and the polycrystalline silicon 14 filled in the separation trench 12 act as an etching stopper when the SiO2 film 10 is removed, the cushion oxide film 8a under the polycrystalline silicon film 9' and the insulating film 13 are prevented from being etched at the same time. Since no oxidized part exists in the polycrystalline silicon film 9' as well, the etching does not proceed to deeper layers thereunder as described above.

Moreover, the present second embodiment can use the polycrystalline silicon film 9' at the same time at which the second etch-back process is applied to the polycrystalline silicon film 14.

[THIRD EMBODIMENT]

The above-mentioned first embodiment forms a pad silicon oxide film of uniform film thickness, forms a separation trench after depositing a Si3N4 film and a SiO2 film by means of a CVD method, performs in order the formation of an insulating film on the inner wall of the separation trench, filling the separation trench with polycrystalline silicon, etching back a protruding part of the polycrystalline silicon, and etching away the SiO2 film using the Si3N4 film and the polycrystalline silicon as an etching stopper, patterns the Si3N4 film or redeposits the Si3N4 film, and then forms a field oxide film by processing the pad silicon oxide film by means of a LOCOS process, but the Field oxide film 8 can be preformed using a LOCQS process. An example of this is shown in the third embodiment.

The third embodiment of the invention subjects a main surface of a first P-type single crystal silicon substrate 1 to mirror-like polishing and then forms an insulating film 2 of a specified thickness thereon by means of thermal oxidation. Furthermore, the third embodiment bonds a second single crystal silicon substrate 3 having a mirror-like polished main surface to the insulating film 2 side of the surface of the first silicon substrate 1 and heats them in a sufficiently pure atmosphere to bond them together so that the insulating film 2 is held between the respective silicon substrates 1 and 3. In this way, an SOI substrate is produced which is assembled by bonding the second silicon substrate 3 to the first silicon substrate 1 through the insulating film 2 (see Fig. 19). In Fig. 19, reference numeral 4 shows an N-type high-density impurity (Sb) layer which is formed by doping the surface of the second N-type silicon substrate 3 before bonding the two substrates.

Furthermore, the embodiment forms a P-well region 5, an N-well region 6 and a deep N+ region 7 on the second silicon substrate 3 side, which are formed into an SOI layer by means of a sequence of oxidation, photolithography and impurity diffusion process (see Fig. 20). During this period, an oxide film can be freely built up and removed on the surface of the second silicon substrate 3. Thereafter, a field oxide film 8 is formed on the surface of the second silicon substrate 3 side by means of a LOCOS process (see Fig. 21). Fig. 21 shows a state after removing a Si3N4 film with H3PO4 after performing oxidation by means of a LOCOS process.

Furthermore, the third embodiment deposits in order a Si₃N₄ film 9 as a first insulating layer and a SiO₂ film 10 as a second insulating layer on the surface of the substrate by means of a CVD process and anneals them at 1000°C to make the SiO₂ film 10 dense. Next, the embodiment deposits a photoresist not shown, and in a region where the field oxide film 8 is thick in film thickness, the embodiment forms an opening 11 reaching the surface of the silicon substrate 3 by selectively etching the SiO₂ film. 10, the Si₃N₄ film 9 and the field oxide film 8 using the photoresist as a mask by known photolithography and RI E processes using a CF₄ or CHF₃ series gas as an etching gas (see Fig. 22). Fig. 22 shows a state after stripping the photoresist.

Next, the embodiment forms a separation trench 12 reaching the insulating film 2 by selectively etching the second silicon substrate 3 using the SiO2 film 10 as a mask by means of an R.I.E process using an HBr series gas as an etching gas (see Fig. 23). In this case, the thickness of the SiO2 film 10 to be deposited in the previous step must be determined by the etching rates of the SiO2 film 10 and the silicon substrate 3 so that the separation trench 12 can successfully reach the insulating film 2.

Next, the surface of the inner walls of the separation trench 12 is subjected to C.D.E treatment. This C.D.E treatment is carried out by means of an RF discharge type plasma etching apparatus under, for example, the conditions of material gases of CF4, O₂ and N₂, a discharge frequency of 13.56 MHz, an etching rate of 50 nm/min (1500K/min) and a distance of the plasma from the wafer of 100 cm. In this way, the inner walls of the separation trench 12 are etched by about 150 nm (1500 Å).

Next, the inner walls of the separation trench 12 are annealed in the C.D.E treatment. This annealing process is carried out, for example, by heating for 30 minutes at 1000°C in a N₂ atmosphere.

Next, a sacrificial oxidation process may be applied to the annealed inner walls of the isolation trench 12. In this sacrificial oxidation process, for example, after forming a 50 nm (500 Å) sacrificial oxide film using a dry oxidation process at 1000°C, this sacrificial oxidation film is then removed with fluoric acid.

Further, an insulating film 13 is formed on the inner walls of the separation trench 12 by wet thermal oxidation at, for example, 1050°C, and then polycrystalline silicon 14 is deposited thereon by LP-CVD. At this time, the polycrystalline silicon not only fills the separation trench 12, but also overlies the SiO2 film 10 (see Fig. 24).

Thereafter, the polycrystalline silicon 14 overlying the SiO2 film 10 is etched back (for the first time) by a dry etching process (see Fig. 25). At this time, the etching process is stopped so that the tip of the polycrystalline silicon 14 remaining in the separation trench 12 can be higher than the Si3N4 film 9.

Next, the SiO2 film 10 is etched away by a wet etching process using a fluorine solution (see Fig. 26). In this case, since the Si3N4 film 9 and the polycrystalline silicon 14, which is left so that its tip may be higher to the part than the Si3N4 film 9, act as etching stoppers, the field oxide film 8 under the Si3N4 film 9 and the insulating film 13 formed on the inner walls of the separation trench 12 are not etched.

Next, the part of the polycrystalline silicon 14 filled in the separation trench 12 which is above the Si₃N₄ film 9 is etched away (for the second time) (see Fig. 27). In this case, it is desirable to set the tip of the polycrystalline silicon 14 to be 0.3 µm lower than the tip of the field oxide film 8 so that when a thermal oxide film 15, which will be described later, is formed on the polycrystalline silicon 14 in the subsequent step, the thermal oxide film 15 comes to the same level as the surrounding field oxide film 8.

Next, after the oxide film 15 is built up by thermally oxidizing the tip of the polycrystalline silicon 14 filled in the separation trench 12 through the Si3N4 film 9 (see Fig. 28), the Si3N4 film 9 is etched away (see Fig. 29). As can be clearly seen from Fig. 29, a portion of the separation trench 12 is kept flat without generating a level difference.

Furthermore, the third embodiment forms a thin gate oxide film after removing a pad oxide film 8a, then forms a polycrystalline silicon wiring (gate electrode) 16 by means of an LP-CVD method, a photolithography process and an etching process, and forms a P+ diffusion layer 17 and an N+ diffusion layer 18 by means of selective doping (see Fig. 30). During this time, since an etching depth of the field oxide film 8 is about 0.2 µm, the flatness of the region of the isolation trench 12 is not deteriorated.

After all this, the present embodiment deposits an interlayer insulating film 19 made of PSG, BPSG or the like, creates a contact hole in a necessary part and forms an aluminum wiring 20 and a passivation film 21 made of a nitride film or the like is produced by means of a plasma CVD process, and thus produces a Bi-CMOS semiconductor device in which a CMOS transistor and a bipolar transistor are combined (see Fig. 31).

In this way, a manufacturing method of the invention prevents the progress of etching in an oxide film such as a field oxide film 8 or an insulating film 13 and the like existing under the Si3N4 film 9 and the polycrystalline silicon 14 when the SiO2 film 10 is etched away in the region of the separation trench 12. Therefore, since the flatness of the region of the separation trench 12 can be achieved without causing a level difference, such problems as breakage or short-circuiting of a polycrystalline silicon wiring 16 or aluminum wiring 20 are not caused.

Furthermore, in the above-mentioned conventional method shown in Figs. 37 and 38, after a separation trench 35 is formed in a region where the field oxide film 32 is thin in film thickness, a burred portion B of the silicon substrate 31 is located around the upper edge of the separation trench 35 so that the etched-back tip of the polycrystalline silicon 37 is lower than the burred portion B. Therefore, a vertical beak A is formed in a corner when an oxide film 38 is formed on the tip of the polycrystalline silicon 37, and as a result, a problem has been caused that crystal defects are easily generated by stress concentration at the burred portion B of the silicon substrate 31.

In the present embodiment, after a separation trench is formed in a region where a field oxide film 8 is thick in terms of film thickness and the Since the tip of the polycrystalline silicon 14 which has undergone the second etch-back process is higher than the tip of the second silicon substrate 3 (see Fig. 27), crystal defects are not generated when the polycrystalline silicon 14 is oxidized without the stress concentration in the second silicon substrate 3 caused by vertical beak-up as occurs in a conventional method which forms a separation trench in a region where a field oxide film 8 is thin in film thickness (see Figs. 37 and 38). Thus, current leakage caused by crystal defects can be prevented. Furthermore, unlike the conventional method which forms a separation trench in a region where the field oxide film 8 is thin in film thickness, the present embodiment does not need to manufacture a semiconductor which is larger in dimension to allow for some deviation in mask coverage, so that it can make the semiconductor device smaller in dimension.

In this way, the embodiment makes it possible to form a separation trench in a region where a field oxide film is thick in terms of film thickness without deteriorating the flatness of a silicon substrate. Therefore, since it is not necessary to allow certain deviations in mask coverage and the occurrence of crystal defects of a silicon substrate is also prevented, a semiconductor device can be manufactured which does not have breakage or short-circuiting of polycrystalline silicon wiring and aluminum wiring and which does not need to be made unnecessarily large in size.

Furthermore, since a separation trench is formed after the formation of a field oxide film, it is assumed that the occurrence of crystal defects around the separation trench can be prevented. That is, when a field oxide film is formed after the formation of a separation trench, there is a fear that the volume expands when the field oxide film is formed and crystal defects are generated by stress concentration at the boundary between a silicon substrate and a separation trench, whereas the present embodiment has no such fear.

Furthermore, the present embodiment subjects an inner wall of the separation trench 12 to a C.D.E treatment and an annealing process. Therefore, the embodiment enables a damaged layer generated on the inner wall of the separation trench 12 in the formation of the separation trench to be completely or completely removed by means of a C.D.E treatment, the damaged layer not completely removed by the C.D.E treatment and another damaged layer newly generated by the C.D.E process to be removed by means of the subsequent annealing process, and elimination of crystal defects on the inner walls and the like of the separation trench 12 becomes possible.

In the above-mentioned third embodiment, the first etching back process of the polycrystalline silicon 14 is carried out by a dry etching process, but may also be carried out by a polishing process.

[FOURTH EMBODIMENT]

The fourth embodiment, which uses a polycrystalline silicon film 9' instead of the Si₃N₄ film 9 used in the third embodiment, will be described below.

After a substrate is processed in the steps shown in Figs. 19 to 21, the present embodiment deposits a polycrystalline silicon film 9' by an LP-CVD method and a SiO₂ film 10 by a CVD method in order, and anneals the substrate at 1000°C in the same manner as the process shown in Fig. 22 to make the SiO₂ film 10 dense. Thereafter, the present embodiment deposits a photoresist, forms a photoresist pattern by a photolithography process, creates an opening 11 in the Si3N4 film 10, the polycrystalline silicon film 9' and the field oxide film 8 by an R.I.E process using a CF4 or CHF3 based gas as an etching gas, and deposits a Si3N4 film 22 on the surface of the substrate (see Fig. 32). Furthermore, the embodiment leaves the Si3N4 film 22 only on a side wall of the opening 11 by an anisotropic R.I.E process (see Fig. 33). The Si3N4 film 22 protects the polycrystalline silicon film 9' exposed in the opening 11 from being oxidized at the same time that an insulating film 13 is formed on an inner wall of the separation trench 12 by thermal oxidation in the subsequent step.

Next, the embodiment etches the second silicon substrate 3 using the SiO₂ film 10 as a mask by an RI E process using an HBr series gas as an etching gas to form the separation trench 12 reaching the insulating film 2, subjects the inner wall of the separation trench 12 to a CD E treatment and an annealing process as described above and forms the insulating film 13 by thermal oxidation, and then removes the Si₃N₄ film 22 covering the surface of the wall of the opening 11 by an H₃PO₄ solution (see Fig. 34). How As described above, in the case of forming the insulating film 13, the polycrystalline silicon film 9' is not oxidized because it is covered by the Si₃N₄ film 22 in the opening 11. If the polycrystalline silicon film 9' is oxidized at this time, the oxidized part of the polycrystalline silicon 9' also undergoes etching by the etching liquid at the same time that the SiO₂ film 10 is etched away in the subsequent step, and this causes level differences in the region of the separation trench.

Next, in the same manner as the step shown in Fig. 24, after depositing the polycrystalline silicon 14 (see Fig. 35) by going through the same steps as shown in Figs. 25 to 31, a Bi-CMOS semiconductor device as shown in Fig. 31 is manufactured.

In the present embodiment, since the polycrystalline silicon film 9' and the polycrystalline silicon 14 filled in the separation trench 12 act as an etching stopper when etching away the SiO₂ film, the field oxide film 8 and the insulating film 13 under the polycrystalline silicon film 9' are prevented from being etched at the same time. And as described above, since there is no oxidized part in the polycrystalline silicon film 9', the etching does not proceed to a deeper layer from there.

Moreover, the present fourth embodiment can remove the polycrystalline silicon film 9' at the same time that the polycrystalline silicon film 14 is subjected to the second etch-back process.

In the above-mentioned various embodiments, how an oxide film for use as a mask in molding a separation trench, a SiO₂ film is formed by a CVD method, but a PSG (phospho silicate glass) film can also be formed instead of the SiO₂ film.

INDUSTRIAL APPLICABILITY

According to a manufacturing method of the invention described above, an insulating film in a recess, a field oxide film around the recess, or the like can be prevented from being etched at the same time that a film used as a mask in forming the recess is etched away. Therefore, such disadvantages as a local reduction in dielectric strength in a region of a recess, deterioration in the flatness of the surface of a substrate in the region of a recess, and the like are not caused, and a semiconductor device having a trench of high reliability in a wiring layer can be provided, furthermore, the invention is very effective in manufacturing an SOI substrate having a separation trench.

Claims (13)

1. A method for producing a semiconductor device, comprising the steps: [a] depositing a first layer (9, 9') and a second layer (10) on the main surface of a semiconductor layer (3, 4) on an insulating substrate (2) in order, the semiconductor layer (3, 4) on the insulating layer (2) forming an SOI substrate; [b] forming an opening (11) in the first layer (9, 9') and the second layer (10) which exposes a portion of the main surface of the semiconductor layer (3); [c] forming a recess (12) which forms a trench (12) extending through the insulating substrate (2) by etching the semiconductor layer (3, 4) through the opening (11) using the second layer (10) as a mask; [d] oxidizing the portion of the semiconductor layer (3, 4) exposed as walls of the recess (12) without oxidizing the first layer (9, 9), thereby forming an insulating layer (13) on the walls; [e] filling the recess (12) having the oxidized semiconductor walls with a filler (14) through the opening until an upper surface of the filler (14) becomes higher than the upper surface of the first layer (9, 9'), the filler contacting the first layer (9, 9) at the opening; and [f] removing the second layer (10) using the filler (14) whose upper surface is higher than the upper surface of the first layer (9, 9) and the first layer (9, 9') as an etching stopper, thereby preventing the insulating layer (13) located under the contact portion between the first layer (9, 9') and the filler (14) from being etched during the removal of the second layer (10). 2. Method for producing a semiconductor device according to claim 1, characterized by a further step of selectively removing the first layer (9; 9') after the step of removing the second layer. 3. Method for producing a semiconductor device according to claim 1 or 2, characterized by the further steps Processing an inner wall of the recess (12) by means of a chemical dry etching process; and Baking the inner wall of the recess processed by the chemical dry etching process; after the step of forming a recess (12) by etching the semiconductor substrate. 4. A method of manufacturing a semiconductor device according to claim 3, characterized in that the process of annealing is a process of heating the semiconductor substrate to about 1000 to 1100°C in an atmosphere of an inactive gas. 5. A method for producing a semiconductor device according to claim 4, characterized in that the inactive gas is nitrogen. 6. A method for producing a semiconductor device according to one of claims 1 to 5, characterized in that the step of filling the recess includes the steps : Filling the recess (12) with the filler (14) through the opening; and Exposing the second layer (10) by etching back a portion of the filler applied to the surface of the second layer until an upper surface of the filler is lower than the height of the second layer but higher than the height of the first layer whereby the filler contacts the first layer (9, 9') at the opening. 7. A method for producing a semiconductor device according to one of claims 1 to 6, characterized by a further step of oxidizing a surface (15) of the filler (14) using the first layer (9) as a mask after removing the second layer (10). 8. Method for producing a semiconductor device according to one of claims 1 to 7, characterized in that the first layer (9) is a silicon nitride layer, the second layer (10) is a silicon oxide layer and the insulating layer (13) is a silicon oxide layer. 9. A method of manufacturing a semiconductor device according to any one of claims 1 to 6, characterized by a step of covering an end side of the first layer (9) exposed within the opening (11) with an oxidation-resistant layer (22) after the step of forming the opening (11) in the first and second layers, but before the step of forming the recess (12). 10. A method for manufacturing a semiconductor device according to claim 9, characterized by a further step of removing the oxidation-resistant layer (22) after the step of forming the insulating layer (13) on the inner wall of the recess. 11. Method for producing a semiconductor device according to claim 9 or 10, characterized in that the first layer (9) is a polycrystalline silicon layer, the second layer (10) is a silicon oxide layer, the insulating layer (13) is a silicon oxide layer and the oxidation-resistant layer (22) is a silicon nitride layer. 12. A method of manufacturing a semiconductor device according to any one of claims 1 to 11, characterized by a further step - before the step of depositing the first and second layers on the main surface of the semiconductor substrate - of forming a silicon oxide layer (8, 8a) on the main surface of the semiconductor substrate (3) to provide a thick portion (8) at a region corresponding to a field region of the semiconductor device, and characterized in that the step of forming the opening in the first and second layers includes a step of forming the opening (11) in the thick portion (8) of the silicon oxide layer (8, 8a) through a surface of the semiconductor substrate (3). 13. Method for producing a semiconductor device according to one of claims 1 to 12, characterized in that the filler (14) is polycrystalline silicon.