CN112103240A - SOI-based dielectric isolation structure manufacturing method and dielectric isolation structure - Google Patents

SOI-based dielectric isolation structure manufacturing method and dielectric isolation structure Download PDF

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Publication number
CN112103240A
CN112103240A CN202011051681.6A CN202011051681A CN112103240A CN 112103240 A CN112103240 A CN 112103240A CN 202011051681 A CN202011051681 A CN 202011051681A CN 112103240 A CN112103240 A CN 112103240A
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silicon
isolation structure
dielectric isolation
soi
layer
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邵同盟
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Shitemei Suzhou Measurement And Control Technology Co ltd
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Shitemei Suzhou Measurement And Control Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A manufacturing method of a dielectric isolation structure based on SOI and the dielectric isolation structure are disclosed, the manufacturing method comprises: carrying out oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to obtain a silicon dioxide layer, and then depositing a silicon nitride layer; depositing a photoresist film on the silicon nitride layer, and adopting negative photoresist contact exposure; performing dry etching on the silicon nitride layer, performing wet etching on the silicon dioxide layer, and then performing deep groove etching; removing the photoresist; oxidizing and growing silicon dioxide with the thickness of 1.7-1.8 mu m on the inner side wall of the etched groove, wherein the air pressure of the growing environment is more than ten standard atmospheric pressures; depositing polycrystalline silicon by low-pressure chemical vapor deposition, wherein the grooves formed by etching are filled with the polycrystalline silicon; carrying out surface planarization on the polycrystalline silicon; and removing the silicon nitride layer, and performing field oxidation. The invention has low complexity of the manufacturing process, good insulating property between the high voltage area and the low voltage area of the dielectric isolation structure and the breakdown voltage of more than 880V.

Description

SOI-based dielectric isolation structure manufacturing method and dielectric isolation structure
Technical Field
The invention relates to the technical field of SOI (silicon on insulator), in particular to a manufacturing method of a dielectric isolation structure based on SOI and the dielectric isolation structure.
Background
The SOI (Silicon-On-Insulator) technology is used as an all-dielectric isolation technology, effectively overcomes the defects of bulk Silicon materials by using a unique structure, fully develops the potential of a Silicon integrated circuit technology, and is gradually becoming a mainstream technology for manufacturing a super-large-scale integrated circuit with high speed, low power consumption, high integration and high reliability. The SOI technology adopts full-medium isolation, thoroughly eliminates the parasitic latch-up effect of CMOS (Complementary Metal Oxide Semiconductor) devices, reduces single-particle upset interfaces, has excellent single-particle resistance and instantaneous irradiation capability, enables the SOI chip to work in the worst cosmic ray environment, and is widely applied in space science. However, the charge trapping and interface states generated in the oxide layer by the total dose ionization damage cause inversion of the silicon substrate near the isolation oxide layer and parasitic transistor leakage at a certain source-drain bias.
In addition, the structure or material of the medium isolation region is improved to a certain extent in the prior art, so that the opening of a parasitic channel is inhibited. However, in either method, the process complexity is increased to some extent, so that the manufacturing cost of the transistor device is increased. However, for the SOI process of a thick silicon film, the difficulty of the all-dielectric isolation process between devices is high, the complexity is high, and the shallow trench isolation technology cannot meet the circuit requirements.
The prior art lacks a manufacturing process of a medium isolation structure based on an SOI process of a thick silicon film.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a manufacturing method of a dielectric isolation structure based on an SOI and the dielectric isolation structure, and the specific technical scheme is as follows:
in one aspect, a method for fabricating a dielectric isolation structure based on SOI is disclosed, which enables the breakdown voltage of the dielectric isolation structure to be greater than 880V on the SOI with a silicon film thickness of 20 μm, the method comprising the steps of:
s1, carrying out oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to form a silicon dioxide layer of 50-55nm, wherein the SDB silicon wafer is made of an SOI material;
s2, depositing a 55-60nm silicon nitride layer on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and exposing by adopting a negative photoresist contact mode, wherein the thickness of the film is more than 1 mu m;
s4, carrying out dry etching on the silicon nitride layer, carrying out wet etching on the silicon dioxide layer, and carrying out deep groove etching to form a groove with the width more than 5 microns and less than 6.2 microns;
s5, removing the residual photoresist;
s6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed in the step S4, wherein the air pressure of the growing environment is greater than ten standard atmospheric pressures, and the growing thickness range of the silicon dioxide is 1.7-1.8 μm;
s7, depositing polycrystalline silicon on the surface layer of the semi-finished structure formed in the step S6 by using low-pressure chemical vapor deposition, wherein the deposition thickness of the polycrystalline silicon is more than 3 mu m, and the grooves formed by etching are filled with the polycrystalline silicon;
s8, carrying out surface planarization on the polycrystalline silicon;
and S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
Further, the SDB silicon wafer includes, from top to bottom, a top layer silicon, a buried oxide layer, and a substrate, and the trench obtained in step S4 is etched to the buried oxide layer.
Further, before step S1, an SDB silicon wafer is fabricated, wherein the top silicon layer has a thickness of 20 μm and the buried oxide layer has a thickness in the range of 5-6 μm.
Preferably, in step S8, a CMP process is used to planarize the surface of the polysilicon.
Preferably, the pressure of the growth environment in step S6 is 10.8 atm, and the growth thickness of the silicon dioxide is in the range of 1.76 μm.
Preferably, step S4 deep trench etching results in a trench having a width of 6.1 μm.
Optionally, the wet etching solution used in the wet etching process in step S4 includes any one of KOH, EPW, and TMAH.
On the other hand, the SOI-based dielectric isolation structure is disclosed and is manufactured by the manufacturing method.
Further, the thickness of the top silicon layer on the SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is more than 880V.
The technical scheme of the invention has the beneficial effects that:
(a) the dielectric isolation structure is applied to a thick silicon film SOI process, and the breakdown voltage of the dielectric isolation structure reaches more than 880V;
(b) the insulating property between the high-voltage area and the low-voltage area of the dielectric isolation structure is good, and the manufacturing process complexity is low.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flow chart of a method for fabricating an SOI-based dielectric isolation structure according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood and more clearly understood by those skilled in the art, the technical solutions of the embodiments of the present invention will be described in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of a portion of the invention and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. In addition, the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In one embodiment of the present invention, a method for fabricating a dielectric isolation structure based on SOI is provided, so as to realize a breakdown voltage of the dielectric isolation structure greater than 880V on an SOI with a silicon film thickness of 20 μm, as shown in fig. 1, the method comprises the following steps:
firstly, manufacturing an SDB silicon wafer, wherein the SDB silicon wafer comprises top silicon, an oxygen burying layer and a substrate from top to bottom, the thickness of the top silicon is 20 microns, and the thickness range of the oxygen burying layer is 5-6 microns.
S1, carrying out oxidation pretreatment on the upper surface of the top silicon of a Silicon Direct Bonding (SDB) silicon wafer to form a silicon dioxide layer of 50-55nm, wherein the SDB silicon wafer is made of an SOI material;
s2, depositing a 55-60nm silicon nitride layer on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and exposing by adopting a negative photoresist contact mode, wherein the thickness of the film is more than 1 mu m;
and S4, performing dry etching on the silicon nitride layer, performing wet etching on the silicon dioxide layer, and performing deep groove etching to form a groove with the width larger than 5 microns and smaller than 6.2 microns (preferably 6.1 microns), wherein the groove is etched to the buried oxide layer.
Specifically, the expected depth of the medium isolation groove can be obtained by controlling the size of an etching window and the etching time by adopting a wet etching process, so that the simultaneous completion of the full medium isolation and partial isolation structure of the thick silicon film SOI integrated circuit is realized, the integration level of the integrated circuit is improved, the photoetching frequency is reduced, the process is simple and controllable, and the damage is small. The wet etching solution adopted by the wet etching process comprises any one of KOH (potassium hydroxide), EPW (ethylenediamine and pyrocatechol) and TMAH (tetramethylammonium hydroxide).
S5, removing the residual photoresist;
and S6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed by etching in the step S4, wherein the pressure of the growth environment is greater than ten standard atmospheric pressures, and the growth thickness of the silicon dioxide ranges from 1.7 to 1.8 μm (preferably 1.76 μm).
One of the core inventions of the present invention is that a high-pressure environment of 10.8 atm is preferably used to oxidize and grow silicon dioxide on the inner sidewall of the etched trench, which plays a key role in raising the breakdown voltage of the dielectric isolation structure.
S7, depositing polycrystalline silicon on the surface layer of the semi-finished structure formed in the step S6 by Low Pressure Chemical Vapor Deposition (LPCVD), wherein the deposition thickness of the polycrystalline silicon is more than 3 mu m, and the grooves formed by etching are filled with the polycrystalline silicon;
the full-medium isolation groove is filled with polycrystalline silicon, so that long-time high-temperature annealing of the traditional isolation process is avoided, the influence on total dose strengthening impurity diffusion is reduced, and the total dose irradiation resistance of the device is improved; the isolation process has little influence on other process processes, and can be completed before the trap injection of the device or before the gate oxide.
And S8, performing surface planarization on the polysilicon.
The polysilicon is preferably surface planarized using a Chemical Mechanical Polishing (CMP) process. CMP is a process in which a workpiece to be polished is pressed against a rotating elastic polishing pad, a corrosive processing liquid is supplied to the workpiece, and when the workpiece is subjected to etching processing (chemical processing), a polishing material of ultrafine abrasive grains (diameter 100nm or less) is simultaneously supplied to selectively polish the convex portions of the workpiece (mechanical processing). CMP is introduced into the surface shaping of the dielectric isolation structure to reduce the field oxide taper angle height and improve the breakdown voltage of the dielectric isolation.
And S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
On the other hand, the SOI-based dielectric isolation structure is disclosed and is manufactured by the manufacturing method.
Further, the thickness of the top silicon layer on the SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is more than 880V.
The medium isolation method is applied to the thick silicon film SOI process, alkaline wet etching is adopted, medium isolation grooves with different depths can be simultaneously realized, so that full medium isolation among devices is realized, the integration level of a circuit is improved, the photoetching times are reduced, the process manufacturing cost is reduced, and meanwhile, the process is simple and has small difficulty. The isolation process adopted by the invention can avoid long-time high-temperature annealing of the isolation structure, can reduce the influence on total dose reinforcement impurity diffusion in the application of a radiation-resistant circuit, improves the total dose irradiation resistance of the device, and simultaneously eliminates the parasitic latch-up effect of a CMOS device through full-medium isolation.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. A method for manufacturing a dielectric isolation structure based on SOI is characterized in that the breakdown voltage of the dielectric isolation structure realized on the SOI with the silicon film thickness of 20 μm is more than 880V, and the method comprises the following steps:
s1, carrying out oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to form a silicon dioxide layer of 50-55nm, wherein the SDB silicon wafer is made of an SOI material;
s2, depositing a 55-60nm silicon nitride layer on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and exposing by adopting a negative photoresist contact mode, wherein the thickness of the film is more than 1 mu m;
s4, carrying out dry etching on the silicon nitride layer, carrying out wet etching on the silicon dioxide layer, and carrying out deep groove etching to form a groove with the width more than 5 microns and less than 6.2 microns;
s5, removing the residual photoresist;
s6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed in the step S4, wherein the air pressure of the growing environment is greater than ten standard atmospheric pressures, and the growing thickness range of the silicon dioxide is 1.7-1.8 μm;
s7, depositing polycrystalline silicon on the surface layer of the semi-finished structure formed in the step S6 by using low-pressure chemical vapor deposition, wherein the deposition thickness of the polycrystalline silicon is more than 3 mu m, and the grooves formed by etching are filled with the polycrystalline silicon;
s8, carrying out surface planarization on the polycrystalline silicon;
and S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
2. The method for fabricating an SOI-based dielectric isolation structure as claimed in claim 1, wherein the SDB silicon wafer comprises a top layer silicon, a buried oxide layer and a substrate from top to bottom, and the trench obtained in step S4 is etched to the buried oxide layer.
3. The method of claim 2, wherein before step S1, an SDB silicon wafer is fabricated, wherein the top silicon layer has a thickness of 20 μm and the buried oxide layer has a thickness in the range of 5-6 μm.
4. The method of claim 1, wherein in step S8, a CMP process is used to planarize the surface of the polysilicon.
5. The method as claimed in claim 1, wherein the pressure of the growth environment in step S6 is 10.8 atm, and the thickness of the silicon dioxide is 1.76 μm.
6. The method for fabricating an SOI-based dielectric isolation structure as claimed in claim 1, wherein the step S4 deep trench etching results in a trench with a width of 6.1 μm.
7. The method for fabricating an SOI-based dielectric isolation structure as claimed in claim 1, wherein the wet etching solution adopted in the wet etching process in step S4 includes any one of KOH, EPW and TMAH.
8. An SOI-based dielectric isolation structure, characterized by being produced by a method of production as claimed in any one of claims 1 to 7.
9. The dielectric isolation structure of claim 8 wherein the top silicon on SOI has a thickness of 20 μm and the dielectric isolation structure has a breakdown voltage of greater than 880V.
CN202011051681.6A 2020-09-29 2020-09-29 SOI-based dielectric isolation structure manufacturing method and dielectric isolation structure Pending CN112103240A (en)

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