CN112909079B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN112909079B CN112909079B CN202110258183.7A CN202110258183A CN112909079B CN 112909079 B CN112909079 B CN 112909079B CN 202110258183 A CN202110258183 A CN 202110258183A CN 112909079 B CN112909079 B CN 112909079B
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 230000008569 process Effects 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 230000004888 barrier function Effects 0.000 claims abstract description 48
- 238000000227 grinding Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 4
- 239000012530 fluid Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 6
- 238000005498 polishing Methods 0.000 description 13
- 238000001039 wet etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229920006318 anionic polymer Polymers 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
In a semiconductor device and a method of forming the same provided by the present invention, a method of forming a semiconductor device includes the steps of: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure; flattening the shallow trench structure through a DSTI CMP process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the planarization effect of the DSTI CMP process is better, the CMP dishing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI recess is smaller, the problem that the MOSFET device is started earlier due to the concentration of the tip electric field of the STI recess region is solved, and the leakage current of the MOSFET device is reduced.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being operated at a faster speed. The greater the data storage capacity and the more functions, the more advanced the semiconductor device is towards higher element density and high integration, and the higher the requirements on its physical structure and manufacturing process are. Whereas MOSFET (Metal-Oxide-semiconductor field effect transistor) devices suffer from leakage. Among them, STI (shallow trench isolation ) recess (divot) is one of the causes of leakage of MOSFET devices. In general, the deeper the STI recess, the more pronounced the leakage of the MOSFET device.
As shown in fig. 1, the gate structure 11 of the MOSFET device includes a gate oxide layer and gate polysilicon formed in sequence. One of the reasons for causing the electric leakage of the STI recess is that the gate oxide layer at the boundary between the active region (ACT) and the STI (namely, at the region a) is thinner, specifically, the gate oxide layer is generated in a thermal oxidation mode, the stress at the boundary between the active region and the STI is larger, so that oxygen atoms are difficult to enter the active region, silicon dioxide is formed with the silicon substrate of the active region, and finally, the gate oxide layer at the boundary between the active region and the STI is thinner, so that devices in the region are easier to open, and the electric leakage of the region is increased; the second reason why the STI recess causes the leakage is that in the region a, the electric field is concentrated in the region a during the subsequent process of forming the gate structure 11, so that the device in the region is easier to open, and the leakage in the region increases.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can reduce the occurrence of STI (shallow trench isolation) dent so as to reduce the leakage current of a MOSFET (metal oxide semiconductor field effect transistor) device.
In order to achieve the above object, the present invention provides a method for forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a barrier layer on the semiconductor substrate;
forming a shallow trench structure in the semiconductor substrate;
flattening the shallow trench structure through a DSTI CMP process; and
and removing the barrier layer.
Optionally, the thickness of the barrier layer is
Optionally, a first pad oxide layer is further formed on the semiconductor substrate before forming the barrier layer on the semiconductor substrate.
Further, forming a shallow trench structure in the semiconductor substrate includes:
sequentially etching the barrier layer, the first underlying oxide layer and the semiconductor substrate, and stopping etching in the semiconductor substrate to form a shallow trench;
thermally treating the semiconductor substrate to form a second underlying oxide layer in the shallow trench; and
and forming a filling layer in the shallow trench to form a shallow trench structure.
Further, the filling layer is formed in the shallow trench through a high-density plasma oxide layer deposition process, and the filling layer is also formed on the barrier layer at the same time.
Further, the material of the filling layer comprises silicon dioxide, and the material of the blocking layer comprises silicon nitride.
Further, when the shallow trench structure is planarized by a DSTI CMP process, a polishing solution with a high selectivity of the filling layer to the barrier layer is selected.
Further, after the DSTI CMP process, the filling layer with partial thickness of the STI is etched and removed through an etching process.
Further, a gate structure, a source region and a drain region are sequentially formed on the semiconductor substrate, so that a semiconductor device is formed, wherein the source region and the drain region are located between adjacent shallow trench structures, the gate structure is located between the source region and the drain region, and the source region and the drain region are separated.
On the other hand, the invention also provides a semiconductor device which is prepared by the method.
Compared with the prior art, the invention has the following beneficial effects:
in a semiconductor device and a method of forming the same provided by the present invention, a method of forming a semiconductor device includes the steps of: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure in the semiconductor substrate; flattening the shallow trench structure through a DSTI CMP process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the planarization effect of the DSTI CMP process is better, the CMP dishing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI recess is smaller, the problem that the MOSFET device is started earlier due to the concentration of the tip electric field of the STI recess region is solved, and the leakage current of the MOSFET device is reduced.
Further, the thickness of the barrier layer isSo that the thickness of the barrier layer is greater than +.>In the aspect of the invention, the thickness is thinned, the stress at the boundary between the active region and the STI is reduced, the risk of STI dent generated in the subsequent mechanical grinding process and wet etching process is reduced, and simultaneously, the occurrence of cracks on the surface of the barrier layer and the surface of the semiconductor substrate positioned below the barrier layer in the mechanical grinding process is avoided.
Drawings
Fig. 1 is a top view of a semiconductor device having STI recesses;
fig. 2 is a schematic cross-sectional view of a prior art semiconductor device;
fig. 3 is a flow chart illustrating a method for forming a semiconductor device according to an embodiment of the invention;
fig. 4a-4e are schematic cross-sectional views illustrating a method for forming a semiconductor device according to an embodiment of the present invention.
Reference numerals illustrate:
in fig. 1-2:
11-gate structure; 12-a pad oxide layer; 13-underlying silicon nitride layer; 14-HDP layer;
in fig. 4a-4 e:
100-a semiconductor substrate; 111-a first pad bottom oxide layer; 112-a second underlying oxide layer; 120-barrier layer, 130-fill layer.
Detailed Description
As described in the background, the stress at the boundary of the active region and the STI is larger, which eventually results in a thinner gate oxide at the boundary of the active region and the STI. As shown in fig. 2, stress at the boundary of the active region and the STI is formed for two reasons: one of the reasons is that when STI linear (i.e., forming the liner oxide layer 12 in the shallow trench, the material of the liner oxide layer 12 is silicon dioxide), oxygen atoms need to enter the silicon lattice because the process is a thermal diffusion process, but because the silicon lattice at the inner corner region of the bottom of the STI is difficult to unload the stress caused by oxygen diffusion by deformation, oxygen diffusion is difficult to proceed, so the thickness of silicon dioxide at the inner corner region at the bottom of the STI is thinner, and the thickness of silicon dioxide at the outer corner region at the opening of the trench of the STI is thicker, as the opposite is true; the second reason is that, in the STI (high density plasma oxide layer) deposition process, the acceptance angle of the outer corner region is larger, so that the thickness of the HDP layer 14 of the HDP process of the outer corner region is thicker, while the thickness of the HDP layer 14 of the HDP process of the inner corner region is thinner, further, the thickness of the silicon dioxide of the outer corner region is thicker. Since the thermal expansion coefficient of silicon dioxide is lower than that of silicon, a concentrated compressive stress of silicon dioxide on the silicon substrate at the trench opening of the STI is formed in the outer corner region, and this compressive stress causes higher activation energy at the boundary between the active region and the STI during subsequent processes (for example, STI CMP (Chemical Mechanical Polishing) process and wet etching (wet standard) process), resulting in higher polishing rate of silicon dioxide by the STI CMP process and higher etching rate of silicon dioxide by the wet etching process, thereby causing STI dishing.
From the above analysis, it is clear that the thickness of the substrate nitride layer 13 will affect the magnitude of the stress in the STI external corner region. However, the thickness of the substrate nitride layer 13 may not be too thin, and when the thickness of the substrate nitride layer 13 is too thin, cracks may occur on the surface of the substrate nitride layer 13 during the subsequent STI CMP process, and the silicon substrate under the substrate nitride layer 13 may crack under the action of mechanical polishing force.
Based on the above study, the invention provides a semiconductor device and a forming method thereof, wherein the forming method of the semiconductor device has better planarization effect through DSTI CMP process than the STI CMP process in the prior art, and does not generate CMP dishing phenomenon on the grinding surface in the DSTI CMP process, so that the depth of the STI recess is smaller, thereby solving the problem of early turn-on of the MOSFET device caused by the concentration of the tip electric field of the STI recess region, namely reducing the leakage current of the MOSFET device.
The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
The embodiment provides a method for forming a semiconductor device. Fig. 3 is a flow chart of a method for forming a semiconductor device according to the present embodiment. As shown in fig. 3, the method comprises the steps of:
step S10: providing a semiconductor substrate;
step S20: forming a barrier layer on the semiconductor substrate;
step S30: forming a shallow trench structure in the semiconductor substrate;
step S40: flattening the shallow trench structure through a DSTI CMP process; and
step S50: and removing the barrier layer.
A method of forming a semiconductor device according to this embodiment will be described in detail with reference to fig. 3 to 4.
Fig. 4a is a schematic cross-sectional view of a semiconductor substrate according to this embodiment. As shown in fig. 4a, step S10 is first performed to provide a semiconductor substrate 100.
The semiconductor substrate 100 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, may be a die, may be a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, but is not limited to, a silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, etc. In this embodiment, a first underlying oxide layer 111 is formed on the semiconductor substrate 100.
Fig. 4b is a schematic cross-sectional view of the present embodiment after forming a barrier layer. As shown in fig. 4b, step S20 is then performed to form a barrier layer 120 on the semiconductor substrate. The material of the barrier layer 120 is, for example, silicon nitride. The thickness of the barrier layer 120 isThe specific thickness is, for example-> Etc. which is greater than +.>In terms of thickness reduction, the stress at the boundary of the active region and the STI is reduced, the risk of STI dishing during the subsequent mechanical polishing process and wet etching process is reduced, and at the same time, cracks on the surface of the barrier layer 120 and the surface of the semiconductor substrate 100 located under the barrier layer 120 during the mechanical polishing process are avoided.
Fig. 4c is a schematic cross-sectional view of the present embodiment after forming a barrier layer. As shown in fig. 4c, step S30 is then performed to form a shallow trench structure in the semiconductor substrate.
The method specifically comprises the following steps:
first, the barrier layer 120, the first underlying oxide layer 111, and the semiconductor substrate 100 are sequentially etched, and etching is stopped in the semiconductor substrate 100 to form a shallow trench. In this embodiment, the barrier layer 120, the first underlying oxide layer 111 and the semiconductor substrate 100 may be sequentially etched by a dry etching process, and the etching is stopped in the semiconductor substrate 100 to form shallow trenches, and the semiconductor substrate between adjacent trenches is used to form an active region.
Next, the semiconductor substrate 100 is heat-treated to form a second underlying oxide layer 112 in the shallow trench, for example, an STI liner process, which forms a thinner silicon dioxide layer at the inner corner region of the bottom of the shallow trench, and forms a thicker silicon dioxide film layer at the outer corner region of the opening of the shallow trench, that is, the heat treatment process forms a thinner second underlying oxide layer 112 at the inner corner region of the shallow trench, and forms a thicker second underlying oxide layer 112 at the outer corner region. The thinning of the barrier layer 120 in this embodiment reduces the influence of the thicker thickness of the second underlying oxide layer 112 formed in the outer corner region in this step on the subsequent process.
Next, a filling layer 130 is formed in the shallow trench to form a shallow trench structure. The filling layer is formed in the shallow trench by, for example, an HDP (high density plasma oxide) deposition process, and is also formed on the barrier layer 120, and a specific material of the filling layer 130 is, for example, silicon dioxide. This step forms thicker silicon dioxide in the outer corner regions of the shallow trenches, which is detrimental to the subsequent mechanical polishing and wet etching processes.
Fig. 4d is a schematic cross-sectional view of the present embodiment after DSTI CMP process. As shown in fig. 4d, step S40 is performed to planarize the shallow trench structure by DSTI CMP.
In this step, first, a polishing liquid having a high selectivity between the filler layer 130 and the barrier layer 120 is selected, and in this embodiment, ceO is used 2 Abrasive, typically CeO 2 The abrasive has a smaller particle diameter and a uniform size than the conventional abrasive. And due to CeO 2 The silicon nitride has the capability of absorbing negative ions, and the silicon nitride also has the capability of absorbing negative ions, and negative ion polymers are added into the grinding liquid, and the negative ion polymers are like a layer of protective film and are respectively wrapped on CeO 2 The particles and the surface of the barrier layer have a greatly reduced contact opportunity due to the repulsive force of the anionic polymer, and CeO is not absorbed by the filler layer 130 2 The particles are able to interact with the surface of the filler layer 130 to produce corresponding physical and chemical reactions, so that a high selectivity to silicon dioxide/silicon nitride can be achieved. The CeO2 abrasive makes the polishing rate of the barrier layer 120 low, so that the polishing amount of the barrier layer 120 is small, and the polishing rate of the filler layer 130 is fast, so that the polishing amount of the polishing rate is large. Next, the semiconductor substrate 100 is polished.
As can be seen from the above, the DSTI CMP process of the present step can reduce the polishing thickness of the barrier layer 120 due to the high selectivity, thereby reducing the stress at the boundary between the active region and the STI, and the planarization effect of the DSTI CMP process is better than that of the conventional STI CMP (i.e., the planarization of the DSTI CMP process is higher than that of the conventional STI CMP), and the CMP dishing phenomenon (i.e., the dishing phenomenon occurs above the shallow trench, such that the surface is wavy) does not occur on the polishing surface in the DSTI CMP process, so that the depth of the STI recess is also smaller, thereby solving the problem of early turn-on of the MOSFET device due to the concentration of the tip electric field of the STI recess region, i.e., reducing the leakage current of the MOSFET device.
Optionally, after the DSTI CMP process, the filling layer 130 having a partial thickness of the STI is etched and removed by an etching process to reduce the surface height of the STI with respect to the surface of the semiconductor substrate. The etching process may be a dry etching process and/or a wet etching process. In this embodiment, for example, a wet etching process is used to etch the oxide layer in the STI, and the etching solution of the wet etching process is HF.
Step S50 is then performed to remove the barrier layer 120. In this embodiment, the barrier layer 120 is removed by a wet etching process. In this step, since the stress at the boundary of the active region and the STI is small, the STI recess effect is reduced, and the leakage current of the semiconductor device is reduced.
As shown in fig. 1, next, a gate structure, a source region, and a drain region are sequentially formed on the semiconductor substrate 100, thereby forming a semiconductor device. The gate structure includes, for example, a gate oxide layer and a gate polysilicon formed on the semiconductor substrate in sequence, and an active region (i.e., a source region and a drain region) is formed in the semiconductor substrate between adjacent shallow trench structures. The gate structure is located between and separates the source and drain regions. The grid structure, the source region and the drain region are arranged in parallel, the extending direction of the grid structure is the width direction of the active region, and the direction perpendicular to the extending direction of the grid structure is the long direction of the active region. The above process forms a MOSFET device with a more pronounced leakage current reduction when the width of the active region is smaller (the width of the active region is less than 1 μm).
As shown in fig. 4e, taking the low-voltage Nmos transistor as an example, the width of the active region of the low-voltage Nmos transistor is 0.14 μm, the length is 0.12 μm, the abscissa is the gate-source voltage Vgs, the ordinate is the drain current Id, the drain-source voltage Vds takes 1.65V, and when the bulk source voltage Vbs is 0V, -0.375V, -0.75V, -1.125V, -1.5V, the solid line in fig. 4e is the Vgs/Id curve of the Nmos transistor prepared by the existing technology, and the dotted line is the Vgs/Id curve of the Nmos transistor prepared by the technology according to the present scheme. As can be seen from the region b, when the value of the gate-source voltage Vgs is between 0.5V and-0.5V, the value of the leakage current Id of the Nmos transistor prepared by the process of the present invention is obviously smaller than that of the Nmos transistor prepared by the existing process, that is, the leakage current of the Nmos transistor prepared by the process of the present invention is smaller, and the device characteristics are better.
The embodiment also provides a semiconductor device which is prepared by the method.
In summary, in the semiconductor device and the forming method thereof provided by the present invention, the forming method of the semiconductor device includes the following steps: providing a semiconductor substrate; forming a barrier layer on the semiconductor substrate; forming a shallow trench structure; flattening the shallow trench structure through a DSTI CMP process; and removing the barrier layer. Compared with the STI CMP process in the prior art, the planarization effect of the DSTI CMP process is better, the CMP dishing phenomenon on the grinding surface does not occur in the DSTI CMP process, so that the depth of the STI recess is smaller, the problem that the MOSFET device is started earlier due to the concentration of the tip electric field of the STI recess region is solved, and the leakage current of the MOSFET device is reduced.
Further, the thickness of the barrier layer isSo that the thickness of the barrier layer is greater than +.>In the aspect of the invention, the thickness is thinned, the stress at the boundary between the active region and the STI is reduced, the risk of STI dent generated in the subsequent mechanical grinding process and wet etching process is reduced, and simultaneously, the occurrence of cracks on the surface of the barrier layer and the surface of the semiconductor substrate positioned below the barrier layer in the mechanical grinding process is avoided.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (5)
1. A method of forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate;
sequentially forming a first pad oxide layer and a barrier layer on the semiconductor substrate, wherein the thickness of the barrier layer is 700A-900A;
sequentially etching the barrier layer, the first underlying oxide layer and the semiconductor substrate, and stopping etching in the semiconductor substrate to form a shallow trench;
thermally treating the semiconductor substrate to form a second underlying oxide layer in the shallow trench;
forming a filling layer in the shallow trench to form a shallow trench structure, wherein the filling layer is also formed on the barrier layer at the same time;
selecting a grinding fluid with high selection ratio of the filling layer and the barrier layer, and flattening the shallow trench structure through a DSTI CMP process; and
and removing the barrier layer.
2. The method of forming a semiconductor device of claim 1, wherein the fill layer is formed in the shallow trench by a high density plasma oxide layer deposition process.
3. The method of forming a semiconductor device of claim 1, wherein a material of the fill layer comprises silicon dioxide and a material of the barrier layer comprises silicon nitride.
4. The method of claim 1, wherein the removing the filling layer of the shallow trench structure is performed by etching after the DSTI CMP process.
5. The method of forming a semiconductor device of claim 1, wherein a gate structure, a source region, and a drain region are sequentially formed on the semiconductor substrate, thereby forming a semiconductor device, wherein the source region and the drain region are located between adjacent ones of the shallow trench structures, and the gate structure is located between and separating the source region and the drain region.
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