CN110854060A - STI structure and manufacturing method thereof - Google Patents
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- CN110854060A CN110854060A CN201911133354.2A CN201911133354A CN110854060A CN 110854060 A CN110854060 A CN 110854060A CN 201911133354 A CN201911133354 A CN 201911133354A CN 110854060 A CN110854060 A CN 110854060A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 239000000126 substance Substances 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000000227 grinding Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000009969 flowable effect Effects 0.000 claims description 4
- 230000006872 improvement Effects 0.000 description 13
- 239000010408 film Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a manufacturing method of an STI structure, wherein: providing a semiconductor substrate, and sequentially forming a first etching barrier layer, a second etching barrier layer and a photomask layer on the semiconductor substrate from bottom to top; forming a photomask pattern; carrying out first etching to form a shallow trench in the semiconductor substrate; carrying out wet etching on the shallow trench to form a sigma type trench; etching the semiconductor substrate for the second time to form an inverted trapezoidal groove below the sigma-type groove, wherein the inverted trapezoidal groove and the sigma-type groove form a wing-type groove; depositing an insulating medium to fill the wing-type groove and the groove formed in the first etching barrier layer and formed on the first etching barrier layer; carrying out chemical mechanical grinding on the insulating medium until the first etching barrier layer is exposed; and removing the first etching barrier layer. The STI structure of the invention forms a double-wing structure on the shoulder part thereof, and shortens the distance between the STI structure and the channel, thereby obviously improving the stress of the STI on the channel and improving the performance of the device.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and particularly belongs to an SIT structure and a manufacturing method thereof.
Background
When the size of an integrated circuit is reduced to 90nm or below, in order to improve the performance of the device, a stress engineering technology is introduced in a large quantity, wherein the stress engineering technology comprises the steps of applying compressive stress to a device channel by using embedded germanium-silicon or silicon-germanium epitaxially grown on silicon, and increasing the hole mobility to improve the performance of a PMOS device; or silicon carbide is epitaxially grown on the silicon or tensile stress is applied to a device channel by utilizing a stress memory technology, and the electron mobility is increased to improve the performance of the NMOS device.
Taking a typical 28nm logic PMOS as an example, as shown in fig. 2A to 2F, the typical 28nm logic PMOS is a device structure diagram of a key process for manufacturing an existing STI structure, and a manufacturing process of the existing STI structure is specific, as shown in fig. 1, and includes the following steps:
as shown in fig. 2A, a semiconductor substrate 100 is provided, and a thin film stack structure is formed on the semiconductor substrate 100.
The thin film stack structure sequentially comprises a first etching barrier layer and a second etching barrier layer from bottom to top, and a photomask layer is formed on the second etching barrier layer.
The first etching barrier layer sequentially comprises a pad oxide layer 101 and a silicon nitride layer 102 from bottom to top. The second etching barrier layer sequentially comprises an advanced patterning film layer 103 and a nitrogen-free oxide layer 104 from bottom to top, and the advanced patterning film layer 103 has the characteristics of high etching selectivity, high transparency and high conformality. The photomask layer includes, from Bottom to top, a Bottom Anti Reflective Coating (BARC) 105 and a Photoresist (PR) 106.
As shown in fig. 2B, exposure and development are performed to form a photomask pattern.
As shown in fig. 2C, the bottom anti-reflective layer 105, the nitrogen-free oxide layer 104 and the advanced patterning film layer 103 in the second etching barrier layer, the silicon nitride layer 102 and the pad oxide layer 101 in the first etching barrier layer, and the semiconductor substrate 100 are etched, and the photoresist 106 and the bottom anti-reflective layer 105 in the photomask layer, and the nitrogen-free oxide layer 104 and the advanced patterning film layer 103 in the second etching barrier layer are removed, so that an inverted trapezoidal deep trench is formed in the semiconductor substrate 100.
As shown in fig. 2D, the deep trench of the inverted trapezoid is filled with an insulating dielectric 107.
As shown in fig. 2E, the insulating dielectric 107 is subjected to Chemical Mechanical Polishing (CMP) to expose the first etch stop layer.
As shown in fig. 2F, the silicon nitride layer 102 and the pad oxide layer 101 of the first etch stop layer are removed.
Referring to the document m.miyamoto, h.ohta, et al, "Impact of Reducing STI-induced stress on Layout Dependence of MOSFET Characteristics", IEEE Transactions on electron Devices, vol.51, No.3, pp.440-443,2004, PMOS device performance can be improved by shortening the distance La from the edge of Shallow Trench Isolation (STI) to the polysilicon gate, as shown in fig. 3, as shown in fig. 4.
However, due to the design rule and layout, as shown in FIG. 5 and FIG. 6, the distance La between the active area AA and the gate can not be reduced at will, and La is 0.075 μm or more for the 28LP core device and 0.155 μm or more for the 28LP I/O device.
Although the above documents disclose that the closer the edge of the shallow trench isolation is to the polysilicon gate, the higher the compressive stress, and the better the PMOS performance, even so, it is very important to improve the inverted trapezoidal structure (as shown in fig. 7) of the existing shallow trench isolation from the appearance of the shallow trench isolation, so that the shallow trench isolation is closer to the trench, and the stress of the shallow trench isolation to the trench is increased.
Disclosure of Invention
The invention aims to provide an STI structure and a manufacturing method thereof, which can shorten the distance between the STI structure and a channel and improve the performance of a device.
In order to solve the above technical problem, the STI structure provided in the present invention is composed of a wing trench and an insulating medium, wherein the wing trench is formed in a semiconductor substrate, the wing trench includes an upper sigma-type trench and a lower inverted trapezoidal trench, the insulating medium fills the inverted trapezoidal trench and the sigma-type trench, and a top surface of the insulating medium is higher than the semiconductor substrate.
In a further improvement, the top opening of the sigma-type trench is flush with the top surface of the semiconductor substrate.
In a further improvement, the wing grooves have a depth of
In a further improvement, the insulating dielectric is silicon dioxide.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In order to solve the above technical problem, the present invention further provides a method for manufacturing the STI structure, wherein the method comprises the following steps:
step S1, providing a semiconductor substrate, and sequentially forming a first etching barrier layer, a second etching barrier layer and a photomask layer on the semiconductor substrate from bottom to top;
step S2, forming a photomask pattern;
step S3, carrying out first etching on the second etching barrier layer, the first etching barrier layer and the semiconductor substrate, forming a shallow trench in the semiconductor substrate, and removing the second etching barrier layer;
step S4, performing wet etching on the shallow trench to form a sigma-type trench;
step S5, carrying out secondary etching on the semiconductor substrate, and etching below the sigma-type groove to form an inverted trapezoidal groove, wherein the inverted trapezoidal groove and the sigma-type groove form a wing-type groove;
step S6, depositing an insulating medium, wherein the wing-type groove and the groove formed on the first etching barrier layer are filled with the insulating medium and formed on the first etching barrier layer;
step S7, carrying out chemical mechanical grinding on the insulating medium until the first etching barrier layer is exposed;
step S8, removing the first etching stop layer.
In a further improvement, in step S3, the shallow trench is U-shaped or bowl-shaped.
In a further improvement, the depth of the shallow trench is
In a further improvement, in step S4, the wet etching is performed using a tetramethylammonium hydroxide solution.
In a further improvement, in step S5, the wing grooves have a depth of
In a further improvement, in step S5, a second etching is performed by using the first etching stop layer as a mask.
In a further improvement, in step S6, the insulating medium is deposited by a high density plasma chemical vapor deposition process or a high aspect ratio chemical vapor deposition process or a flowable chemical vapor deposition process.
In a further improvement, the thickness of the insulating medium is
In a further improvement, the insulating dielectric is silicon dioxide.
In step S1, the first etching stop layer includes, in order from bottom to top, a pad oxide layer and a silicon nitride layer; the second etching barrier layer sequentially comprises an advanced pattern film layer and a nitrogen-free oxide layer from bottom to top; the photomask layer sequentially comprises a bottom antireflection layer and photoresist from bottom to top.
In a further improvement, the thickness of the pad oxide layer isThe thickness of the silicon nitride layer is
In a further improvement, in step S7, the chemical mechanical polishing stops the silicon nitride layer in the first etch stop layer.
Compared with the conventional STI structure and manufacturing process, the shallow trench is formed in a semiconductor substrate firstly, then the shallow trench is subjected to wet etching to form a sigma-type trench, finally an inverted trapezoidal trench is formed below the sigma-type trench, the wing-type trench is formed by the method, and the finally manufactured STI structure forms a double-wing structure at the shoulder (namely below the top surface of the semiconductor substrate) of the STI structure by combining subsequent deposition of an insulating medium, chemical mechanical grinding and removal of an etching barrier layer.
Drawings
FIG. 1 is a flow chart of a method for fabricating a conventional STI structure;
FIGS. 2A-2F are schematic cross-sectional views of a device for various processes of fabricating a conventional STI structure for a 28nm process;
FIG. 3 is a schematic structural view of a prior art document;
FIG. 4 is a graph comparing the performance of the prior art documents;
FIG. 5 is a schematic diagram of a PMOS employing 40 LP;
FIG. 6 is a schematic diagram of an SRAM fabricated with 28nm PMOS;
FIG. 7 is a diagram of a conventional STI structure;
FIGS. 8A-8H are schematic device cross-sectional views of various fabrication processes of the STI structure of the present invention for a 28nm process;
FIG. 9 is a flow chart of a method for fabricating an STI structure of the present invention.
Wherein the reference numerals are as follows:
100 is a semiconductor substrate; 101 is a pad oxide layer; 102 is a silicon nitride layer; 103 is an advanced patterning film layer; 104 is a nitrogen-free oxide layer; 105 is a bottom anti-reflection layer; 106 is photoresist; 107 is an insulating medium; 108 is a shallow trench; 109 is a sigma type groove; 110 are wing grooves.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown in the accompanying drawings, wherein the specific embodiments are by way of illustration. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.
In an embodiment of the present invention, the STI structure is composed of a wing trench 110 and an insulating dielectric 107, as shown in fig. 8H.
The wing trenches 110 are formed in the semiconductor substrate 100, and the wing trenches 110 include upper sigma-type trenches 109 and lower inverted trapezoidal trenches. The insulating medium 107 fills the inverted trapezoidal trench and the sigma-type trench 109, and the top surface of the insulating medium 107 is higher than the semiconductor substrate 100.
As shown in fig. 8H, the top opening of the sigma-type trench 109 is flush with the top surface of the semiconductor substrate 100, so that a two-wing structure is formed on top of the STI under silicon.
The wing-type groove 110 is formed by further etching an inverted trapezoidal groove on the basis of the sigma-type groove 109, the upper part of the whole wing-type groove 110 is in a sigma shape, the lower part of the whole wing-type groove is in an inverted trapezoidal shape, and the depth of the whole wing-type groove 110 is
The material of the insulating dielectric 107 includes, but is not limited to, silicon dioxide.
The semiconductor substrate includes a silicon substrate.
The STI structure forms a double-wing structure at the shoulder (i.e., under the top surface of the semiconductor substrate 100), so that the distance between the STI structure and the channel is shortened, the stress of the STI on the channel is significantly improved, and the performance of the device is improved.
Taking a 28nm process as an example, the device cross-sectional views of the STI structures of the embodiments of the present invention are shown in fig. 8A to 8H.
In the method for manufacturing the STI structure according to the embodiment of the present invention, as shown in fig. 9, the forming steps include:
step S1, providing a semiconductor substrate 100, and sequentially forming a first etching stop layer, a second etching stop layer and a photomask layer on the semiconductor substrate 100 from bottom to top, as shown in fig. 8A.
The first etching barrier layer sequentially comprises a pad oxide layer 101 and a silicon nitride layer 102 from bottom to top. The second etching barrier layer sequentially comprises an advanced patterning film layer 103 and a nitrogen-free oxide layer 104 from bottom to top; advanced patterning film layer 103 has the characteristics of high etch selectivity, high transparency, and high conformality. The photomask layer sequentially comprises a bottom antireflection layer 105 and photoresist 106 from bottom to top.
Preferably, the thickness of the pad oxide layer 101 is
The thickness of the silicon nitride layer 102 is
Step S2, forming a photomask pattern on the first etching stop layer, as shown in fig. 8B.
Specifically, a photomask pattern is formed on the photoresist 106 of the photomask layer by exposure and development.
Step S3, performing a first etching on the second etching stop layer, the first etching stop layer and the semiconductor substrate 100, forming a shallow trench 108 in the semiconductor substrate 100, and removing the second etching stop layer, as shown in fig. 8C.
Specifically, the shape of the shallow trench 108 may be U-shaped or curved bowl-shaped (bending-shape), and the depth of the shallow trench 108 is
Step S4, performing wet etching on the shallow trench 108 to form a sigma-type trench 109, as shown in fig. 8D.
Specifically, two wings are formed by etching outwards at the side of the shallow trench 108, and finally, a sigma-type trench 109 is formed in the semiconductor substrate 100.
In step S4, the chemical solution used in the wet etching includes, but is not limited to, a known tetramethylammonium hydroxide solution (TMAH).
Step S5, performing a second etching on the semiconductor substrate 100, and etching to form an inverted trapezoidal trench below the sigma-type trench 109, where the inverted trapezoidal trench and the sigma-type trench 109 form a wing-type trench 110, as shown in fig. 8E.
Specifically, the first etching barrier layer is used as a mask to perform second etching, so that the rest positions of the device are not etched.
The wing-shaped groove 110 is formed by further etching on the basis of the sigma-type groove 109 described in the third step, so that the whole wing-shaped groove 110 is in a sigma shape at the upper part and in an inverted trapezoid shape at the lower part, and the total depth is
Step S6, depositing an insulating dielectric 107, wherein the insulating dielectric 107 fills the wing trench 110 and the trench formed on the first etch stop layer and is formed on the first etch stop layer, as shown in fig. 8F.
In step S6, the insulating medium 107 may be deposited by a high density plasma chemical vapor deposition process HDP-CVD, a high aspect ratio chemical vapor deposition process HARP-CVD, or a Flowable chemical vapor deposition process Flowable CVD.
The material of the insulating dielectric 107 includes, but is not limited to, silicon dioxide, and the total thickness of the insulating dielectric 107 after deposition and before chemical mechanical polishing is much greater than the total depth of the fin trench 110 to facilitate chemical mechanical polishing, preferably, the total thickness of the insulating dielectric 107 is
Step S7, performing chemical mechanical polishing on the insulating medium 107 until the first etching stop layer is exposed, as shown in fig. 8G.
Specifically, the chemical mechanical polishing stops on the silicon nitride layer 102 in the first etch stop layer.
In step S8, the silicon nitride layer 102 and the pad oxide layer 101 of the first etch stop layer are removed, as shown in fig. 8H, and finally an STI structure is formed.
According to the invention, a shallow trench 108 is formed in a semiconductor substrate, then the shallow trench 108 is subjected to wet etching to form a sigma-type trench 109, finally an inverted trapezoidal trench is etched below the sigma-type trench 109, a wing-type trench 110 is formed by the method, and a double-wing structure is formed on a shoulder part (namely below the top surface of the semiconductor substrate) of the STI structure finally manufactured by combining subsequent deposition of an insulating medium, chemical mechanical polishing and removal of an etching barrier layer.
Compared with the existing STI structure and manufacturing process, the distance between the stretched STI structure and the channel is closer than that between the traditional inverted trapezoid STI structure and the channel, so that the stress of the STI to the channel is obviously improved, and the performance of the device is improved.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.
Claims (17)
1. An STI structure, wherein the STI structure is composed of a wing trench and an insulating medium, the wing trench is formed in a semiconductor substrate and comprises an upper sigma-type trench and a lower inverted trapezoidal trench, the insulating medium fills the inverted trapezoidal trench and the sigma-type trench, and the top surface of the insulating medium is higher than the semiconductor substrate.
2. The STI structure of claim 1, wherein a top opening of the sigma-type trench is flush with a top surface of the semiconductor substrate.
3. The STI structure of claim 1, wherein the fin trench has a depth of
4. The STI structure of claim 1, wherein the insulating dielectric is silicon dioxide.
5. The STI structure of claim 1, wherein the semiconductor substrate comprises a silicon substrate.
6. A method for fabricating an STI structure, wherein the STI structure is composed of a wing trench and an insulating medium, the wing trench is formed in a semiconductor substrate, the wing trench includes an upper sigma-type trench and a lower inverted trapezoidal trench, the insulating medium fills the inverted trapezoidal trench and the sigma-type trench, and a top surface of the insulating medium is higher than the semiconductor substrate, the STI structure is formed by:
step S1, providing a semiconductor substrate, and sequentially forming a first etching barrier layer, a second etching barrier layer and a photomask layer on the semiconductor substrate from bottom to top;
step S2, forming a photomask pattern;
step S3, carrying out first etching on the second etching barrier layer, the first etching barrier layer and the semiconductor substrate, forming a shallow trench in the semiconductor substrate, and removing the second etching barrier layer;
step S4, performing wet etching on the shallow trench to form a sigma-type trench;
step S5, carrying out secondary etching on the semiconductor substrate, and etching below the sigma-type groove to form an inverted trapezoidal groove, wherein the inverted trapezoidal groove and the sigma-type groove form a wing-type groove;
step S6, depositing an insulating medium, wherein the wing-type groove and the groove formed on the first etching barrier layer are filled with the insulating medium and formed on the first etching barrier layer;
step S7, carrying out chemical mechanical grinding on the insulating medium until the first etching barrier layer is exposed;
step S8, removing the first etching stop layer.
7. The method of claim 6, wherein in step S3, the shallow trench is U-shaped or bowl-shaped.
8. The method of claim 7, wherein the shallow trench has a depth of
9. The method of claim 6, wherein in step S4, the wet etching is performed by using a tetramethylammonium hydroxide solution.
10. The STI structure fabrication method of claim 6, wherein in step S5, the fin trench has a depth of
11. The method of claim 6, wherein in step S5, the second etching is performed by using the first etching stop layer as a mask.
12. The method of claim 6, wherein in step S6, the insulating medium is deposited by a high density plasma chemical vapor deposition process or a high aspect ratio chemical vapor deposition process or a flowable chemical vapor deposition process.
13. According to claim12 the method of fabricating an STI structure, wherein the insulating dielectric has a thickness of
14. The method of claim 6, wherein the insulating dielectric is silicon dioxide.
15. The method of manufacturing an STI structure of claim 6, wherein in step S1, the first etch stop layer includes a pad oxide layer and a silicon nitride layer in sequence from bottom to top; the second etching barrier layer sequentially comprises an advanced pattern film layer and a nitrogen-free oxide layer from bottom to top; the photomask layer sequentially comprises a bottom antireflection layer and photoresist from bottom to top.
16. The method of claim 15, wherein the pad oxide layer has a thickness of
The thickness of the silicon nitride layer is
17. The method of claim 15, wherein in step S7, the chemical mechanical polishing stops on the silicon nitride layer in the first etching stop layer.
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| CN112909079A (en) * | 2021-03-09 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
| CN112909079B (en) * | 2021-03-09 | 2024-02-09 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
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