CN107968046B - Method for manufacturing semiconductor device - Google Patents
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- CN107968046B CN107968046B CN201610915624.5A CN201610915624A CN107968046B CN 107968046 B CN107968046 B CN 107968046B CN 201610915624 A CN201610915624 A CN 201610915624A CN 107968046 B CN107968046 B CN 107968046B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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Abstract
The invention provides a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming a barrier layer on the surface of the semiconductor substrate; forming a photoresist pattern of an inverted trapezoid on the barrier layer; isotropically etching the photoresist pattern to make sidewalls of the photoresist pattern perpendicular to a surface of the semiconductor substrate; performing anisotropic etching to etch away the barrier layer outside the sidewalls of the photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; and removing the photoresist pattern and the barrier layer. According to the manufacturing method, the outline of the target pattern is optimized, the uniformity of the Critical Dimension (CD) of the target pattern is improved, the cost is low, the online control is easy, and the yield and the performance of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
With the increasing demand for high-capacity semiconductor memory devices, the integration density of semiconductor memory devices is receiving attention, and in order to increase the integration density of semiconductor memory devices, many different methods are used in the prior art, and Double-Patterning (DP) is widely accepted and applied as a solution in the process of manufacturing semiconductor devices with nodes less than 32 nm.
Double-Patterning (DP) overcomes the K1 limitation by pitch fragmentation, and is widely used in the fabrication of semiconductor devices. Currently, Self-aligned Double Patterning (SADP), photo-Etch-photo-Etch (LELE), and Freeze-coat-Etch (LFL) are available in Double-Patterning (DP) technology.
Which technology is selected in the device preparation process needs to be selected by comprehensively considering the flexibility, applicability and cost of each technology. Wherein the ability of Self-aligned double patterning (SADP) to achieve minimum pitch etching is beyond expectations for this approach.
In the SADP process, a positive photoresist is usually selected and patterned as a core (core) in a double pattern, and then an ultra-low temperature deposition method is selected to form a spacer layer on the photoresist core, so that the spacer layer generates a certain stress on the photoresist core in the deposition process, which causes the performance of the sidewall of the photoresist core to be reduced, even generates serious deformation and inclination, thereby causing an influence on the transfer of the pattern, seriously distorting the profile of the transferred pattern, and finally affecting the performance and yield of the device.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, and forming a barrier layer on the surface of the semiconductor substrate;
forming a photoresist pattern of an inverted trapezoid on the barrier layer;
isotropically etching the photoresist pattern to make sidewalls of the photoresist pattern perpendicular to a surface of the semiconductor substrate;
performing anisotropic etching to etch away the barrier layer outside the sidewalls of the photoresist pattern;
forming a spacer on a sidewall of the photoresist pattern;
and removing the photoresist pattern and the barrier layer.
Further, the method of forming the photoresist pattern of the inverted trapezoid includes:
spin-coating a negative photoresist on the semiconductor substrate;
exposing the negative photoresist by using a bright field photomask;
and developing and removing the unexposed negative photoresist to form the photoresist pattern with the inverted trapezoid shape.
Further, the developing solution used for the development includes n-butyl acetate.
Further, the barrier layer is a low temperature oxide layer.
Further, the method of forming the low temperature oxide layer includes: the plasma enhanced chemical vapor deposition is carried out at a temperature below 200 ℃.
Further, the isotropic etching is performed using plasma etching.
Further, the plasma etching uses an etching gas including HBr and He, or uses an etching gas including oxygen.
Further, the anisotropic etching is performed using a plasma etching, an etching gas of the plasma etching including a fluorocarbon.
Further, after the step of removing the photoresist pattern and the barrier layer, the method further includes the steps of:
and etching the semiconductor substrate by using the gap wall as a mask, and transferring a pattern into the semiconductor substrate.
Further, the step of forming a spacer on the sidewall of the photoresist pattern includes the processes of:
conformally depositing a spacer material layer to cover the photoresist pattern, the barrier layer and part of the exposed surface of the semiconductor substrate;
and etching back to remove the spacer material layer on the top surface of the photoresist pattern and on part of the surface of the semiconductor substrate so as to form the spacer.
According to the manufacturing method, the negative developing photoetching technology is used for forming the inverted trapezoidal photoresist pattern, then isotropic etching and anisotropic etching are utilized for trimming the inverted trapezoidal photoresist pattern, so that the side wall of the photoresist pattern is perpendicular to the surface of the semiconductor substrate, and further the gap wall formed on the side wall of the photoresist pattern is perpendicular to the surface of the semiconductor substrate, the pattern of the gap wall is favorably transferred into the semiconductor substrate, the outline of a target pattern is optimized, the uniformity of the Critical Dimension (CD) of the target pattern is improved, the cost is low, online control is easy, and the yield and the performance of a device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1G are schematic structural diagrams of a semiconductor device obtained in accordance with one embodiment of the present invention;
FIGS. 2A-2F are schematic structural diagrams of a device obtained in the steps related to the fabrication of a semiconductor device based on a dual patterning technique according to another embodiment of the prior art;
fig. 3 is a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;
FIGS. 4A-4F are schematic structural views of a device obtained in accordance with steps associated with the fabrication of a semiconductor device based on a dual patterning technique according to the present invention;
fig. 5A-5C are partial schematic views of a device obtained by a process of trimming an inverted trapezoidal photoresist pattern according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
There are two methods for manufacturing a semiconductor device by SADP in the prior art, the first method is, as shown in fig. 1A to 1G, firstly, as shown in fig. 1A, providing a semiconductor substrate 100, sequentially forming an Advanced Patterning Film (APF) material 101 and a bottom anti-reflection layer (BARC)102 on the semiconductor substrate 100, and forming a patterned photoresist layer 103 on the bottom anti-reflection layer 102.
As shown in fig. 1B, the bottom anti-reflective layer 102 is patterned to transfer a pattern into the bottom anti-reflective layer.
As shown in fig. 1C, the advanced patterning film material 101 is etched using the bottom anti-reflection layer 102 as a mask to transfer a pattern into the advanced patterning film material 101;
as shown in fig. 1D to 1G, a spacer material layer 104a is then deposited to cover the advanced patterning film material 101, the spacer material layer 104a is etched to form a spacer 104, and the semiconductor substrate 100 is etched using the spacer 104 as a mask to obtain a target pattern. In the method, a CVD method is needed to deposit the spacer material layer, the hard mask layer needs to be etched in the patterning process, the etching condition of the hard mask layer is very harsh, and the method is not only complicated, but also has high cost.
A second method may be selected to reduce the cost, as shown in fig. 2A to 2F, first, as shown in fig. 2A, directly forming a photoresist pattern 201 on the substrate 200, where the photoresist pattern 201 is usually a positive photoresist, and the shape of the photoresist pattern 201 after exposure and development tends to be a regular trapezoid after a photolithography process, and then, as shown in fig. 2B, performing etching trimming (trimming) on the photoresist pattern 201 to trim the shape of the photoresist pattern 201, however, the trimming in this step has a limited effect, and the sidewall of the photoresist pattern 201 is still hard to be perpendicular to the surface of the semiconductor substrate after trimming, and then as shown in fig. 2C, depositing a spacer material layer 202A on the photoresist pattern, but due to the insufficient hardness of the photoresist, the spacer material layer is not enough to bear the pressure of the spacer material layer and the pressure during etching, the photoresist pattern 201 is also easily deformed, with the deformed photoresist pattern as the photoresist core, the formed spacer 202 is also deformed, and when the dual patterning technique is performed, the formed target pattern is severely deformed as shown in fig. 2D to 2F, thereby affecting the yield and performance of the device. In addition, there is another method of improving the hardness of the resist pattern by a method of hardening the resist pattern by plasma containing hydrogen, and the like, thereby improving the profile of the pattern, but the effect of this method is also limited.
Therefore, although the prior art has the double-pattern technology, the problems of complicated process and high cost exist, and if the cost is reduced, the quality of the product cannot be guaranteed, so that the device is seriously deformed, and the product yield is reduced, so that the method needs to be improved to eliminate the existing problems.
Example one
In order to solve the foregoing technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, which mainly includes the following steps:
step S301, providing a semiconductor substrate, and forming a barrier layer on the surface of the semiconductor substrate;
step S302, forming an inverted trapezoidal photoresist pattern on the barrier layer;
step S303, performing isotropic etching on the photoresist pattern to make a sidewall of the photoresist pattern perpendicular to a surface of the semiconductor substrate;
step S304, carrying out anisotropic etching to etch and remove the barrier layer on the outer side of the side wall of the photoresist pattern;
step S305, forming a spacer on the sidewall of the photoresist pattern;
step S306, removing the photoresist pattern and the barrier layer.
According to the manufacturing method, the negative development technology is used for forming the inverted trapezoidal photoresist pattern, then isotropic etching and anisotropic etching are utilized for trimming the inverted trapezoidal photoresist pattern, so that the side wall of the photoresist pattern is perpendicular to the surface of the semiconductor substrate, and further the gap wall formed on the side wall of the photoresist pattern is perpendicular to the surface of the semiconductor substrate, the pattern of the gap wall is favorably transferred into the semiconductor substrate, the outline of a target pattern is optimized, the uniformity of the Critical Dimension (CD) of the target pattern is improved, the cost is low, online control is easy, and the yield and the performance of a device are improved.
A method of fabricating a semiconductor device according to the present invention is described in detail with reference to fig. 4A-4F and fig. 5A-5C, wherein fig. 4A-4F are schematic structural views of the device obtained in accordance with the steps associated with fabricating a semiconductor device based on a dual patterning technique according to the present invention; fig. 5A-5C are partial schematic views of a device obtained by a process of trimming an inverted trapezoidal photoresist pattern according to an embodiment of the present invention.
First, as shown in fig. 4A, a semiconductor substrate 400 is provided, a barrier layer 401 is formed on a surface of the semiconductor substrate 400, and then, a photoresist pattern 402 of an inverted trapezoid is formed on the barrier layer.
Specifically, as shown in fig. 4A, the semiconductor substrate 400 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Optionally, an isolation structure may also be formed in the semiconductor substrate, where the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. In the invention, shallow trench isolation is formed, and various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate.
Generally, the ion doping conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration of the well (well) structure is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the well (well) structure is required to be larger than that of the isolation structure.
In addition, an active region may be defined on the semiconductor substrate. Other active devices may also be included on the active region and are not shown in the figures for convenience.
The semiconductor substrate 400 may further include a target material layer, which may be an interconnect wiring layer, an interlayer dielectric layer, a gate material layer, or a hard mask layer formed on the substrate. The constituent material of the interconnect wiring layer is at least one selected from tungsten, tungsten silicide, aluminum, titanium, and titanium nitride. The constituent material of the interlayer dielectric layer may be selected from a low dielectric constant (k) material or an ultra-low k material. The gate material layer is made of one material selected from polysilicon and aluminum. The hard mask layer is made of at least one material selected from the group consisting of an oxide, undoped silicon glass, silicon on glass, SiON, SiN, SiBN, BN, and a high-k material. It should be noted that the target material layer is optional, not necessary, and may be selected according to actual situations.
A barrier layer 401 is formed on the surface of the semiconductor substrate 400, and when a target material layer is formed on the surface of the semiconductor substrate 400, the barrier layer 401 is formed on the target material layer, and the material of the barrier layer 401 may include nitride, oxide, oxynitride, and especially silicon nitride, silicon oxide, silicon oxynitride, or the like.
In this embodiment, the blocking layer 401 may be a Low Temperature Oxide (LTO) layer, which includes silicon dioxide, and the LTO layer is formed by a silicon dioxide precursor (e.g., a silicon source such as silane gas or tetraethyl orthosilicate, and an oxygen source such as molecular oxygen and ozone) through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method at a temperature not higher than 200 ℃. In various embodiments, the low temperature oxide may be formed by a PECVD method at a temperature of 120-200 ℃ and may have a thickness of 50-1000 angstroms.
The above deposition temperature ranges are exemplary only, and other suitable temperatures are also applicable to the present invention.
An inverse trapezoidal photoresist pattern 402 is formed on the barrier layer 401, wherein the inverse trapezoidal photoresist pattern 402 may be formed using any suitable method, for example, using a Negative Tone Definition (NTD) photolithography process. The inverted trapezoid is a shape of a cross section obtained by cutting the photoresist pattern 402 with a plane perpendicular to the surface of the semiconductor substrate.
In one example, the step of forming the photoresist pattern 402 of an inverted trapezoid includes the following processes:
first, a negative photoresist is spin coated on the semiconductor substrate, and the negative photoresist may be any suitable negative photoresist commonly used in the art, for example, the negative photoresist may include a photosensitive material such as polyvinyl alcohol laurate.
Next, the negative photoresist is exposed using a bright field Mask (Mask) including a light-transmitting region and a light-opaque region, wherein the light-transmitting region corresponds to a shape or the like of a predetermined photoresist pattern 402. A part of light beams are transmitted by a bright field photomask (Mask) and irradiate the negative photoresist to react with the negative photoresist, and under the action of light, double bonds in photosensitive material molecules in the negative photoresist are opened, and cross-linking is carried out between chains to form an insoluble net-shaped structure, so that a primary graph is defined, wherein the light beams can be ultraviolet light or electron beams and the like.
Next, the unexposed negative photoresist is developed and removed to form the inverse trapezoidal photoresist pattern 402.
And developing the exposed negative photoresist, spraying a developing solution on the surface of the semiconductor substrate, and developing and removing the unexposed negative photoresist to form a final inverted trapezoidal photoresist pattern 402. Xylene or n-butyl acetate (nBA) may be used as the developer, or other suitable developers may be used to develop and remove the unexposed negative photoresist.
Next, as shown in fig. 4B, the photoresist pattern 402 is isotropically etched (isotropicetching) to make the sidewalls of the photoresist pattern 402 perpendicular to the surface of the semiconductor substrate 400, and then anisotropically etched (anistropic etching) to etch away the barrier layer 401 outside the sidewalls of the photoresist pattern 402.
Specifically, as shown in fig. 5A, the photoresist pattern 402 with an inverted trapezoid shape is first trimmed (Trimming) by one-step isotropic etching to make the sidewall of the photoresist pattern 402 perpendicular to the surface of the semiconductor substrate 400, so as to ensure that the spacer formed on the sidewall of the photoresist pattern 402 is also perpendicular to the surface of the semiconductor substrate 400.
Wherein, the isotropic etching in this step can be implemented using a dry etching method, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser cutting, or the like.
In this embodiment, the isotropic etching is performed using plasma etching using an etching gas including HBr and He, or an etching gas including oxygen.
The etch has a high etch rate for the photoresist pattern 402 and a low etch rate for the barrier layer 401 thereunder, i.e., the etch has a high etch selectivity of the photoresist pattern 402 to the barrier layer 401.
Isotropic etching for the photoresist pattern 402, the photoresist pattern 402 is etched in both X, Y and Z directions.
Thereafter, as shown in fig. 5B and 5C, anisotropic etching is performed to etch away the barrier layer 401 outside the sidewalls of the photoresist pattern 402.
The anisotropic etching may be performed using any suitable etching method, such as wet etching using a method having a high etching rate for the barrier layer 401 or dry etching.
Preferably, the anisotropic etching is performed using a dry etching method including, but not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser cutting, or the like.
Illustratively, plasma etching is usedThe anisotropic etching is performed with an etching gas comprising fluorocarbon, for example, the etching gas for dry etching may comprise CF4、CHF3Or other fluorocarbon (CxFy) gases.
As an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: the etching gas contains CF4、CHF3The flow rates of the gases are respectively 50 sccm-500 sccm and 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.
After the anisotropic etching, the remaining photoresist pattern 402 and the underlying barrier layer 401 collectively function as a Core (Core) pattern.
And the anisotropic etching has a high etching rate to the barrier layer 401 and a low etching rate to the photoresist pattern 402, and the anisotropic etching etches away the barrier layer 401 in a direction (Z direction) perpendicular to the surface of the semiconductor substrate 400 and also possibly etches away a part of the thickness of the photoresist pattern 402 at the same time.
Next, as shown in fig. 4C, a spacer material layer 403a is conformally deposited to cover the photoresist pattern 402, the barrier layer 401 and a portion of the exposed surface of the semiconductor substrate 400.
The spacer material layer 403a may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
The spacer material layer 403a may be formed using a method including, but not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, for example, a low temperature chemical vapor deposition method may be used.
Next, as shown in fig. 4D, an etch back removes the spacer material layer on the top surface of the photoresist pattern 402 and on a portion of the surface of the semiconductor substrate 400 to form spacers 403 on the sidewalls of the photoresist pattern 402 and the barrier layer 401.
The etch back may use a dry etching method, including but not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps.
After the etch back process, the spacer material layer on the top surface of the photoresist pattern 402 and a portion of the spacer material layer on the surface of the semiconductor substrate are etched away, and only the spacer material layer on the sidewalls of the photoresist pattern 402 and the barrier layer 401 is exposed to form a spacer 403, and the spacer 403 is used as a mask for the subsequent etching, so that the pattern of the spacer 403 is transferred into the semiconductor substrate 400 below the spacer 403.
Next, as shown in fig. 4E, the photoresist pattern 402 and the blocking layer 401 are removed, and the spacers 403 are left as a mask.
The photoresist pattern 402 and the barrier layer 401 may be removed using any commonly used etching method, including but not limited to wet etching or dry etching, including but not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The dry etching may be selected from CF4、CHF3In addition, N is added2、CO2、O2As an etching atmosphere, wherein the gas flow rate is CF410-200sccm，CHF310-200sccm，N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, and the etching time is 5-120 s.
Finally, as shown in fig. 4F, the semiconductor substrate 400 is etched using the spacers 403 as a mask, and a pattern is transferred into the semiconductor substrate 400.
When a target material layer is formed on the surface of the semiconductor substrate 400, the target material layer may be etched by using the spacers 403 as a mask to transfer a pattern into the target material layer, or the semiconductor substrate 400 may be etched by using the spacers 403 as a mask to transfer a pattern into the semiconductor substrate 400 to form a target pattern, such as a fin structure.
Suitable etching methods may be used depending on the nature of the material actually required to be etched, including but not limited to wet etching or dry etching, preferably dry etching is used. Since the spacers 403 are formed perpendicular to the surface of the semiconductor substrate 400, the pattern can be transferred into the semiconductor substrate well during the etching process in this step, and the transferred pattern is guaranteed to have a good profile.
Finally, the spacers 403 are removed. Illustratively, diluted hydrofluoric acid DHF (containing HF, H) is used in the step2O2And H2O) wet stripping the spacer. The concentration of DHF is not critical, but preferred is HF: H in the present invention2O2:H2O＝0.1-1.5:1:5。
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. In addition to the above steps, the manufacturing method of this embodiment may further include other steps in the above steps or between different steps, and these steps may be implemented by various processes in the current process, and are not described herein again.
In summary, according to the manufacturing method of the present invention, a negative tone development lithography technology is used to form an inverted trapezoidal photoresist pattern, and then isotropic etching and anisotropic etching are used to trim the inverted trapezoidal photoresist pattern so as to make the sidewall of the photoresist pattern perpendicular to the surface of the semiconductor substrate, thereby ensuring that the spacer formed on the sidewall of the photoresist pattern is perpendicular to the surface of the semiconductor substrate, which is beneficial to transferring the pattern of the spacer into the semiconductor substrate well, optimizing the profile of the target pattern, improving the uniformity of the Critical Dimension (CD) of the target pattern, and the method has low cost and easy online control, thereby improving the yield and performance of the device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a barrier layer on the surface of the semiconductor substrate;
forming an inverted trapezoidal negative photoresist pattern on the barrier layer;
isotropically etching the photoresist pattern to make sidewalls of the photoresist pattern perpendicular to a surface of the semiconductor substrate;
performing anisotropic etching to etch away the barrier layer outside the sidewalls of the photoresist pattern;
forming a spacer on a sidewall of the photoresist pattern;
and removing the photoresist pattern and the barrier layer.
2. The manufacturing method of claim 1, wherein the method of forming the photoresist pattern of the inverted trapezoid comprises:
spin-coating a negative photoresist on the semiconductor substrate;
exposing the negative photoresist by using a bright field photomask;
and developing and removing the unexposed negative photoresist to form the photoresist pattern with the inverted trapezoid shape.
3. The method of claim 2, wherein the developing solution used for the development comprises n-butyl acetate.
4. The method of manufacturing of claim 1, wherein the barrier layer is a low temperature oxide layer.
5. The manufacturing method according to claim 4, wherein the method of forming the low-temperature oxide layer includes: the plasma enhanced chemical vapor deposition is carried out at a temperature below 200 ℃.
6. The manufacturing method according to claim 1, wherein the isotropic etching is performed using plasma etching.
7. The manufacturing method according to claim 6, wherein the plasma etching uses an etching gas including HBr and He, or uses an etching gas including oxygen.
8. The manufacturing method according to claim 1, wherein the anisotropic etching is performed using plasma etching whose etching gas includes fluorocarbon.
9. The manufacturing method of claim 1, further comprising, after the step of removing the photoresist pattern and the barrier layer, the steps of:
and etching the semiconductor substrate by using the gap wall as a mask, and transferring a pattern into the semiconductor substrate.
10. The manufacturing method of claim 1, wherein the step of forming a spacer on the sidewall of the photoresist pattern comprises the processes of:
conformally depositing a spacer material layer to cover the photoresist pattern, the barrier layer and part of the exposed surface of the semiconductor substrate;
and etching back to remove the spacer material layer on the top surface of the photoresist pattern and on part of the surface of the semiconductor substrate so as to form the spacer.
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